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ORCIDIntegration, Volume 18
Volume 18, Number 1, December 1994
- Leon Stok:
Data path synthesis. 1-71 - Jason Cong, Yuzheng Ding:
On nominal delay minimization in LUT-based FPGA technology mapping. 73-94 - Francis Depuydt, Gert Goossens, Hugo De Man:
Scheduling with register constraints for DSP architectures. 95-120 - George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos:
On the design of a high-performance, expandable, sorting engine. 121-135
Volume 18, Numbers 2-3, June 1995
- Sebastian T. J. Fenn, David Taylor, Mohammed Benaissa:
A dual basis bit-serial systolic multiplier for GF(2m). 139-149 - Kenneth J. Schultz, P. Glenn Gulak:
Architectures for large-capacity CAMs. 151-171 - Jing Lee, Jung-Hua Chou, Shen-Li Fu:
Reliability and wirability optimizations for module placement on a convectively cooled printed wiring board. 173-186 - Jamel M. Tahir, Satnam Singh Dlay, Raouf N. Gorgui-Naguib
, Oliver R. Hinton:
Fault tolerant arithmetic unit using duplication and residue codes. 187-200 - Bernd Becker, Ralf Hahn, Joachim Hartmann, Uwe Sparmann:
On the testability of iterative logic arrays. 201-218
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