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ORCIDIntegration, Volume 27
Volume 27, Number 1, January 1999
- S. Ramanathan, V. Visvanathan:
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1. 1-32 - Janett Mohnke, Paul Molitor
, Sharad Malik:
Establishing latch correspondence for sequential circuits using distinguishing signatures. 33-46 - Joseph L. Ganley, James P. Cohoon:
Provably good moat routing. 47-56 - Tetsushi Koide, Shin'ichi Wakabayashi:
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. 57-76 - Dimitri Kagaris, Spyros Tragoudas:
Maximum weighted independent sets on transitive graphs and applications1. 77-86
Volume 27, Number 2, July 1999
- Mehmet Emin Dalkiliç, Vijay Pitchumani:
Multi-schedule design space exploration: an alternative synthesis framework. 87-112 - Dirk Stroobandt, Jo Depreitere, Jan Van Campenhout:
Generating new benchmark designs using a multi-terminal net model. 113-129 - Ingmar Neumann, Hans-Ulrich Post:
Timing driven cell replication during placement for cycle time optimization. 131-141 - Michael Gallant, Dhamin Al-Khalili:
Synthesis of low-power CMOS circuits using hybrid topologies. 143-163 - Youxin Gao, D. F. Wong:
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. 165-178 - Ytong-Bin Kim, Tom W. Chen:
Assessing merged DRAM/Logic technology. 179-194
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