default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 49
Volume 49, March 2015
- Rabab Ezz-Eldin, Magdy A. El-Moursy, Hesham F. A. Hamed:
High Throughput Asynchronous NoC Design under High Process Variation. 1-13 - Rashad Ramzan, Jerzy J. Dabrowski:
RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique. 14-21 - Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari
, Massoud Pedram:
Design of NBTI-resilient extensible processors. 22-34 - MohammadSadegh Sadri, Andrea Bartolini, Luca Benini:
Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level. 35-48 - José Ricardo Cárdenas-Valdez, José-Cruz Nuñez Pérez, José Alejandro Galaviz-Aguilar, Andrés Calvillo-Téllez, Christian Gontrand, J. Apolinar Reynoso-Hernández, Esteban Tlelo-Cuautle:
Modeling memory effects in RF power amplifiers applied to a digital pre-distortion algorithm and emulated on a DSP-FPGA board. 49-64 - Nikolaos Kefalas, George Theodoridis:
A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter. 65-77 - Jin-Tai Yan:
Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs. 78-86 - Songwei Pei, Huawei Li, Song Jin, Jun Liu, Xiaowei Li:
An on-chip frequency programmable test clock generation and application method for small delay defect detection. 87-97 - Xiao Zhao, Huajun Fang, Tong Ling, Jun Xu:
Transconductance improvement method for low-voltage bulk-driven input stage. 98-103 - Anupama R. Subramaniam, Janet Roveda, Yu Cao:
Finite-point method for efficient timing characterization of sequential elements. 104-113 - Mariangela Genovese, Paolo Bifulco, Davide De Caro, Ettore Napoli, Nicola Petra, Maria Romano, Mario Cesarelli, Antonio G. M. Strollo:
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. 114-124 - Mozammel Hossain, Chirag Desai, Tom Chen, Vikas Agarwal:
Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design. 125-136
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-05 22:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
