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ORCIDIntegration, Volume 63
Volume 63, September 2018
- Desheng Zheng, Xiaoyu Li, Guowu Yang, Hai Wang, Lulu Tian:
An assertion graph based abstraction algorithm in GSTE and Its application. 1-8 - Cuauhtémoc R. Aguilera-Galicia, Omar Longoria-Gandara, Luis Pizano-Escalante, Javier Vázquez Castillo, Manuel Salim Maza:
On-chip implementation of a low-latency bit-accurate reciprocal square root unit. 9-17 - Vlastimil Kote, Adam Kubacak, Patrik Vacula, Jiri Jakovenko
, Miroslav Husák:
Automated pre-placement phase as a part of robust analog-mixed signal physical design flow. 18-30 - Taeyoung Kim, Sheldon X.-D. Tan, Chase Cook, Zeyu Sun:
Detection of counterfeited ICs via on-chip sensor and post-fabrication authentication policy. 31-40 - Roberto Sanchez Correa, Jean-Pierre David:
Ultra-low latency communication channels for FPGA-based HPC cluster. 41-55 - Even Låte, Trond Ytterdal, Snorre Aunet:
A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology. 56-63 - Mohamed Abbas, Ashraf Ramadan:
Low-cost methodology for fault diagnosis and localization in pipelined ADCs. 64-73 - Mahdi Shabany, Dimpesh Patel, Mario Milicevic, Mojtaba Mahdavi, P. Glenn Gulak:
A 70 pJ/b configurable 64-QAM soft MIMO detector. 74-86 - Yun Fang, Xiaopeng Yu, Zheng Shi, Kiat Seng Yeo:
A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS. 87-92 - Armin Mohammadjany, Ali Reza Hazeri, Hossein Miar Naimi:
Exact analyses for locking range in injection-locked frequency dividers. 93-100 - Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation. 101-114 - Manas Kumar Hati, Tarun Kanti Bhattacharyya:
Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops. 115-129 - Siavash Mowlavi, Aram Baharmast, Jafar Sobhi, Ziaddin Daei Koozehkanani:
A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier. 130-137 - Sameh Attia, Hossam A. H. Fahmy, Yehea Ismail, Hassan Mostafa:
Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources. 138-147 - Yongsuk Choi, Gyunam Jeon, Yong-Bin Kim:
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. 148-159 - Baixin Chen, Cheng Zhuo, Yiyu Shi:
A physics-aware methodology for equivalent circuit model extraction of TSV-inductors. 160-166 - Jun-Da Chen, Wen-Jun Wang:
A 1.5 ∼ 5 GHz CMOS broadband low-power high-efficiency power amplifier for wireless communications. 167-173 - Ankur Kumar, Rajendra Kumar Nagaria:
A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits. 174-184 - Nagapuri Srinivas, Gayadhar Pradhan, Puli Kishore Kumar:
An efficient hardware architecture for detection of vowel-like regions in speech signal. 185-195 - Xiaolong Lv, Xiao Zhao, Yongqing Wang, Dawei Jia:
Super class AB-AB bulk-driven folded cascode OTA. 196-203 - Amr Hassan, Hassan Mostafa, Hossam A. H. Fahmy:
NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA. 204-212 - Francesca Stradolini, Abuduwaili Tuoheti, Tugba Kilic, Danilo Demarchi, Sandro Carrara:
Raspberry-Pi based system for propofol monitoring. 213-219 - Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou:
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling. 220-231 - Zeinab Hijazi, Marco Grassi, Daniele D. Caviglia, Maurizio Valle:
Time-based calibration-less read-out circuit for interfacing wide range MOX gas sensors. 232-239 - Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake:
Analog perceptron circuit with DAC-based multiplier. 240-247 - Valerio Tenace, Andrea Calimera:
Quasi-exact logic functions through classification trees. 248-255 - Jonathan Calvillo, Ricardo Póvoa, Jorge Guilherme, Nuno Horta:
Second-order compensation BGR with low TC and high performance for space applications. 256-265 - Ali Ibrahim, Luigi Pinna, Maurizio Valle:
Experimental characterization of dedicated front-end electronics for piezoelectric tactile sensing arrays. 266-272 - Giulia Di Capua, Nuno Horta, Francisco V. Fernández, Günhan Dündar, Salvatore Pennisi, Gaetano Palumbo, Massimo Alioto, Gianluca Giustolisi:
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. 273-274 - Umberto Garlando, Fabrizio Riente, Giovanna Turvani, A. Ferrara, Giulia Santoro, Marco Vacca, Mariagrazia Graziano:
Architectural exploration of perpendicular Nano Magnetic Logic based circuits. 275-282 - Arianna Coccia, Saheed Tijani, Danilo Manstretta, Rinaldo Castello:
A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier. 283-290 - Sefa Özbek, Golzar Alavi, Johannes Digel, Markus Grözing, Joachim N. Burghartz, Manfred Berroth:
3-Path SiGe BiCMOS power amplifier on thinned substrate for IoT applications. 291-298 - Niccolo Lacaita, Matteo Bassi, Andrea Mazzanti, Francesco Svelto:
A K-band low-noise bipolar class-C VCO for 5G backhaul systems in 55 nm BiCMOS technology. 299-305 - Federica Resta, Simone Gerardin, S. Mattiazzo, Alessandro Paccagnella, Marcello De Matteis, Christian C. Enz, Andrea Baschirotto:
1GigaRad TID impact on 28 nm HEP analog circuits. 306-314 - Ali Abou Khalil, Maurizio Valle, Hussein Chible, Chiara Bartolozzi:
CMOS event-driven tactile sensor circuit. 315-322 - Nunzio Greco, Alessandro Parisi, Nunzio Spina, Egidio Ragonese, Giuseppe Palmisano:
Scalable lumped models of integrated transformers for galvanically isolated power transfer systems. 323-331 - Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández:
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator. 332-341 - Saverio Panarello, Claudia Triolo, F. Garesci, Salvatore Patanè, R. Denaro:
Improving ICs reliability with high speed thermal mapping. 342-350 - Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. 351-361 - Axel Hald, Pekka Herzogenrath, Jürgen Scheible, Jens Lienig, Johannes Seelhorst, Peter Brandl:
Full custom MEMS design: A new method for the analysis of motion-dependent parasitics. 362-372 - Philipp Tertel, Lars Hedrich:
Real-time emulation of block-based analog circuits on an FPGA. 373-382 - Georg Gläser, Martin Grabmann, Gerrit Kropp, Andreas Furtig:
There is a limit to everything: Automating AMS operating condition check generation on system-level. 383-391
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