default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroprocessing and Microprogramming, Volume 25
Volume 25, Numbers 1-5, January 1989
- Krzysztof Goczyla
:
A microcomputer database design. 3-7 - S. M. Kuo Pan, Yukio Kaneda:
A table oriented database-prolog system. 9-14 - Prem Malhotra, Rudolph E. Seviora:
Knowledge bases for digital circuit understanding. 15-20 - S. Grünwald:
The selection of expert system development environments. 21-26 - P. Grimaldi, A. Marcelli:
Toward a structured approach to expert system development. 27-32 - Naphtali Rishe, Doron Tal, Qiang Li:
Architecture for a massively parallel database machine. 33-38 - Luí de Sá, Jorge Dias, Vítor Silva:
Image processing system with multiple DSPs. 41-46 - M. Vlajnic, A. Purkovic, Z. Mladenovic, S. Nedic:
Universal DSP board. 47-50 - H. Bohr:
Supercomputer accelerator card for PC. 51-54 - Jürgen Kreyßig, Horst Schukat, Hans Christoph Zeidler, Hans Diel, Helmut Weber:
An intelligent disk controller - A processor system for file management and querry functions. 55-60 - K. Bruck, M. Griese, Ch. Jatho, A. S. Kirilov, V. I. Prikhodko:
Some computer graphics algorithms and their hardware realization. 61-64 - Ludo Cuypers:
Computer music programming. 65-69 - Wolfgang A. Halang:
Education of real-time systems engineers. 71-75 - P. Pardo, Yair Be'ery:
SPL - A different high level language for systolic processors. 79-83 - Fabrizio Lombardi, Donatella Sciuto:
Linear testability conditions for two-dimensional arrays. 85-90 - D. Tal, István Erényi, John Craig Comfort:
A fault-tolerant systolic data flow machine. 91-96 - G. L. Aranci, C. A. Binda, U. Clerici, E. Comignaghi:
A fault tolerant oriented CMOS systolic implementation of an FIR filter. 97-105 - J. Tasic, R. Sega:
Systolic arrays in adaptive digital filters. 107-112 - V. N. Doniants, V. G. Lazarev, R. Stefanelli:
Fault-tolerance of cellular processing arrays: Algorithmic methods for yield enhancement and reliability. 113-118 - Norbert Drescher:
A new microarchitecture based on a RISC like structure but with a CISC like instruction set. 121-125 - Antonio Núñez, Roberto Sarmiento, Pedro P. Carballo:
Some results in GaAs processor design using LSI integrated circuits. 127-132 - Patrick Abellard, B. Barbagelata:
A data flow numerical processing operator. 133-138 - Piotr Krzyzagórski:
Avoiding deadlock with a dual-port memory. 139-142 - V. Olman, R. Raud, A. Lepp:
Probability based timing verification. 143-148 - Gyula Csopaki:
Hardware description language for specification of digital systems. 151-155 - T. Grabowiecki, Adam Pawlak:
PROLOG as a formalism for VLSI design specification. 157-162 - Nikolaos G. Bourbakis, I. N. Savvides:
Geometric transformations for optimum VLSI layout placement. 163-170 - B. Hoppe:
Circuit optimization: Gate level modelling and multiobjective programming. 171-176 - Mustahsan Mir, M. H. Imam:
Optimal placement for hierarchical VLSI layout design. 177-182 - S. Gai, Antonio Lioy:
A multilevel hardware description language. 183-187 - Lambert Spaanenburg:
Design of a 1-chip IBM-3270 protocol handler. 189-194 - J. J. Narraway:
Probability machines. 197-201 - Borko Furht:
A contribution to classification and evaluation of structures for parallel computers. 203-208 - Eberhard Zehendner, Theo Ungerer:
A simulation method for parallel computer architectures. 209-212 - Mike P. Papazoglou, Adam Pawlak, Wlodzimierz Wrona:
Multiprocessor modelling: An example of object-oriented development. 213-219 - L. Tassakos, Klaus W. Plessmann:
pdvPool: A real-time object-oriented multiprocessor system. 221-227 - Edil Severiano Tavares Fernandes, C. L. de Amorim, Valmir C. Barbosa, Felipe M. G. França, A. F. de Souza:
MPH - A Hybrid Parallel Machine. 229-232 - Dong C. Shin, Song C. Moon:
A concurrency control scheme for nested transactions. 233-238 - B. De Decker, Pierre Verbaeten:
Modeling distributed systems: Communication issues in Hermix. 239-243 - N. Stanley Scott, Danny Crookes, Peter Milligan, P. L. Kilpatrick, Philip J. Morrow:
A case study in improving programming productivity on transputer networks. 247-251 - H. Zedan, R. F. Stone, D. S. Simpson:
PCHAN: A notion for dynamic resource management in distributed occam systems. 253-257 - Ermanno Di Zitti, Giacomo M. Bisio, Francesco Curatelli, Giancarlo Parodi:
High efficiency solution of triangular system equations on a 2-D array of transputers. 259-263 - Adriano Valenzano, Paolo Montuschi, Luigi Ciminiera:
Implementation of algorithms for graphic surface modeling using transputers. 265-270 - Alan Purvis, Ron W. Berry, Peter D. Manning:
A multi-transputer based audio computer with MIDI and analogue interfaces. 271-276 - Hermann Schomberg:
Image processing on a transputer-based perfect shuffle machine. 277-280 - T. J. Jackson, D. J. Mapps, Emmanuel C. Ifeachor, T. Donnelly:
A real-time transputer-based system for a digital recording data channel. 281-285 - E. Binaghi, Giacomo R. Sechi, Roberto Vaccaro, Lorenzo Verdoscia:
HCRC-Parallel computer: A massively parallel combined architecture supercomputer. 287-292 - Joshua Etkin:
The transition from network operating systems to distributed global operating systems: Do we stretch too much the real-time requirements? 295-300 - M. Ortega, José M. Troya:
Live nodes distribution in parallel branch and bound algorithms. 301-306 - Joshua Etkin, John A. Zinky:
Distributed debugging: Network analysis tools. 307-312 - Iztok Tvrdy:
Formal modelling of telematic services using LOTOS. 313-317 - Rumen Stainov, Ljudmil Manasiev:
A distributed communication service. 319-322 - Klaus-Jürgen Schulz:
Design and implementation of a portable communication transport system for unix network applications in C++. 323-326 - S. J. Nichols, R. T. Clarke, P. Mars:
Design of a high speed simulation tool for WAN using parallel processing. 327-331 - E. Carminati, A. Gandelli:
A parallel processor for the dynamic characterization of A/D converters. 335-339 - Nikolaos G. Bourbakis, Mike P. Papazoglou, S. H. Nguyen:
Design and simulation using Petri-Nets of a parallel WHT multiprocessor system. 341-346 - Sanja Vranes:
A heuristic algorithm for real-time application allocation to multimicrocomputer. 347-351 - R. Trobec, L. Gyergyek, J. Korenini:
Two-dimensional parallel system diagnostic. 353-358 - R. Adamov:
A naive approach to software structure validation. 361-365 - Monica Alderighi, A. Conni, Lauro Mantoani, Giacomo R. Sechi:
An automatic software generator in the design of reliable procedural programs. 367-373 - Tatjana Welzer, Ivan Rozman, József Györkös:
Automated normalization tool. 375-380 - Nelson Q. Vasconcelos, Edil S. T. Fernandes:
An environment for concurrent programming in Pascal. 381-386 - A. Bissett, J. Forrest:
An external data structure tool for pascal. 387-390
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-11 22:57 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
