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ORCIDMicroprocessing and Microprogramming, Volume 28
Volume 28, Numbers 1-5, March 1990
- Carlos Delgado Kloos, Gregorio González Martínez:
Expansion of LOTOS behaviour expressions as an exercise in transformational design. 3-8 - Dong C. Shin, Song C. Moon:
A deadlock detection algorithm for nested transaction model. 9-14 - Eberhard Zehendner, Matthias Haak:
Recent improvements on the concept of conditional critical regions. 15-18 - Michael Friedrich, Johann Zeiler:
Simulation of hardware and multitasking for the parallel programming language ParMod. 19-23 - Peter Milligan, T. J. G. Benson, N. S. Scott:
Towards the development of a mathematician's assistant. 25-29 - Vincenzo Piuri, Evgenij Tourouta:
Global optimisation of fault-tolerant allocation of concurrent communicating processes in distributed environments. 31-35 - Shyh-Chang Su, Prasenjit Biswas:
Scheduling demand-driven parallel logic programs on transputers. 37-41 - Geoffrey Muragori Macharia:
CLD: - A novel approach to dynamic load balancing. 43-47 - Wouter Joosen, Pierre Verbaeten:
On the use of process migration in distributed systems. 49-52 - Monika Kapus-Kolar:
Constructing communication protocols on reliable bounded FIFO channels without overspecification. 55-58 - Miyoshi Hanaki, Hidemi Murakami, Junzou Okunaka, Koki Miyazawa:
An interworking mechanism between LAN & WAN and implementation method. 59-62 - Fausto Distante, Vincenzo Piuri, Angelo Aliquo', Nicola Chiari, William Fornaciari
, Paolo Rastelli:
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description. 63-67 - Baruch Nissenbaum, Yair Be'ery:
Systool-systolic array programming tool. 69-73 - J. J. Narraway, Weimin Ma:
Probablistic diagnosis in multiprocessor systems. 75-78 - P. J. Venables, H. Zedan:
Debugging and monitoring highly parallel systems with grip. 79-84 - Adriano J. de O. Cruz:
Parallel algorithms for SIMD computers. 85-90 - B. Chardonnens, Roger D. Hersch, O. Kölbl:
Multiprocessor performances for dynamic programming. 91-94 - Viljem Zumer, Milan Ojstersek, Marjan Mernik, Peter Kokol:
Controlling industrial processes with a dataflow industrial controller: A way to achieve better performances. 95-99 - Zdenek Blazek:
Preliminary design of a parallel SIC architecture. 103-108 - M. Martinez, N. P. Cagigal, Salvador Bracho:
Arithmetical logical unit design for a processor with BILBO techniques: Functional simulation and test strategies. 109-115 - G. Leeuwrik, D. Richard Miller, Donna J. Quammen, R. Senko, Daniel Tabak:
Hardware design of the multris microprocessor. 117-122 - Wolfgang A. Halang, Soon-Key Jung:
A function oriented architecture for process control systems minimising internal data transfer costs. 123-128 - J.-F. Perotto, Christian Piguet, C. Voirol:
One-chip low-power multiprocessor. 129-132 - Miroslaw Szturmowicz, Marek S. Tudruj:
A multi-layer transputer network for efficient parallel execution of OCCAM programs. 133-138 - Fausto Distante, M. G. Sami, Renato Stefanelli, Giancarlo Storti Gajani:
Area compaction in silicon structures for neural net implementation. 139-143 - D. Raja, K. Shivakumar Srinivasan Rao, K. R. S. Murthy:
A portable real-time kernel for 8086/80186/80286/80386 based systems on IBM-PC. 145-150 - Jai P. Gupta, Padam Kumar, Stephen C. Winter, Derek R. Wilson:
Implementing pattern-matching function definitions in CTDNet - a multiprocessor architecture. 151-155 - Smaïl Niar, Gilles Goncalves, Bernard Toursel, Marie-Paule Lecouffe:
The evaluation of the N-arch emulator on a transputer network. 157-159 - Prasenjit Biswas, Jin Chen:
A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines. 161-166 - Naomi Fujimura:
Software productivity in built-in microprocessors. 169-172 - Monica Alderighi, Erneto Bussola, Sergio D'Angelo, Lauro Mantoani, Giacomo R. Sechi:
Computing models in designing. 173-177 - Nikolay S. Bukovsky:
Building an expert system for software quality evaluation. 179-182 - Dimitris N. Christodoulakis, Christos Tsalidis:
Design principles of the ATHENA software maintainability toll. 183-189 - P. Grimaldi, A. Marcelli:
A structured approach to expert systems development: The methodology and a real world case study. 191-196 - Harry Bretthauer, Thomas Christaller, Jürgen Kopp:
Multiple vs. single inheritance in object-oriented programming languages. 197-200 - Giacomo Bucci, Roberto Cecchini, Alberto Del Bimbo:
CSL: A class specification language for object-oriented design. 201-204 - Lutz Pietschker:
Grammar controlled specification and design of program systems. 205-209 - R. Cobelli, L. Mezzalira, G. F. Navoni, Nello Scarabottolo:
Real time scheduling algorithms and their performances. 211-216 - U. Varchmin, T. Hirschberg, D. Neumann:
An engine signal simulator. 219-222 - P. Strickland, Fazel Naghdy, J. Hollis, John Billingsley:
Automatic reconfigurable transputer networks - A new direction in parallel processing for robotic applications. 223-228 - U. Minomi, G. Sansoni:
Relationships between real-time and fault tolerance: A case study of a redundant loop data acquisition network. 229-232 - Anna Z. Baraniecki:
Concurrent architectures for real-time signal processing. 233-238 - D. Crookes, D. K. Freeman, C. D. Gostling:
Improving DSP software productivity using an optimising Pascal compiler for the AT&T DSP32C. 239-242 - K. Parthenis, Christina Metaxaki-Kossionides, B. Dimitriadis:
An automatic computer vision system for blood analysis. 243-246 - Stavros A. Karkanis, Christina Metaxaki-Kossionides, B. Dimitriadis:
A machine-vision quality inspection system for textile industries supported by parallel multitransputer architecture. 247-252 - Maurizio Morisio, Riccardo Sisto:
The use of Estelle to specify manufacturing systems. 253-258 - Cyrille Comar, Panayiotis E. Pintelas:
An environment for teaching "program design" by exercises. 259-264 - Borislav K. Slavov, Atanas I. Terziev:
Tools for logic-based access to existing databases in distributed environment. 265-268 - J. Vogwell, Steve J. Culley, J. Armour:
The design of open structure engineering databases. 269-273 - Sergio Bampi:
An experiment on PC-based automated extraction of electrical parameters for VLSI MOSFETs: Methods, algorithms, and implementation. 277-282 - Luca Breveglieri, Luigi Dadda, Donatella Sciuto:
Testing of serial input convolvers. 283-290 - Peter Spanier, Hans Wojtkowiak, Karl B. Eisner:
Transforming logic simulator output to tester timing descriptions. 291-294 - Krzysztof Kuchcinski, Zebo Peng:
Testability analysis in a VLSI high-level synthesis system. 295-300 - Alfonso Sotelo, Julio Septién, Román Hermida, Milagros Fernández:
An approach to minimal-time scheduling of micro-operations. 301-304 - Björn Fjellborg:
A general framework for extraction of VLSI pipeline structures. 305-310 - T. Hollant, B. Petitprez:
An object oriented logic simulator. 311-313 - Stefan Rust:
An overview of the sysedit chip design environment. 315-318 - Uwe Wienkop:
A new concept for chip architecture design - Interactive architecture compilation from system specification to register-transfer algorithms. 319-322 - Mikael R. K. Patel:
TAO: A hierarchical design representation for high level synthesis of hardware systems. 323-326 - Michael I. Loupis, G. D. Tziallas:
A knowledge-based framework for VLSI design. 327-331
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