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ORCIDMicroprocessing and Microprogramming, Volume 29
Volume 29, Number 1, July 1990
- Andrea Bobbio
:
Dependability analysis of fault-tolerant systems: a literature survey. 1-13 - Javier D. Bruguera, Emilio L. Zapata, Oscar G. Plata:
A reliability model for multiprocessor networks with degradable nodes. 15-25 - P. P. Meiler, Ad J. van de Goor:
The Delft test system. 27-41 - M. M. A. Shahin:
Microcomputer technique for optimum design of centrifugal pumps. 43-51 - Weng-Fai Wong, K. T. Lua:
A preliminary evaluation of a massively parallel processor: GAPP. 53-62
Volume 29, Number 2, September 1990
- Cevdet Aykanat, Füsun Özgüner, D. S. Scott:
Vectorization and parallelization of the conjugate gradient algorithm on hypercube-connected vector processors. 67-82 - Alberto R. Cunha, José A. Marques:
Performance evaluation of a distributed architecture. 83-96 - K. T. Lua:
Failure of instruction prefetching of 8088/286/ 386 microprocessors in XT/AT systems. 97-106 - Lionel C. Waring:
A general purpose communications shell for a network of transputers. 107-119 - Emilio L. Zapata, Francisco Argüello, Francisco Fernandez Rivera, Javier D. Bruguera:
Multidimensional fast Hartley transform onto SIMD hypercubes. 121-134
Volume 29, Number 3, October 1990
- R. G. Adams, Sue M. Gray, Gordon B. Steven:
Utilising low level parallelism in general purpose code: the HARP project. 137-149 - Vaclav Dvorak:
A cascade implementation of digital systems. 151-163 - Ad J. van de Goor, O. Jansen:
Self test for the Intel 8085. 165-175 - Karl C. Posch, Reinhard Posch:
Approaching encryption at ISDN speed using partial parallel modulus multiplication. 177-184 - Hyunsoo Yoon, Jong H. Nang, Seung Ryoul Maeng:
Parallel simulation of multilayered neural networks on distributed-memory multiprocessors. 185-195
Volume 29, Number 4, December 1990
- Cristian Constantinescu:
A perfomability approach to the cost minimization of a class of gracefully degrading computer systems. 199-204 - Hao-Yung Lo:
High-speed signed digital multipiers for VLSI. 205-215 - Parag K. Lala:
A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips. 217-223 - J. Mohan Kumar, L. M. Patnaik, Divya K. Prasad:
A transputer-based extended hypercube. 225-236 - Luca Pistolesi, Marco Spadoni, Marco Gori:
Performance analysis of tightly-coupled multiprocessor minicomputers. 237-246 - Fleur L. Williams, Gordon B. Steven:
How useful are complex instructions? A case study using the M68000. 247-259
Volume 29, Number 5, March 1991
- J. Alonso, M. Caresana, A. Lanza, Fivos Panetsos, J. Rios:
A DSP based board for neural network simulation. 263-271 - C. Barmon, M. N. Faruqui, G. P. Battacharjee:
Dynamic load balancing algorithm in a distributed system. 273-285 - Ghulam M. Chaudhry, J. S. Bedi:
Performance of tightly-coupled systems with shared cache. 287-292 - Veselko Gustin, Andrej Dobnikar:
Realization of multilayer Boolean neural networks with logic gate array. 293-302 - Christos A. Papachristou, Satnamsingh B. Gambhir:
Microcontrol architectures with sequencing firmware and modular microcode development tools. 303-328
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