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ORCIDMicroprocessing and Microprogramming, Volume 37
Volume 37, Numbers 1-5, January 1993
- Antonio Núñez
, Don Fay:
Letter from the short notes editors, Euromicro '92. v - Xiaoming Fan, Klaus Lagemann:
Experiences and results in designing VLSI-chips using standard-cell techniques. 3-6 - Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana:
CMOS interconnect modelling for timing analysis. 7-10 - Jean-François Naviner, Jean-Claude Dufourd:
Préforme/aGAPE: a synergy between symbolic cell design and assembly. 11-14 - C. W. Cheng, C. K. Li, P. K. Kung:
A nonlinear 3D MOSFET table for VLSI circuit simulation. 15-18 - Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri:
A delay insensitive approach to the VLSI design of a DRAM controller. 19-22 - Antonio Hernández, Luis Gómez, Antonio Núñez:
An empirical model to estimate power consumption in GaAs DCFL/SDCFL circuits. 23-26 - S. A. Rea, Peter Milligan, R. K. McConnell, L. A. Murphy, J. Pelan:
An investigation of the performance characteristics of an i860 processor within a Meiko computing surface. 29-32 - Roger D. Hersch:
Distributing pixmap images among parallel disk arrays. 33-36 - Dae-Wha Seo, Jung Wan Cho:
Directory-based cache coherence scheme using number-balanced binary tree. 37-40 - Daniel Meziat, J. Sequeiros, Julio L. Medina, Sebastián Sánchez:
CDPU for SOHO-CEPAC collaboration. 41-44 - Milivoje Aleksic, Mladena Novakovic, Aleksandar Car, Jelica Protic:
CISC versus RISC processors for graphics: A simulation study. 45-48 - Juan A. Montiel-Nelson, Valentin de Armas, D. Q. M. Fay:
An OCCAM circle generator program implemented in VLSI. 49-54 - D. E. Metafas, Spiridon Nikolaidis, Constantinos E. Goutis:
Real time Cepstrum computation based on an Advanced CORDIC processor. 57-60 - Ferenc Vajda:
Implementation issues of image texture analysis and segmentation. 61-64 - Peter Milligan, T. J. G. Benson, R. K. McConnell, Alan Rea:
Detecting components for parallel execution within the Mathematician's Devil. 65-68 - F. Moreno, S. Alexandres, J. Meneses:
A flexible architecture for real-time speech recognition. 69-72 - P. J. Davey, T. Donnelly, D. J. Mapps:
Pulse slimming in magnetic recording using digital signal processing techniques. 73-76 - Zdenek Blazek:
Two-processor monitoring system for airplanes. 77-80 - Ignacio Aedo, Fivos Panetsos, A. Ribagorda:
Hypertextual applications development tools. 81-84 - Xiaoming Fan:
Analysis of multithreaded architectures - A case study. 87-90 - Krzysztof Kuchcinski:
System level modelling and analysis of complex digital systems. 91-94 - Daniel Mozos, Julio Septién, Francisco Tirado, Milagros Fernández:
Guidance for optimization-based synthesis tools. 95-98 - Dagung Lu, Prasenjit Biswas:
An extended scheduling technique for software pipelining. 99-103 - Pedro P. Carballo, Roberto Sarmiento, Antonio Núñez:
Integer and control units for a GaAs 32-bit RISC processor. 105-108 - Krista Rizman, Ivan Rozman:
Facilitating composition and increasing object reusability by means of an event-driven object-oriented development. 111-114 - Haengrae Cho, Songchun Moon:
CADTM: A database transaction manager for coordinating design activities in CAD environments. 115-118 - Haengrae Cho, Yoo-Sung Kim, Songchun Moon:
Development of an autonomous heterogeneous distributed database system: DHIM. 119-122 - Marjeta Pucko, Monika Kapus-Kolar, Joze Rugelj:
Developing multi-user interfaces for CSCW environment. 123-126 - Wojciech Cellary, Waldemar Wieczerzycki:
On hierarchical locking of composite objects. 127-130 - Andreas Weininger:
Source - A debugging tool for ParMod. 133-136 - Paul Sage, Peter Milligan, R. K. McConnell, S. A. Rea:
Graph management within the Fortport migration environment (including comments on the use of objectstore). 137-140 - R. K. McConnell, Paul Sage, S. A. Rea, P. J. P. McMullan:
Hot spot analysis within the FortPort migration tool for parallel platforms. 141-144 - Simon J. E. Taylor, Nasser Kalantery, Stephen C. Winter, Derek R. Wilson, A. P. Redfern:
Developments in parallel discrete event simulation at the centre for parallel computing. 145-148 - Marek S. Tudruj:
Dynamically reconfigurable multi-transputer systems with serial bus control. 149-152 - Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri:
Design of a massively parallel SIMD architecture for the Boltzmann machine. 153-156 - Rafael Dueire Lins, Bruno O. Lira:
ΓCMC: Fast lazy functional languages. 159-162 - Rafael Dueire Lins, Patricia G. Soares:
Some performance figures for the G-Machine and its optimisations. 163-166 - Petr Kroha:
Translation of a query in OODBMS into a system of parallel tasks. 167-170 - Kam-Wing Ng, Chi-Keung Luk:
The design of a multiparadigm programming language: I. 171-173 - Carol Britton, Martin J. Loomes, Richard J. Mitchell:
Formal specifications as constructive diagrams. 175-178 - Andrea Clematis, Vittoria Gianuzzi:
A hierarchical program structure for concurrent fault tolerant software. 179-182 - Juan López, Alfonso Gago:
A parallel algorithm for the Jacobian matrix of a manipulator. 183-186 - Iztok Savnik, Tomaz Mohoric, Tomi Dolenc, Franc Novak:
Modelling dynamic dependencies by functional database model. 187-190 - Miroslav Svéda:
Small area network interconnection. 193-196 - Arthur I. Karshmer, Renwei Yan:
A CATV based metropolitan area network using distributed switching. 197-200 - Jelica Protic, Milivoje Aleksic:
An example of the efficient message protocol for industrial LAN. 201-204 - Jan Janecek, Stefan Jedlik, Michal Meloun:
Effectiveness of bridging in multiprotocol LANS. 205-208 - Gerd vom Bögel, K. Scherer, M. Bollerott:
An optimized architecture for a rapid-prototype-emulator. 211-214 - Serafín Pérez, Enrique Mandado, Jacobo Ruiz de Ojeda:
Logic controllers design methods using advanced PLDS. 215-219 - Ricardo de Oliveira Duarte, Edil S. T. Fernandes, Antonio Carneiro de Mesquita Filho, Ana L. V. Azevedo:
Configurable cells: Towards dynamic architectures. 221-224
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