default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Journal of Solid-State Circuits, Volume 35
Volume 35, Number 1, January 2000
- Raúl Andrés Bianchi, Jean-Michel Karam, Bernard Courtois:
Analog ALC crystal oscillators for high-temperature applications. 2-14 - Hooman Darabi, Asad A. Abidi:
Noise in RF-CMOS mixers: a simple physical model. 15-25 - Gabriel A. Rincón-Mora:
Active capacitor multiplier in Miller-compensated circuits. 26-32 - J. Francisco Duque-Carrillo
, José L. Ausín, Guido Torelli, José M. Valverde, Miguel Angel Domínguez:
1-V rail-to-rail operational amplifiers in standard CMOS technology. 33-44 - Chenghung James Pan:
A stereo audio chip using approximate processing for decimation and interpolation filters. 45-55 - Pierte Roo, Richard R. Spencer, Paul J. Hurst:
A CMOS analog timing recovery circuit for PRML detectors. 56-65 - Naoki Harada, Akira Watanabe, Yuji Awano, Kohki Hikosaka, Naoki Yokoyama:
A multigigahertz Josephson-semiconductor interface circuit using 77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltage driver for superconductor-semiconductor electronic hybrid systems. 66-73 - Jong-Seok Kim, Deog-Kyoon Jeong, Gyudong Kim:
A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers. 74-84 - Richard C. Jaeger, Jeffrey C. Suhling, Ramanathan Ramani, Arthur T. Bradley, Jianping Xu:
CMOS stress sensors on [100] silicon. 85-95 - Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, Salvatore Levantino, Giovanni Calí:
Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. 96-99 - Chih-Ming Hung, Kenneth K. O:
A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset. 100-103 - Paolo Orsatti, Francesco Piazza, Qiuting Huang:
A 71-MHz CMOS IF-baseband strip for GSM. 104-108 - Liang Dai, Ramesh Harjani:
CMOS switched-op-amp-based sample-and-hold circuit. 109-113 - Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao:
Single-ended SRAM with high test coverage and short test time. 114-118 - Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li:
Low-power embedded SRAM with the current-mode write technique. 119-124 - Wei Hwang, Rajiv V. Joshi, George Gristede:
A scannable pulse-to-static conversion register array for self-timed circuits. 125-128 - Kush Gulati, Hae-Seung Lee:
Corrections to "a high-swing CMOS telescopic operational amplifier". 129
Volume 35, Number 2, February 2000
- Fenghao Mu, Christer Svensson:
Pulsewidth control loop in high-speed CMOS clock buffers. 134-141 - Peter Hazucha, Christer Svensson:
Optimized test circuits for SER characterization of a manufacturing process. 142-148 - Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda:
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. 149-162 - Takeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi:
Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. 163-174 - Bharadwaj S. Amrutur, Mark A. Horowitz:
Speed and power scaling of SRAM's. 175-185 - Christian C. Enz, Yuhua Cheng:
MOS transistor modeling for RF IC design. 186-201 - Bruno Stefanelli, Ian O'Connor, Laurent Quiquerez, Andreas Kaiser, Daniel Billet:
An analog beam-forming circuit for ultrasound imaging using switched-current delay lines. 202-211 - Un-Ku Moon:
CMOS high-frequency switched-capacitor filters for telecommunication applications. 212-220 - Ka Nang Leung, Philip K. T. Mok, Wing-Hung Ki, Johnny K. O. Sin:
Three-stage large capacitive load amplifier with damping-factor-control frequency compensation. 221-230 - Brian M. Ballweber, Ravi Gupta, David J. Allstot:
A fully integrated 0.5-5.5 GHz CMOS distributed amplifier. 231-239 - Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield:
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. 240-247 - Wei-Shinn Wey, Yu-Chung Huang:
A CMOS delta-sigma true RMS converter. 248-257 - Koichi Murata, Taiichi Otsuji, Yuhki Imai, Suehiro Sugitani:
A distributed selector IC using GaAs MESFET's with multilayer-interconnection structure. 258-267 - Eduard Säckinger, Yusuke Ota, Thaddeus J. Gabara, Wilhelm C. Fischer:
A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection. 269-275 - Shen-Iuan Liu, Chien-Hung Kuo, Ruey-Yuan Tsai, Jingshown Wu:
A double-sampling pseudo-two-path bandpass ΔΣ modulator. 276-280 - Ion E. Opris, Bill C. Wong, Sing W. Chin:
A pipeline A/D converter architecture with low DNL. 281-285 - HongMo Wang, Ali Hajimiri, Thomas H. Lee:
Comments on "Design issues in CMOS differential LC oscillators" [and reply]. 286-287
Volume 35, Number 3, March 2000
- Doug Garrity, Larry Starr:
Guest editorial. 294-296 - Eric Fogleman, Ian Galton, William Huff, Henrik Jensen:
A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR. 297-307 - Yun-Ti Wang, Behzad Razavi:
An 8-bit 150-MHz CMOS A/D converter. 308-317 - Iuri Mehr, Larry Singer:
A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC. 318-325 - Thomas H. Lee, Ali Hajimiri:
Oscillator phase noise: a tutorial. 326-336 - Alain-Serge Porret, Thierry Melly, Christian C. Enz, Eric A. Vittoz:
Design of high-Q varactors for low-power wireless applications using a standard CMOS process. 337-345 - Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee:
Bandwidth extension in CMOS with optimized on-chip inductors. 346-355 - Francesco Svelto, Stefano Deantoni, Rinaldo Castello:
A 1.3 GHz low-phase noise fully tunable CMOS LC VCO. 356-361 - Srinath Sridharan, L. Richard Carley:
A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbi detector for disk drive read channels. 362-370 - Michael S. Kappes:
A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications. 371-376 - Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. 377-384 - Abdellatif Bellaouar, Michael S. O'brecht, Amr M. Fahim, Mohamed I. Elmasry:
Low-power direct digital frequency synthesis for wireless communications. 385-390 - Ji-Ning Duan, Li-Jen Ko, Babak Daneshrad:
A highly versatile beamforming ASIC for application in broad-band fixed wireless access systems. 391-400 - Paul T. Capozza, Brian J. Holland, Thomas M. Hopkinson, Roberto L. Landrau:
A single-chip narrow-band frequency-domain excisor for a Global Positioning System (GPS) receiver. 401-411 - Bryan D. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, Asawaree Kalavade, J. Knobloch, E. Micca, M. Moturi, Chris J. Nicol, Jay H. O'Neill, Joe Othmer, Eduard Sackinger, Kanwar Jit Singh, J. Sweet, C. J. Terman, Joseph Williams:
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP. 412-424 - Steven Winegarden:
Bus architecture of a system on a chip with user-configurable system logic. 425-433 - Ilhami Torunoglu, Edoardo Charbon:
Watermarking-based copyright protection of sequential functions. 434-440 - Joop P. M. Van Lammeren, Roy W. B. Wissing:
Mixed-signal quadrature demodulator with a multicarrier regeneration system. 441-445 - Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Peter Holzmann, Oliver C. Kao, Carl R. Palmer, Aditya Raina, Chun Mai-Liu, Albert V. Kordesch:
An analog record, playback, and processing system on a chip for mobile communications devices. 446-449 - Hee-Tae Ahn, David J. Allstot:
A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications. 450-454
Volume 35, Number 4, April 2000
- Prabir C. Maulik, Mandeep S. Chadha, Wai L. Lee, Philip J. Crawley:
A 16-bit 250-kHz delta-sigma modulator and decimation filter. 458-467 - Lucien J. Breems, Eric J. van der Zwan, Johan H. Huijsing:
A 1.8-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion of IF signals. 468-475 - Farbod Behbahani, Weeguan Tan, Ali Karimi-Sanjaani, Andreas Roithmeier, Asad A. Abidi:
A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver. 476-489 - Cicero S. Vaucher:
An adaptive PLL tuning system architecture combining high spectral purity and fast settling time. 490-502 - Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Widely programmable high-frequency continuous-time filters in digital CMOS technology. 503-511 - Frank D. Bannon, John R. Clark, Clark T.-C. Nguyen:
High-Q HF microelectromechanical filters. 512-526 - Chien-Chang Liu, Carlos H. Mastrangelo:
A CMOS uncooled heat-balancing infrared imager. 527-535 - Takeshi Ikenaga, Takeshi Ogura:
A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing. 536-544 - Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka:
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. 545-551 - Oliver Weinfurtner, Daniel W. Storaska, Louis Hsu:
Advanced controlling scheme for a DRAM voltage generator system. 552-563 - Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. 564-571 - Thomas Simon, Anantha P. Chandrakasan:
An ultra low power adaptive wavelet video encoder with integrated memory. 572-582 - Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng:
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. 583-592 - Andre G. Metzger, Charles E. Chang, Ken D. Pedrotti, Steve M. Beccue, Keh-Chung Wang, Peter M. Asbeck:
A 10-Gb/s high-isolation, 16×16 crosspoint switch implemented with AlGaAs/GaAs HBT's. 593-600 - Ming-Dou Ker, Wen-Yu Lo:
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process. 601-611 - Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram, Chenming Hu:
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design. 612-624 - Ruchir Puri, Ching-Te Chuang:
Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits. 625-631 - Gianluca Giustolisi, Giuseppe Palmisano, T. Segreto:
1.2-V CMOS op-amp with a dynamically biased output stage. 632-636 - Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider:
Digitally programmable switched-current FIR filter for low-voltage applications. 637-641 - Siamak Mortezapour, Edward K. F. Lee:
A 1-V, 8-bit successive approximation ADC in standard CMOS process. 642-646 - Bang-Sup Song, Patrick L. Rakers, Steven F. Gillig:
A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC. 647-651 - Tadahiro Kuroda, Mototsugu Hamada:
Low-power CMOS digital design with dual embedded adaptive power supplies. 652-655 - Anders Berkeman, Viktor Öwall, Mats Torkelson:
A low logic depth complex multiplier using distributed arithmetic. 656-659 - Ahmad B. Dowlatabadi:
A robust, load-insensitive pad driver. 660-665
Volume 35, Number 5, May 2000
- Masao Taguchi, David B. Scott:
Guest editorial. 670-671 - Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui:
A source-line programming scheme for low-voltage operation NAND flash memories. 672-681 - Hiromi Nobukata, Shunsuke Takagi, Keizo Hiraga, Takeshi Ohgishi, Masaru Miyashita, Kazuto Kamimura, Shinji Hiramatsu, Kiyohisa Sakai, Takahiro Ishida, Hideki Arakawa, Masahiko Itoh, Ihachi Naiki, Masanori Noda:
A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming. 682-690 - Georg Braun, Heinz Hoenigschmid, Tobias Schlager, Werner Weber:
A robust 8F2 ferroelectric RAM cell with depletion device (DeFeRAM). 691-696 - Yeonbae Chung, Byung-Gil Jeon, Kang-Deog Suh:
A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme. 697-704 - Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata:
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. 705-712 - Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman:
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. 713-718 - Christl Lauterbach, Werner Weber, Dirk Romer:
Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps. 719-723 - Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida:
A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors. 724-731 - Tarek Lulé, Michael Wagner, Marcus Verhoeven, Holger Keller, Markus Böhm:
100000-pixel, 120-dB imager in TFA technology. 732-739 - Thucydides Xanthopoulos, Anantha P. Chandrakasan:
A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. 740-750 - Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara:
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. 751-756 - Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. 757-764 - Hirad Samavati, Hamid R. Rategh, Thomas H. Lee:
A 5-GHz CMOS wireless LAN receiver front end. 765-772 - Wallace Ming Yip Wong, Ping Shing Hui, Zhiheng Chen, Keqiang Shen, Jack Lau, Philip C. H. Chan, Ping Keung Ko:
A wide tuning range gated varactor. 773-779 - Hamid R. Rategh, Hirad Samavati, Thomas H. Lee:
A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver. 780-787 - Christopher Lam, Behzad Razavi:
A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology. 788-794
Volume 35, Number 6, June 2000
- Angelo Nagari, Alessandro Mecchia, Ermes Viani, Sergio Pernici, Pierangelo Confalonieri, Germano Nicollini:
A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications. 798-806 - Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim:
A low-noise phase-locked loop design by loop bandwidth optimization. 807-815 - Xiaodong Wang, Richard R. Spencer:
A CMOS two-path tree search detector. 816-825 - Yun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi:
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder. 826-834 - Hugh Mair, Liming Xiu:
An architecture of high-performance frequency and phase synthesis. 835-846 - Hormoz Djahanshahi, C. André T. Salama:
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications. 847-855 - Won Namgoong, Sydney Reader, Teresa H. Meng:
An all-digital low-power IF GPS synchronizer. 856-864 - Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae:
nMOS reversible energy recovery logic for ultra-low-energy applications. 865-875 - Borivoje Nikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, Michael Ming-Tak Leung:
Improved sense-amplifier-based flip-flop: design and measurements. 876-884 - Steven R. Carlough, Robert A. Philhower, Cliff A. Maier, Sam A. Steidl, Pete M. Campbell, Atul Garg, Kyung-Suc Nah, Matthew W. Ernest, James R. Loy, Thomas W. Krawczyk Jr., Peter F. Curran, Russell P. Kraft, Hans J. Greub, John F. McDonald:
A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip. 885-894 - Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for design of mixed-signal IC's. 895-904 - Pietro Andreani, Sven Mattisson:
On the use of MOS varactors in RF VCOs. 905-910 - Indumini Ranmuthu, Paul M. Emerson, Ken Maggio, Hong Jiang, Ashish Manjekar, Bryan E. Bloodworth, Mark Guastaferro:
A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives. 911-914 - Gijung Ahn, Deog-Kyoon Jeong, Gyudong Kim:
A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission. 915-918 - Ki-Hyuk Sung, Lee-Sup Kim:
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". 919-920 - Un-Ku Moon:
Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications". 920 - Brian M. Ballweber, Ravi Gupta, David J. Allstot:
Correction to "A fully integrated 0.5 - 5.5-GHz CMOS distributed amplifier". 921
Volume 35, Number 7, July 2000
- Stephen H. Lewis:
New associate editor [Editor]. 928 - Michael Schanz, Christian Nitta, Arndt Bußmann, Bedrich J. Hosticka, Reiner K. Wertheimer:
A high-dynamic-range CMOS image sensor for automotive applications. 932-938 - Stephan Benthien, Tarek Lulé, Bernd Schneider, Michael Wagner, Markus Verhoeven, Markus Böhm:
Vertically integrated sensors for advanced imaging applications. 939-945 - Willm Hinrichs, Jens Peter Wittenburg, Hanno Lieske, Helge Kloos, Martin Ohmacht, Peter Pirsch:
A 1.3-GOPS parallel DSP for high-performance image-processing applications. 946-952 - Cathleen Rooman, Daniël Coppée, Maarten Kuijk:
Asynchronous 250-Mb/s optical receivers with integrated detector in standard CMOS technology for optocoupler applications. 953-958 - Roberto Maurino, Peter Mole:
A 200-MHz IF 11-bit fourth-order bandpass ΔΣ ADC in SiGe. 959-967 - James C. Morizio, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya:
14-bit 2.2-MS/s sigma-delta ADC's. 968-976