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ORCIDIEEE Journal of Solid-State Circuits, Volume 43
Volume 43, Number 1, January 2008
- David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra:
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. 3-5 - Umesh Gajanan Nawathe, Mahmudul Hassan, King C. Yen, Ashok Kumar, Aparna Ramachandran, David Greenhill:
Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip. 6-20 - Benjamin Stolt, Yonatan Mittlefehldt, Sanjay Dubey, Gaurav Mittal, Mike Lee, Joshua Friedrich, Eric Fluhr:
Design and Implementation of the POWER6 Microprocessor. 21-28 - Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar:
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. 29-41 - José A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman:
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. 42-51 - Ron Ho, Tarik Ono, Robert David Hopkins, Alex Chow, Justin Schauer, Frankie Y. Liu, Robert J. Drost:
High Speed and Low Energy Capacitively Driven On-Chip Wires. 52-60 - Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor:
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. 61-68 - Ying Su, Jeremy Holleman, Brian P. Otis:
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations. 69-77 - Carlos Tokunaga
, David T. Blaauw, Trevor N. Mudge:
True Random Number Generator With a Metastability-Based Quality Control. 78-85 - John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. 86-95 - Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. 96-108 - Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno:
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. 109-120 - Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Sunghoon Kim, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim, Soo-In Cho:
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. 121-131 - Corrado Villa, Daniele Vimercati, Stefan Schippers, Salvatore Polizzi, Andrea Scavuzzo, Maurizio Perroni, Maurizio Gaibotti, Mauro Luigi Sali:
A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface. 132-140 - Naveen Verma, Anantha P. Chandrakasan:
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy. 141-149 - KwangJin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hyung-Rok Oh, Changsoo Lee, Hye-Jin Kim, Joon-min Park, Qi Wang, Mu-Hui Park, Yu-Hwan Ro, Joon-Yong Choi, Ki-Sung Kim, Young-Ran Kim, In-Cheol Shin, Ki-won Lim, Ho-Keun Cho, ChangHan Choi, Won-ryul Chung, Du-Eung Kim, Yong-Jin Yoon, Kwang-Suk Yu, Gi-Tae Jeong, Hong-Sik Jeong, Choong-Keun Kwak, Chang-Hyun Kim, Kinam Kim:
A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput. 150-162 - Juergen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel:
Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. 163-171 - Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr:
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. 172-179 - Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara:
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. 180-191 - Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers:
Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. 192-201 - Brucek Khailany, Ted Williams, Jim Lin, Eileen Peters Long, Mark Rygh, DeForest Tovey, William J. Dally:
A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. 202-213 - Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar:
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. 214-222 - Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens:
A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. 223-235 - Markus Hammes, Christian Kranz, Dietolf Seippel, Jens Kissing, Andreas Leyk:
Evolution on SoC Integration: GSM Baseband-Radio in 0.13 µm CMOS Extended by Fully Integrated Power Management Unit. 236-245 - Hélène Lhermet, Cyril Condemine, Marc Plissonnier, Raphael Salot, Patrick Audebert, Marion Rosset:
Efficient Power Management Circuit: From Thermal Energy Harvesting to Above-IC Microbattery Energy Storage. 246-255 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
Minimum Energy Tracking Loop With Embedded DC-DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS. 256-265 - Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations. 266-274 - Alberto Fazzi, Roberto Canegallo, Luca Ciccarelli, Luca Magagni, Federico Natali, Erik Jung, Pier Luigi Rolandi, Roberto Guerrieri:
3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities. 275-284 - Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. 285-291 - Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, Hiroyuki Takashina, Yoshinari Yamashita, Shunpei Yamazaki:
UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems. 292-299 - Shailesh Rai, Brian P. Otis:
A 600 µW BAW-Tuned Quadrature VCO Using Source Degenerated Coupling. 300-305
Volume 43, Number 2, February 2008
- Bram Nauta:
New Associate Editor. 311 - Luca Picolli, Andrea Rossini, Piero Malcovati, Franco Maloberti, Fausto Borghetti, Andrea Baschirotto:
A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors. 312-320 - Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo:
A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications. 321-329 - Tongyu Song, Zhiheng Cao, Shouli Yan:
A 2.7-mW 2-MHz Continuous-Time ΣΔ Modulator With a Hybrid Active-Passive Loop Filter. 330-341 - Yun-Shiang Shu, Bang-Sup Song:
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering. 342-350 - Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar:
A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. 351-360 - Jeongjin Roh, San-Ho Byun, Youngkil Choi, Hyungdong Roh, Yi-Gyeong Kim, Jong-Kee Kwon:
A 0.9-V 60-µW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range. 361-370 - Chih-Wen Lu, Lung-Chien Huang:
A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters. 371-378 - Kyoungho Woo, Yong Liu, Eunsoo Nam, Donhee Ham:
Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths. 379-389 - Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu:
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems. 390-398 - Kuo-Hsing Cheng, Chia-Wei Su, Kai-Fei Chang:
A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. 399-413 - Pavan Kumar Hanumolu, Volodymyr Kratyuk, Gu-Yeon Wei, Un-Ku Moon:
A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. 414-424 - Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon:
A Wide-Tracking Range Clock and Data Recovery Circuit. 425-439 - Jun-De Jin, Shawn S. H. Hsu:
A 0.18-µm CMOS Balanced Amplifier for 24-GHz Applications. 440-445 - Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A Low-Power SRAM Using Bit-Line Charge-Recycling. 446-459 - Willem Laflere, Michiel S. J. Steyaert, Jan Craninckx:
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer. 460-467 - Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor:
A Programmable Impedance Matching Circuit for Voiceband Modems. 468-476 - Behzad Razavi:
A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider. 477-485 - Sven Mattisson, Hans Hagberg, Pietro Andreani:
Sensitivity Degradation in a Tri-Band GSM BiCMOS Direct-Conversion Receiver Caused by Transient Substrate Heating. 486-496 - Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki, Masumi Kasahara, Satoshi Tanaka:
ΔΣ PLL Transmitter With a Loop-Bandwidth Calibration System. 497-506 - Yong Hoon Kang, Jin-Kook Kim, Sang Won Hwang, Joon Young Kwak, Jun-Yong Park, Daeyong Kim, Chan Ho Kim, Jong-Yeol Park, Yong-Taek Jeong, Jong Nam Baek, Su Chang Jeon, Pyungmoon Jang, Sang Hoon Lee, You-Sang Lee, Min-Seok Kim, Jin-Yub Lee, Yun Ho Choi:
High-Voltage Analog System for a Mobile NAND Flash. 507-517 - Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. 518-529 - Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh:
High-Speed and Low-Power Design Techniques for TCAM Macros. 530-540 - Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. 541-549 - Jun Zhou, David Kinniment, Charles E. Dike, Gordon Russell, Alexandre Yakovlev:
On-Chip Measurement of Deep Metastability in Synchronizers. 550-557 - Guillermo J. Serrano, Paul E. Hasler:
A Precision Low-TC Wide-Range CMOS Current Reference. 558-565 - Patrick Lichtsteiner, Christoph Posch, Tobi Delbrück:
A 128×128 120 dB 15 µs Latency Asynchronous Temporal Contrast Vision Sensor. 566-576
Volume 43, Number 3, March 2008
- Bram Nauta:
New Associate Editor. 578 - Jarkko Jussila, Pete Sivonen:
A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-µm CMOS. 579-587 - Xiaohua Fan, Heng Zhang, Edgar Sánchez-Sinencio:
A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA. 588-599 - Gang Liu, Peter Haldi, Tsu-Jae King Liu, Ali M. Niknejad:
Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off. 600-609 - Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda:
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. 610-618 - Jri Lee, Mingchung Liu:
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique. 619-630 - Feng Lin, Roman A. Royer, Brian Johnson, Brent Keeth:
A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM. 631-641 - Chih-Fan Liao, Shen-Iuan Liu:
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS. 642-655 - Ahmad Mirzaei, Mohammad E. Heidari, Rahim Bagheri, Asad A. Abidi:
Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers. 656-671 - Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu:
An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process. 672-683 - Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. 684-694 - Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas:
AsAP: An Asynchronous Array of Simple Processors. 695-705 - Jérôme Dubois, Dominique Ginhac, Michel Paindavoine, Barthélémy Heyrman:
A 10 000 fps CMOS Sensor With Massively Parallel Image Processing. 706-717 - Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects. 718-728 - Ickjin Kwon, Yunseong Eo, Heemun Bang, Kyudon Choi, Sangyoon Jeon, Sungjae Jung, Donghyun Lee, Heungbae Lee:
A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader. 729-738
Volume 43, Number 4, April 2008
- Kazuo Yano, Katsu Nakamura:
Introduction to the Special Issue on the 2007 Symposium on VLSI Circuits. 755-756 - Mark Horowitz, Don Stark, Elad Alon:
Digital Circuit Design Trends. 757-761 - Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi:
Memory at VLSI Circuits Symposium. 762-768 - Minjae Lee, Asad A. Abidi:
A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue. 769-777 - Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, Bram Nauta:
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. 778-786 - Junhua Shen, Peter R. Kinget:
A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS. 787-795 - Scott D. Kulchycki, Roxana Trofin, Katelijn Vleugels, Bruce A. Wooley:
A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator. 796-804 - Matthew Z. Straayer, Michael H. Perrott:
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer. 805-814 - Feng Su, Wing-Hung Ki, Chi-Ying Tsui:
Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications. 815-822 - Satoru Adachi, Woonghee Lee, Nana Akahane, Hiromichi Oshikubo, Koichi Mizobuchi, Shigetoshi Sugawa:
A 200-µV/e- CMOS Image Sensor With 100-ke- Full Well Capacity. 823-830 - Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho:
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. 831-843 - Josh Wibben, Ramesh Harjani:
A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors. 844-854 - Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott:
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. 855-863 - Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
Resonant-Clock Latch-Based Design. 864-873 - Tony Tae-Hyoung Kim, Randy Persaud, Chris H. Kim:
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits. 874-880 - Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd M. Austin, Dennis Sylvester, David T. Blaauw:
Exploring Variability and Performance in a Sub-200-mV Processor. 881-891 - Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto:
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. 892-901 - Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. 902-910 - Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara:
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. 911-918 - Ki-Tae Park, Myounggon Kang, Doogon Kim, Soonwook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Kinam Kim:
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. 919-928 - Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue, Toshiyuki Takahashi, Toshifumi Shano, Yukio Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Noriaki Motohashi, Kazuhisa Kanazawa, Kenichi Imamiya, Hiroto Nakai, Menahem Lasser, Mark Murin, Avraham Meir, Arik Eyal, Mark Shlick:
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory. 929-937 - Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu:
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. 938-945 - Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. 946-955 - Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek:
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. 956-963 - Tatsuo Nakagawa, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Yuji Ogata, Akira Maeki, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing. 964-973 - Ali Medi, Won Namgoong:
A High Data-Rate Energy-Efficient Interference-Tolerant Fully Integrated CMOS Frequency Channelized UWB Transceiver for Impulse Radio. 974-980 - Peter H. R. Popplewell, Victor Karam, Atif Shamim, John W. M. Rogers, Langis Roy, Calvin Plett:
A 5.2-GHz BFSK Transceiver Using Injection-Locking and an On-Chip Antenna. 981-990 - Qun Gu, Zhiwei Xu, Daquan Huang, Tim R. LaRocca, Ning-Yi Wang, William Hant, Mau-Chung Frank Chang:
A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases. 991-998 - Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz:
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. 999-1009 - Ganesh Balamurugan, Joseph T. Kennedy, Gaurab Banerjee, James E. Jaussi, Mozhgan Mansuri, Frank O'Mahony, Bryan Casper, Randy Mooney:
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. 1010-1019 - Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu:
A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. 1020-1029 - Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, Ichiro Seto:
A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer. 1030-1037 - Koichi Nose, Masayuki Mizuno:
A 0.016 mm2, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis. 1038-1046
Volume 43, Number 5, May 2008
- Bram Nauta:
New Associate Editor. 1051 - Jacques Christophe Rudell:
Overview for the Special Section on the 2007 Radio Frequency Integrated Circuits Symposium. 1052-1053 - Peter Haldi, Debopriyo Chowdhury, Patrick Reynaert, Gang Liu, Ali M. Niknejad:
A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS. 1054-1063 - Kyu Hwan An, Ockgoo Lee, Hyungwook Kim,