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ORCIDIEEE Journal of Solid-State Circuits, Volume 50
Volume 50, Number 1, January 2015
- Michael P. Flynn:
New Associate Editors. 3 - Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa:
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. 4-9 - Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. 10-23 - Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White:
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. 24-34 - Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li
, Sujal Vora, Raj Varada, Eddie Wang:
A 22 nm 15-Core Enterprise Xeon® Processor Family. 35-48 - Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, Mark Neidengard, Anant Deval, Ashish Khanna, Nasirul Chowdhury, Ravi Rajwar, Timothy M. Wilson, Rajesh Kumar:
Haswell: A Family of IA 22 nm Processors. 49-58 - Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. 59-67 - Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. 68-80 - Martin Saint-Laurent, Paul Bassett, Ken Lin, Baker Mohammad, Yuhe Wang, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Marzio Pedrali-Noy, Willie Anderson:
A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications. 81-91 - Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. 92-101 - Michael Price, James R. Glass, Anantha P. Chandrakasan:
A 6 mW, 5, 000-Word Real-Time Speech Recognizer Using WFST Models. 102-112 - Gyeonghoon Kim, Kyuho Jason Lee, Youchang Kim, Seongwook Park, Injoon Hong, Kyeongryeol Bong, Hoi-Jun Yoo:
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications. 113-124 - Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart:
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. 125-136 - Fang-Li Yuan, Cheng C. Wang, Tsung-Han Yu, Dejan Markovic:
A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing. 137-149 - Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang:
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. 150-157 - Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park, Yongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi, Hyo-Sig Won, Jaehong Park:
A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. 158-169 - Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang:
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. 170-177 - Tae-Young Oh, Hoeju Chung, Jun-Young Park, Ki-Won Lee, Seung-Hoon Oh, Su-Yeon Doo, Hyoung-Joo Kim, ChangYong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, Young-Ryeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi:
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. 178-190 - Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jae-Hwan Kim, Jin-Hee Cho, Jaejin Lee, Jun Hyun Chun:
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits. 191-203 - Ki-Tae Park, Sangwan Nam, Dae-Han Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Minsu Kim, Hyun Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Yoon, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Jeong-Hyuk Choi, Kinam Kim:
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. 204-213 - Marcus Yip, Rui Jin, Hideko Heidi Nakajima, Konstantina M. Stankovic, Anantha P. Chandrakasan:
A Fully-Implantable Cochlear Implant SoC With Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation. 214-229 - Nick Van Helleputte, Mario Konijnenburg, Julia Pettine, Dong-Woo Jee, Hyejung Kim, Alonso Morgado, Roland Van Wegberg, Tom Torfs, Rachit Mohan, Arjan Breeschoten, Harmke de Groot, Chris Van Hoof, Refet Firat Yazicioglu:
A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP. 230-244 - Sunjoo Hong, Kwonjoon Lee, Unsoo Ha, Hyunki Kim, Yongsu Lee, Youchang Kim, Hoi-Jun Yoo:
A 4.9 mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System. 245-257 - Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden:
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters. 258-269 - Junjie Lu, Steven R. Young, Itamar Arel, Jeremy Holleman:
A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS. 270-281 - Jan Genoe, Koji Obata, Marc Ameys, Kris Myny, Tung Huei Ke, Manoj Nag, Soeren Steudel, Sarah Schols, Joris Maas, Ashutosh Tripathi, Jan-Laurens P. J. van der Steen, Tim Ellis, Gerwin H. Gelinck, Paul Heremans:
Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex. 282-290 - Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon:
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. 291-302 - Cyrus S. Bamji, Patrick O'Connor, Tamer A. Elkhatib, Swati Mehta, Barry Thompson, Lawrence A. Prather, Dane Snow, Onur Can Akkaya, Andy Daniel, Andrew D. Payne, Travis Perry, Mike Fenton, Vei-Han Chan:
A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC. 303-319 - Richard J. Przybyla, Hao-Yen Tang, André Guedes, Stefon E. Shelton, David A. Horsley, Bernhard E. Boser:
3D Ultrasonic Rangefinder on a Chip. 320-334 - Masayuki Miyamoto, Mutsumi Hamaguchi, Akira Nagao:
A 143 × 81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential Sensing Architecture. 335-343 - Rikky Muller, Hanh-Phuc Le, Wen Li, Peter Ledochowitsch, Simone Gambini, Toni Björninen, Aaron C. Koralek, Jose M. Carmena, Michel M. Maharbiz, Elad Alon, Jan M. Rabaey:
A Minimally Invasive 64-Channel Wireless μECoG Implant. 344-359 - Hyung-Min Lee, Ki Yong Kwon, Wen Li, Maysam Ghovanloo:
A Power-Efficient Switched-Capacitor Stimulating System for Electrical/Optical Deep Brain Stimulation. 360-374 - Yen-Po Chen, Dongsuk Jeon, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Inhee Lee, Nicholas B. Langhals, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. 375-390
Volume 50, Number 2, February 2015
- Hyosup Won, Taehun Yoon, Jinho Han, Joon-Yeong Lee, Jong-Hyeok Yoon, Taeho Kim, Jeong-Sup Lee, Sangeun Lee, Kwangseok Han, Jinhee Lee, Jinho Park, Hyeon-Min Bae:
A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. 399-413 - Jungmoon Kim, Philip K. T. Mok, Chulwoo Kim:
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement. 414-425 - Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz:
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links. 426-439 - Min Tan, Wing-Hung Ki:
A Cascode Miller-Compensated Three-Stage Amplifier With Local Impedance Attenuation for Optimized Complex-Pole Control. 440-449 - Christian Venerus, Ian Galton:
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO. 450-463 - Youn Sung Park, Yaoyu Tao, Zhengya Zhang:
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. 464-475 - Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. 476-489 - Mohammad Hekmat, Farshid Aryanfar, Jason Wei, Vijay P. Gadde, Reza Navid:
A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators. 490-502 - Kyeongha Kwon, Jong-Hyeok Yoon, Hyeon-Min Bae:
A 6 Gb/s Transceiver With a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers. 503-514 - Jun Won Jung, Behzad Razavi:
A 25 Gb/s 5.8 mW CMOS Equalizer. 515-526 - Sandipan Kundu, Jeyanandh Paramesh:
A Compact, Supply-Voltage Scalable 45-66 GHz Baseband-Combining CMOS Phased-Array Receiver. 527-542 - Hyeok-Ki Hong, Wan Kim, Hyun-Wook Kang, Sun-Jae Park, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. 543-555 - Jianxun Zhu, Harish Krishnaswamy, Peter R. Kinget:
Field-Programmable LNAs With Interferer-Reflecting Loop for Input Linearity Enhancement. 556-572 - Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee:
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. 573-585 - Hang Liu, Xi Zhu, Chirn Chye Boon, Xiaofeng He:
Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology. 586-596 - Yahya M. Tousi, Ehsan Afshari:
A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems. 597-609 - Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim:
Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing. 610-618 - Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". 619
Volume 50, Number 3, March 2015
- Aliakbar Homayoun, Behzad Razavi:
A Low-Power CMOS Receiver for 5 GHz WLAN. 630-643 - Mikko Englund, Kim B. Ostman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS. 644-655 - Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, Jri Lee:
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology. 656-668 - Shuli Geng, Dang Liu, Yanfeng Li, Huiying Zhuo, Woogeun Rhee, Zhihua Wang:
A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications. 669-678 - Masoud Babaie, Robert Bogdan Staszewski:
An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability. 679-692 - Seyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency. 693-703 - Erik Olieman, Anne-Johan Annema, Bram Nauta:
An Interleaved Full Nyquist High-Speed DAC Technique. 704-713 - Xinpeng Xing, Georges G. E. Gielen:
A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS. 714-723 - Zhe Hua, Hoi Lee:
A Reconfigurable Dual-Output Switched-Capacitor DC-DC Regulator With Sub-Harmonic Adaptive-On-Time Control for Low-Power Applications. 724-736 - Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. 737-748 - Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schluessler, Holger Eisenreich, René Schüffny:
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. 749-762 - Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang:
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. 763-775 - Woojae Lee, SeongHwan Cho:
Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance. 776-785 - Fernando Pardo, Jose Antonio Boluda, Francisco Vegara:
Selective Change Driven Vision Sensor With Continuous-Time Logarithmic Photoreceptor and Winner-Take-All Circuit for Pixel Selection. 786-798 - Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, Dror Zilberman:
Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process. 799-807 - Bum-Kyum Kim, Donggu Im, Jaeyoung Choi, Kwyro Lee:
Corrections to "A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization". 808
Volume 50, Number 4, April 2015
- Michael P. Flynn:
New Associate Editor. 811 - Jeffrey C. Gealow, Masato Motomura:
Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. 812-813 - Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. 814-827 - Chen Sun, Michael Georgas, Jason Orcutt, Benjamin Moss, Yu-Hsin Chen, Jeffrey Shainline, Mark T. Wade, Karan Mehta, Kareem Nammari, Erman Timurdogan, Daniel L. Miller, Ofer Tehar-Zahav, Zvi Sternberg, Jonathan C. Leu, Johanna Chong, Reha Bafrali, Gurtej Sandhu, Michael Watts, Roy Meade, Milos A. Popovic, Rajeev J. Ram, Vladimir Stojanovic:
A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS. 828-844 - Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. 845-855 - Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS. 856-866 - Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. 867-881 - Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. 882-895 - Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. 896-907 - Stacy Ho, Chi-Lun Lo, Jiayun Ru, Jialin Zhao:
A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS. 908-919 - Yuan Zhou, Benwei Xu, Yun Chiu:
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. 920-931 - Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. 932-945 - Sy-Chyuan Hwu, Behzad Razavi:
An RF Receiver for Intra-Band Carrier Aggregation. 946-961 - Maryam Tabesh, Nemat Dolatsha, Amin Arbabian, Ali M. Niknejad:
A Power-Harvesting Pad-Less Millimeter-Sized Radio. 962-977 - Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices. 978-989 - Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
High Frequency Buck Converter Design Using Time-Based Control Techniques. 990-1001 - Liechao Huang, Warren Rieutort-Louis, Alexandra Gualdino, Laura Teagno, Yingzhe Hu, Joao Mouro, Josue Sanz-Robinson, James C. Sturm, Sigurd Wagner, Virginia Chu, João Pedro Conde, Naveen Verma:
A System Based on Capacitive Interfacing of CMOS With Post-Processed Thin-Film MEMS Resonators Employing Synchronous Readout for Parasitic Nulling. 1002-1015 - Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita:
A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. 1016-1024 - Kiseok Song, Unsoo Ha, Seongwook Park, Joonsung Bae, Hoi-Jun Yoo:
An Impedance and Multi-Wavelength Near-Infrared Spectroscopy IC for Non-Invasive Blood Glucose Estimation. 1025-1037 - William Biederman, Daniel J. Yeager, Nathan Narevsky, Jaclyn Leverett, Ryan Neely, Jose M. Carmena, Elad Alon, Jan M. Rabaey:
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation. 1038-1047 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. 1048-1058 - Kyuho Jason Lee, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo:
A Vocabulary Forest Object Matching Processor With 2.07 M-Vector/s Throughput and 13.3 nJ/Vector Per-Vector Energy for Full-HD 60 fps Video Object Recognition. 1059-1069 - Phil Knag, Jung Kuk Kim, Thomas Chen, Zhengya Zhang:
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding. 1070-1079
Volume 50, Number 5, May 2015
- Ranjit Gharpurey:
Introduction to the Special Section on the 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. 1083-1084 - Venumadhav Bhagavatula, Mazhareddin Taghivand, Jacques Christophe Rudell:
A Compact 77% Fractional Bandwidth CMOS Band-Pass Distributed Amplifier With Mirror-Symmetric Norton Transforms. 1085-1093 - Song Hu, Shouhei Kousai, Jong Seok Park, Outmane Lemtiri Chlieh, Hua Wang:
Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS. 1094-1106 - Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun:
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners. 1107-1116 - Rahmi Hezar, Lei Ding, Aritra Banerjee, Joonhoi Hur, Baher Haroun:
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications. 1117-1125 - Mustafijur Rahman, Mohammad Elbadry, Ramesh Harjani:
An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and Injection Locking. 1126-1136 - Anders Nejdel, Henrik Sjöland, Markus Törmänen:
A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching. 1137-1147 - Hajir Hedayati, Wing-Fat Andy Lau, Namsoo Kim, Vladimir Aparin, Kamran Entesari:
A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS. 1148-1164 - Nitz Saputra, John R. Long:
A Fully Integrated Wideband FM Transceiver for Low Data Rate Autonomous Systems. 1165-1175 - Tong Zhang, Apsara Ravish Suvarna, Venumadhav Bhagavatula, Jacques Christophe Rudell:
An Integrated CMOS Passive Self-Interference Mitigation Technique for FDD Radios. 1176-1188 - Dong Yang, Hazal Yüksel, Alyosha C. Molnar:
A Wideband Highly Integrated and Widely Tunable Transceiver for In-Band Full-Duplex Communication. 1189-1202 - Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx:
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. 1203-1213 - Bodhisatwa Sadhu, Mark A. Ferriss, Alberto Valdes-Garcia:
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance. 1214-1223 - Steven M. Bowers, Amirreza Safaripour, Ali Hajimiri:
Dynamic Polarization Control. 1224-1236 - Brecht François, Patrick Reynaert:
A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS. 1237-1250 - Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. 1251-1262