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ORCIDIEEE Journal of Solid-State Circuits, Volume 53
Volume 53, Number 1, January 2018
- Keith A. Bowman
, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak:
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. 3-7 - Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, Rinkle Jain, Sheldon Weng, Stephen T. Kim, George E. Matthew, Nachiket V. Desai, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. 8-19 - Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins:
An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator. 20-34 - Loai G. Salem, Julian Warchall, Patrick P. Mercier:
A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control. 35-49 - Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David T. Blaauw:
A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector. 50-65 - Michael Price, James R. Glass, Anantha P. Chandrakasan:
A Low-Power Speech Recognizer and Voice Activity Detector Using Deep Neural Networks. 66-75 - Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Luyao Gong, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim:
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. 76-90 - Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench:
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. 91-101 - Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak:
Zen: An Energy-Efficient High-Performance × 86 Core. 102-114 - Kyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Donghyeon Han, Hoi-Jun Yoo:
A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector. 115-123 - Chulbum Kim, Doo-Hyun Kim, Woopyo Jeong, Hyun-Jin Kim, Il-Han Park, Hyun Wook Park, Jong-Hoon Lee, Jiyoon Park, Yang-Lo Ahn, Ji Young Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sanggi Hong, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yub Lee, Ki-Tae Park, Kyehyun Kyung:
A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. 124-133 - Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stephan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale:
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications. 134-143 - Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. 144-154 - Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler:
1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%. 155-163 - Sining Pan, Yanquan Luo, Saleh Heidary Shalmany, Kofi A. A. Makinwa:
A Resistor-Based Temperature Sensor With a 0.13 pJ $\cdot$ K2 Resolution FoM. 164-173 - Maximilian Marx, Daniel DeDorigo, Sebastian Nessler, Stefan Rombach, Yiannos Manoli:
A 27 $\mu \text{W}$ 0.06 mm2 Background Resonance Frequency Tuning Circuit Based on Noise Observation for a 1.71 mW CT- $\Delta \Sigma $ MEMS Gyroscope Readout System With 0.9 °/h Bias Instability. 174-186 - Jae-Sung An, Sang-Hyun Han, Ju Eon Kim, Dong-Hyun Yoon, Young-Hwan Kim, Han-Hee Hong, Jae-Hun Ye, Sung-Jin Jung, Seung-Hwan Lee, Ji-Yong Jeong, Kwang-Hyun Baek, Seong-Kwan Hong, Oh-Kyong Kwon:
A 3.9-kHz Frame Rate and 61.0-dB SNR Analog Front-End IC With 6-bit Pressure and Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for Capacitive Touch Screen Panels. 187-203 - Hyunseok Hwang, Hyeyeon Lee, Myungjin Han, Hongchae Kim, Youngcheol Chae:
A 1.8-V 6.9-mW 120-fps 50-Channel Capacitive Touch Readout With Current Conveyor AFE and Current-Driven $\Delta \Sigma $ ADC. 204-218 - Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Takashi Muto, Takeshi Akiyama, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa:
A 1.8e-rms Temporal Noise Over 110-dB-Dynamic Range 3.4µm Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter. 219-228 - Shin'ichi Machida, Sanshiro Shishido, Takeyoshi Tokuhara, Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue:
A 2.1-Mpixel Organic Film-Stacked RGB-IR Image Sensor With Electrically Controllable IR Sensitivity. 229-235 - Nachiket V. Desai, Chiraag Juvekar, Shubham Chandak, Anantha P. Chandrakasan:
An Actively Detuned Wireless Power Receiver With Public Key Cryptographic Authentication and Dynamic Power Allocation. 236-246 - Xugang Ke, Joseph Sankman, Yingping Chen, Lenian He, Dongsheng Brian Ma:
A Tri-Slope Gate Driving GaN DC-DC Converter With Spurious Noise Compression and Ringing Suppression for Automotive Applications. 247-260 - Seokhyeon Jeong, Yu Chen, Tae-Kwang Jang, Julius Ming-Lin Tsai, David T. Blaauw, Hun-Seok Kim, Dennis Sylvester:
Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for Unattended Ground Sensor Nodes. 261-274 - SungWon Chung, Hooman Abediasl, Hossein Hashemi:
A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS. 275-296 - Yasmin Afsar, Tiffany Moy, Nicholas Brady, Sigurd Wagner, James C. Sturm, Naveen Verma:
An Architecture for Large-Area Sensor Acquisition Using Frequency-Hopping ZnO TFT DCOs. 297-308 - Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Harald A. R. Homulle, Lin Song, Mina Shahmohammadi, Robert Bogdan Staszewski, Andrei Vladimirescu, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon:
Cryo-CMOS Circuits and Systems for Quantum Computing Applications. 309-321
Volume 53, Number 2, February 2018
- Yang Xu, Jianxun Zhu, Peter R. Kinget:
A Blocker-Tolerant RF Front End With Harmonic-Rejecting N-Path Filter. 327-339 - Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull, Hua Wang:
A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM-PM Distortion Self-Compensation. 340-356 - Ahmed I. Hussein, Sriharsha Vasadi, Jeyanandh Paramesh:
A 450 fs 65-nm CMOS Millimeter-Wave Time-to-Digital Converter Using Statistical Element Selection for All-Digital PLLs. 357-374 - Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi:
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers. 375-388 - Amir Nikpaik, Amir Hossein Masnadi Shirazi, Abdolreza Nabavi, Shahriar Mirabbasi, Sudip Shekhar:
A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS. 389-403 - Seungnam Choi, Hwan-Seok Ku, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications. 404-417 - Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis P. Tsividis:
A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption. 418-430 - Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, Jaeha Kim:
CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks. 431-444 - Mostafa Gamal Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, Guanghua Shu, Ahmed Elmallah, Alexander V. Rylyakov, Pavan Kumar Hanumolu:
A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. 445-457 - Iria Garcia Lopez, Ahmed Awny, Pedro Rito, Minsu Ko, Ahmet Cagri Ulusoy, Dietmar Kissinger:
100 Gb/s Differential Linear TIAs With Less Than 10 pA/√Hz in 130-nm SiGe: C BiCMOS. 458-469 - Marijn Verbeke, Pieter Rombouts, Hannes Ramon, Bart Moeneclaey, Xin Yin, Johan Bauwelinck, Guy Torfs:
A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit. 470-483 - Hyun-Sik Kim, Dong-Kyu Kim:
An Active-Matrix OLED Driver CMOS IC With Compensation of Non-Uniform Routing-Line Resistances in Ultra-Thin Panel Bezel. 484-500 - Sung-Yun Park, Jihyun Cho, Kyounghwan Na, Euisik Yoon:
Modular 128-Channel Δ-ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems. 501-514 - Ha Le-Thai, Genis Chapinal, Tomas Geurts, Georges G. E. Gielen:
A 0.18-µm CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1e-rms Noise at 3.8-µs Conversion Time. 515-526 - Shang-Fu Yeh, Kuo-Yu Chou, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh:
A 0.66erms- Temporal-Readout-Noise 3-D-Stacked CMOS Image Sensor With Conditional Correlated Multiple Sampling Technique. 527-537 - Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants. 538-551 - Yi-Wei Huang, Tai-Haur Kuo, Szu-Yu Huang, Kuan-Yu Fang:
A Four-Phase Buck Converter With Capacitor-Current-Sensor Calibration for Load-Transient-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits. 552-568 - Saad Bin Nasir, Shreyas Sen, Arijit Raychowdhury:
Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits. 569-581 - Xun Liu, Cheng Huang, Philip K. T. Mok:
A High-Frequency Three-Level Buck Converter With Real-Time Calibration and Wide Output Range for Fast-DVS. 582-595 - Chi-Hsiang Huang, Hung-Hsien Wu, Chia-Ling Wei:
Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter. 596-604 - Jihyuck Jo, Soyoung Cha, Dayoung Rho, In-Cheol Park:
DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. 605-618 - Yiqun Zhang, Mahmood Khayatzadeh, Kaiyuan Yang, Mehdi Saligane, Nathaniel Ross Pinckney, Massimo Alioto, David T. Blaauw, Dennis Sylvester:
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor. 619-631 - Saurabh Jain, Longyang Lin, Massimo Alioto:
Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling. 632-641 - Mingu Kang, Sujan K. Gonugondla, Ameya Patil, Naresh R. Shanbhag:
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array. 642-655 - Morteza Nabavi, Manoj Sachdev:
A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. 656-667
Volume 53, Number 3, March 2018
- Rikky Muller, Samuel Palermo:
Guest Editorial 2017 IEEE Custom Integrated Circuits Conference. 679-680 - Qiwei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone:
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers. 681-691 - Hani Esmaeelzadeh, Sudhakar Pamarti:
A Quick Startup Technique for High-Q Oscillators Using Precisely Timed Energy Injection. 692-702 - Shravan S. Nagam, Peter R. Kinget:
A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector. 703-714 - Dongyi Liao, Fa Foster Dai, Bram Nauta, Eric A. M. Klumperink:
A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching. 715-727 - Jiangyi Li, Teng Yang, Minhao Yang, Peter R. Kinget, Mingoo Seok:
An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function. 728-737 - Hechen Wang, Fa Foster Dai, Hua Wang:
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order ΔΣ Linearization. 738-749 - Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi:
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR. 750-761 - Jeffrey Lee, Ray Gomez, Sudhakar Pamarti:
A Broadband Class-AB Power Amplifier With Instantaneous Supply-Switching Efficiency Enhancement for Cable TV Application. 762-771 - Aurangozeb, A. K. M. Delwar Hossain, Maruf Mohammad, Masum Hossain:
Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver. 772-788 - Yeonam Yoon, Nan Sun:
A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration. 789-798 - Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. 799-813 - Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. 814-824 - Dongseok Shin, Kwang-Jin Koh:
An Injection Frequency-Locked Loop - Autonomous Injection Frequency Tracking Loop With Phase Noise Self-Calibration for Power-Efficient mm-Wave Signal Sources. 825-838 - Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu:
A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS. 839-849 - Chi-Hang Chan, Yan Zhu, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins:
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. 850-860 - Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl:
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. 861-872 - Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu:
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. 873-883 - Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu:
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. 884-895 - Linxiao Shen, Nanshu Lu, Nan Sun:
A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor. 896-905 - Hyunmin Park, Jintae Kim:
A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V. 906-912 - Lisong Li, Yuan Gao, Huaxing Jiang, Philip K. T. Mok, Kei May Lau:
An Auto-Zero-Voltage-Switching Quasi-Resonant LED Driver With GaN FETs and Fully Integrated LED Shunt Protectors. 913-923 - Fahim U. Rahman, Visvesh Sathe:
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. 924-935 - Yu Pu, Chunlei Shi, Giby Samson, Dongkyu Park, Ken Easton, Rudy Beraha, Adam Newham, Mark Lin, Venkat Rangan, Karam Chatha, Danny Butterfield, Rashid Attar:
A 9-mm2 Ultra-Low-Power Highly Integrated 28-nm CMOS SoC for Internet of Things. 936-948 - Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. 949-960
Volume 53, Number 4, April 2018
- Jan Craninckx:
New Associate Editors. 963-964 - Makoto Ikeda, Ken Chang:
Introduction to the Special Issue on the 2017 Symposium on VLSI Circuits. 965-967 - Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei:
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. 968-982 - Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. 983-994 - Yiqun Zhang, Li Xu, Qing Dong, Jingcheng Wang, David T. Blaauw, Dennis Sylvester:
Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security. 995-1005 - Qing Dong, Supreet Jeloka, Mehdi Saligane, Yejoong Kim, Masaru Kawaminami, Akihiko Harada, Satoru Miyoshi, Makoto Yasuda, David T. Blaauw, Dennis Sylvester:
A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin. 1006-1015 - Hongyang Jia, Naveen Verma:
Exploiting Approximate Feature Extraction via Genetic Programming for Hardware Acceleration in a Heterogeneous Microprocessor. 1016-1027 - Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita:
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. 1028-1037 - Harish Kumar Krishnamurthy, Sheldon Weng, George E. Matthew, Nachiket V. Desai, Ruchir Saraswat, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS. 1038-1048 - Kye-Seok Yoon, Sung-Wan Hong, Gyu-Hyeong Cho:
Double Pile-Up Resonance Energy Harvesting Circuit for Piezoelectric and Thermoelectric Materials. 1049-1060 - Tomohiro Takahashi, Yuichi Kaji, Yasunori Tsukuda, Shinichiro Futami, Katsuhiko Hanzawa, Takahito Yamauchi, Ping Wah Wong, Frederick T. Brady, Phil Holden, Thomas Ayers, Kyohei Mizuta, Susumu Ohki, Keiji Tatani, Hayato Wakabayashi, Yoshikazu Nitta:
A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture. 1061-1070 - Yuichi Kato, Takuya Sano, Yusuke Moriyama, Shunji Maeda, Takeshi Yamazaki, Atsushi Nose, Kimiyasu Shiina, Yohtaro Yasu, Ward van der Tempel, Alper Ercan, Yoshiki Ebiko, Daniel Van Nieuwenhove, Shunichi Sukegawa:
320 × 240 Back-Illuminated 10-µm CAPD Pixels for High-Speed Modulation Time-of-Flight CMOS Image Sensor. 1071-1078 - Yeunhee Huh, Sung-Wan Hong, Sang-Hui Park, Changsik Shin, Jun-Suk Bang, Changbyung Park, Sungsoo Park, Gyu-Hyeong Cho:
A 10.1" 183-µW/electrode, 0.73-mm2/sensor High-SNR 3-D Hover Sensor Based on Enhanced Signal Refining and Fine Error Calibrating Techniques. 1079-1088 - Marcus J. Weber, Yoshiaki Yoshihara, Ahmed Sawaby, Jayant Charthad, Ting Chia Chang, Amin Arbabian:
A Miniaturized Single-Transducer Implantable Pressure Sensor With Time-Multiplexed Ultrasonic Data and Power Links. 1089-1101 - Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals. 1102-1114 - Md Shakil Akter, Kofi A. A. Makinwa, Klaas Bult:
A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier. 1115-1126 - Bonjern Yang, Eric Chang, Ali M. Niknejad, Borivoje Nikolic, Elad Alon:
A 65-nm CMOS I/Q RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering. 1127-1138 - Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, Hyung-Jong Ko, Seung-Tak Ryu:
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. 1139-1148 - Junhua Shen, Akira Shikata, Lalinda Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, Michael C. W. Coln:
A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS. 1149-1160 - Ewout Martens, Benjamin P. Hershberg, Jan Craninckx:
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. 1161-1171 - Shuang Zhu, Bo Wu, Yongda Cai, Yun Chiu:
A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS. 1172-1183 - Guoqiang Zhang, Kosuke Yayama, Akio Katsushima, Takahiro Miki:
A 3.2 ppm/°C Second-Order Temperature Compensated CMOS On-Chip Oscillator Using Voltage Ratio Adjusting Technique. 1184-1191 - Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi:
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. 1192-1202 - Po-Wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim:
A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer. 1203-1213 - Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli:
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. 1214-1226 - Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl:
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. 1227-1237
Volume 53, Number 5, May 2018
- Jan Craninckx:
New Associate Editor. 1243