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ORCIDIEEE Journal of Solid-State Circuits, Volume 60
Volume 60, Number 1, January 2025
- Dennis Sylvester
:
New Associate Editor. 3 - Dennis Sylvester:
New Associate Editor. 4 - Wei-Zen Chen, Benton H. Calhoun, Chia-Hsiang Yang, Shreyas Sen, Jun Yang:
Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC). 5-8 - Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw C. H. Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin:
A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS. 9-22 - Marco Cusmai, Noam Familia, Elad Kuperberg, Mohammad Nashash, Dovid Gottesman, Zvi Marcus, Yeshayahu Horwitz, Sagi Zalcman, Jihwan Kim, Sandipan Kundu, Ilia Radashkevich, Yoav Segal, Dror Lazar, Udi Virobnik, Peng Li, Ariel Cohen:
A 0.92-pJ/b PAM-4 and 0.61-pJ/b PAM-6 224-Gb/s DAC-Based Transmitter in 3-nm FinFET. 23-34 - Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. 35-48 - Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. 49-64 - Kaize Zhou, Weiwei Shan, Keran Li, Zhuo Chen, Haitao Ge, Jun Yang:
A Proactive Droop Mitigation Technique Using Dual-Proportional-Derivative Controller Based on Current and Voltage Prediction. 65-74 - Suhwan Kim, Harish K. Krishnamurthy, Zakir K. Ahmed, Nachiket V. Desai, Sheldon Weng, Anne Augustine, Huong T. Do, Jingshu Yu, Phong D. Bach, Xiaosen Liu, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Monolithic, 10.5 W/mm2, 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class. 75-84 - Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang:
An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation. 85-98 - Junha Ryu, Hankyul Kwon, Wonhoon Park, Zhiyong Li, Beomseok Kwon, Donghyeon Han, Dongseok Im, Sangyeob Kim, Hyungnam Joo, Minsung Kim, Hoi-Jun Yoo:
NeuGPU: An Energy-Efficient Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile Devices. 99-111 - Jueun Jung, Seungbin Kim, Bokyoung Seo, Wuyoung Jang, Sangho Lee, Jeongmin Shin, Donghyeon Han, Kyuho Jason Lee:
An Energy-Efficient Processor for Real-Time Semantic LiDAR SLAM in Mobile Robots. 112-124 - Shiyu Guo, Yuhao Ju, Xi Chen, Sachin S. Sapatnekar, Jie Gu:
Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering. 125-135 - Hyeokjun Kwon, Hyunhoon Lee, Gyuhyun Jung, Youngjoo Lee:
Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing. 136-145 - Yan He, Yumin Su, Kaiyuan Yang:
Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation. 146-157 - Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. 158-170 - Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. 171-183 - Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Changsik Yoo, Tae-Young Oh, SangJoon Hwang:
A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. 184-196 - Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang:
A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. 197-204 - Weitao Wu, Hongzhi Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Dongfan Xu, Catherine Wang, Zhenghao Li, Quan Pan:
A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS. 205-216 - Dongwon Lee, Kyung-Sik Choi, Yuqi Liu, Jeongsoo Park, Laurenz Kulmer, Tzu-Yuan Huang, Juerg Leuthold, Hua Wang:
Ultrawideband Distributed Amplifier With Positive Feedback and Intrastack Coupling. 217-229 - Amirreza Alizadeh, Utku Soylu, Logan Whitaker, Biljana Stamenic, Demis D. John, Munkyo Seo, Ahmed S. H. Ahmed, Mark J. W. Rodwell:
Planar 200-GHz Transceiver Modules. 230-243 - Shengpu Niu, Joris Lambrecht, Cheng Wang, Michiel Verplaetse, Ye Gu, Gertjan Coudyzer, Xin Yin:
A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme. 244-259 - Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu:
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage. 260-271 - Jun-Hwan Jang, Hui-Dong Gwon, Sungmin Yoo, Jun-Hyeok Yang, Byong-Deok Choi:
A 0.5-1-V Time-Voltage Hybrid Domain Dual- Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm. 272-285 - Aditi Chakraborty, Ashis Maity:
A Fast SIMO Converter for Command-Directed IoT Nodes With State-Driven Priority Sequencing and Delay-Adjusted Fixed Window Hysteretic Control Using Constant Current-Peak Sequential DCM-CCM Operation. 286-297 - Junyi Qian, Haitao Ge, Yicheng Lu, Weiwei Shan:
A 4.69-TOPS/W Training, 2.34-μJ/Image Inference On-Chip Training Accelerator With Inference-Compatible Backpropagation and Design Space Exploration in 28-nm CMOS. 298-307 - Zhiyu Chen, Ziyuan Wen, Weier Wan, Akhil Reddy Pakala, Yiwei Zou, Wei-Chen Wei, Zengyi Li, Yubei Chen, Kaiyuan Yang:
PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout. 308-320 - Haochen Zhang, Wei-Han Yu, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak:
A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. 321-331 - Ruiqi Guo, Zhiheng Yue, Yang Wang, Hao Li, Te Hu, Yabing Wang, Hao Sun, Jeng-Long Hsu, Yaojun Zhang, Bonan Yan, Leibo Liu, Ru Huang, Shaojun Wei, Shouyi Yin:
A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. 332-346 - Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xinghua Wang, Xiaoran Li, Feng Zhang:
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity. 347-361
Volume 60, Number 2, February 2025
- Emiel Zijlma, Stef van Zanten, Roel Plompen, Eric A. M. Klumperink, Ronan A. R. van der Zee, Bram Nauta:
Analysis and Design of a Low-Loss 1-10 GHz Capacitive Stacking N-Path Filter/Mixer. 367-381 - Yiming Yu, Runyu Liu, Yanpeng Wu, Mengqian Geng, Ruiqi Wang, Zengchuang Chen, Ruilin Liao, Xin Xie, Xiaobo Duan, Zhiyong Gui, Gang Liu, Chenxi Zhao, Huihua Liu, Yunqiu Wu, Kai Kang:
A 26/28/39-GHz Reconfigurable Phased-Array Receiver Front-End With Built-In Calibration Technique for 5G New Radio. 382-393 - Soumya Krishnapuram Sireesh, Niels Christoffers, Sanaz Hadipour Abkenar, Christoph Wagner, Andreas Stelzer:
A 4-bit RFDAC-Based FMCW Modulator for Automotive Radar. 394-409 - Xin An, Helmuth Morath, Florian Protze, Jens Wagner, Frank Ellinger:
A V-Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700 nW. 410-420 - Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun:
A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration. 421-431 - Junghyun Yoon, Moon Hyung Jang, Changuk Lee, Yong Lim, Youngcheol Chae:
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth. 432-442 - Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan:
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer. 443-455 - Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk. 456-468 - Jihang Gao, Siyuan Ye, Jie Li, Xinhang Xu, Zhuoyi Chen, Jiajia Cui, Yaohui Luan, Ru Huang, Le Ye, Linxiao Shen:
An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS. 469-482 - Xiaodong Xu, Beomsoo Park, Marino De Jesus Guzman, Yingjie Chen, Changsok Han, Nima Maghari:
Mixed-Order Correlated Dual-Loop Sturdy MASH CT-ΔΣ Modulator With Distributed Signal Feed-In and VCO Quantizer. 483-496 - Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi:
A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator. 497-508 - Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi:
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces. 509-518 - Jae-Koo Park, Dae-Won Rho, Seung-Jae Yang, Woo-Young Choi:
An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS. 519-528 - Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Zhihua Wang, Baoyong Chi:
A Transformer-Based Series-Resonance CMOS VCO. 529-542 - Eunji Song, Jeonghyu Yang, Youngmin Oh, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han:
100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology. 543-554 - Zhiguo Tong, Junwei Huang, Xiangyu Mao, Rui Paulo Martins, Yan Lu:
A Double Pulse Overlapping Laser Diode Driver With Minimum 100-ps Pulse for LiDAR System. 555-567 - Yi Luo, Shahriar Mirabbasi:
A 60-Frames/s CMOS Image Sensor With Pixelwise Conversion Gain Modulation and Self-Triggered ADCs for Per-Frame Adaptive DCG-HDR Imaging. 568-578 - Martin Lefebvre, David Bol:
A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11- μ m Bulk and 22-nm FD-SOI. 579-592 - Nandor G. Toth, Zhong Tang, Teruki Someya, Sining Pan, Kofi A. A. Makinwa:
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ∘C (3σ) Inaccuracy From -55 ∘C to 125 ∘C. 593-602 - Jiayang Li, Dai Jiang, Yu Wu, Jiaxing Zhang, Nima Seifnaraghi, Richard H. Bayford, Andreas Demosthenous:
A 1.76 mW, 355-fps, Electrical Impedance Tomography System With a Simple Time-to-Digital Impedance Readout for Fast Neonatal Lung Imaging. 603-614 - Wen-Chieh Chen, Shih-Hung Chen, Man-Ching Huang, Shu-Wei Chang, Geert Hellings, Guido Groeseneken:
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology. 615-625 - Yuanfei Wang, Mo Huang, Qiujin Chen, Rui Paulo Martins, Yan Lu:
A VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio Switched- Capacitor Converter. 626-637 - Yanjin Lyu, Yuanqi Hu:
A 2.30 NEF Split-Steering Amplifier for Switched-Capacitor Circuits With -14.2-dB CM-CM Gain and 100-V/μs Slew Rate. 638-650 - Yi Zhong, Yisong Kuang, Kefei Liu, Zilin Wang, Shuo Feng, Guang Chen, Youming Yang, Xiuping Cui, Qiankun Wang, Jian Cao, Song Jia, Yun Liang, Guangyu Sun, Xiaoxin Cui, Ru Huang, Yuan Wang:
PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. 651-671 - Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw:
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. 672-684 - Dewei Wang, Sung Justin Kim, Minhao Yang, Aurel A. Lazar, Mingoo Seok:
Background Noise and Process-Variation-Tolerant Sub-Microwatt Keyword Spotting Hardware Featuring Spike-Domain Division-Based Energy Normalization. 685-694 - Haikang Diao, Yifan He, Xuan Li, Chen Tang, Wenbin Jia, Jinshan Yue, Haoyang Luo, Jiahao Song, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu, Yuan Wang, Xiyuan Tang:
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. 695-706 - Hao Zhang, Weifeng He, Wim Dehaene:
A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications. 707-718 - Zhiheng Yue, Yang Wang, Huizheng Wang, Ruiqi Guo, Fengbin Tu, Jianxun Yang, Shaojun Wei, Yang Hu, Shouyi Yin:
CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. 719-733 - Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Fengbin Tu, Shouyi Yin:
TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. 734-747
Volume 60, Number 3, March 2025
- Dennis Sylvester:
New Associate Editor. 751 - Taiyun Chi, Yoonmyung Lee, Shaolan Li:
Guest Editorial 2024 Custom Integrated Circuits Conference. 752-754 - Heyu Ren, Liangjian Lyu, Binbin Chen, Wenjun Gong, Xing Wu, Chuanjin Richard Shi:
A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity. 755-767 - Li Wang, Zilu Liu, Ruitao Ma, C. Patrick Yue:
A Compact 20-24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme. 768-784 - Hongzhuo Liu, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi:
An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths. 785-798 - Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu:
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. 799-812 - Qifeng Huang, Siji Huang, Yanhang Chen, Yifei Fan, Qiwei Zhao, Jie Yuan:
A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden. 813-825 - Chang Yao, Zhen Lu, Liheng Liu, Yaohua Pan, Wenhui Qin, Shaoyu Ma, Yun Sheng, Zhiliang Hong, Jiawei Xu:
A 140 dB-DR Light-to-Digital Converter Using Current-Domain Hybrid Zoom for Baseline Cancellation and Interference Compensation. 826-837 - Ke Li, Haoyu Gong, Xianyu Congzhou, Zhensheng Li, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin:
A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. 838-849 - Xinling Yue, Sijun Du:
A Single-Stage Bias-Flip Regulating Rectifier With Fully Digital Duty-Cycle-Based MPPT for Piezoelectric Energy Harvesting. 850-860 - Yang Liu, Yuan Yao, Lin Cheng, Wing-Hung Ki:
Pseudo Hysteretic Controlled Gap Time Modulated Isolated DC-DC Converter With Common-Mode Transient Immunity. 861-870 - Guangshu Zhao, Chao Xie, Chenxi Wang, Milin Zhang, Man-Kay Law:
High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From -25 °C to 85 °C. 871-882 - Yingping Chen, Qing Yuan, Ming Liu:
A Closed-Loop EMI Regulated GaN Power Converter With In Situ EMI Sensing and Global Excess-Spectrum Modulation. 883-893 - Aditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Asish Koruprolu, Corentin Pochet, Andrew M. Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall:
A 2.5-20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery. 894-907 - Haoming Xin, Meiyi Zhou, Roland Van Wegberg, Peter Vis, Konstantinos Petkos, Shrishail Patki, Nicolò Rossetti, Mark Fichman, Vojkan Mihajlovic, Carolina Mora Lopez, Geert Langereis, Mario Konijnenburg, Nick Van Helleputte:
A 16-Output 10-V Compliant Stimulator ASIC With Sub-10-nA Mismatch and Simultaneous ETI Sensing for Selective Neural Stimulation. 908-920 - Alireza Dabbaghian, Hossein Kassiri:
Modular DR- and CMR-Boosted Artifact-Resilient EEG Headset With Distributed Pulse-Based Feature Extraction and Neuro-Inspired Boosted-SVM Classifier. 921-933 - Martin Lefebvre, David Bol:
MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection. 934-948 - Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si:
A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. 949-962 - Jaehyun Lee, Dong-gu Choi, Gain Kim, Minyoung Song, Jong-Hyeok Yoon:
BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. 963-976 - Chaoming Fang, Ziyang Shen, Zongsheng Wang, Chuanqing Wang, Shiqi Zhao, Fengshi Tian, Jie Yang, Mohamad Sawan:
An Energy-Efficient Unstructured Sparsity-Aware Deep SNN Accelerator With 3-D Computation Array. 977-989 - Sukbin Lim, Jaehoon Heo, Jinho Yang, Joo-Young Kim:
Hawkeye: A Point Cloud Neural Network Processor With Virtual Pillar and Quadtree-Based Workload Management for Real-Time Outdoor BEV Detection. 990-1001 - Xiaoyu Feng, Xinyuan Lin, Huazhong Yang, Yongpan Liu, Wenyu Sun:
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit. 1002-1013 - Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Lixue Kuang, Lilan Yu, Yue Liu, Xin Liang, Zhihua Wang, Baoyong Chi:
A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC. 1014-1029 - Changxuan Han, Jie Zhou, Xun Luo:
A 70-86-GHz Deep-Noise-Canceling LNA With Dual-Stage Noise Cancellation Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner. 1030-1042 - Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada:
A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. 1043-1055 - Haoyu Zhuang, Yirui Cao, Linzhi Tao, Qiang Li:
A 0.69-Noise-Efficiency-Factor 55× -Preamp-Gain Dynamic Comparator With a Stacking FIA. 1056-1069 - Tingxu Hu, Yan Lu, Rui Paulo Martins, Mo Huang:
An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers. 1070-1081 - Jeongwon Choe, Youngjoo Lee:
Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min-Max Algorithm. 1082-1091 - Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag:
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation. 1092-1102 - Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak:
A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM. 1103-1112 - Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications. 1113-1121
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