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ORCIDMicroprocessors and Microsystems, Volume 64
Volume 64, February 2019
- Bing Jiang, Meng Chen, Feifan Chen:
A network interface device for networked control system with time-driven mode. 1-11 - Sahar Malmir, Majid Shalchian:
Design and FPGA implementation of dual-stage lane detection, based on Hough transform and localized stripe features. 12-22 - Tassadaq Hussain, Saqib Amin
, Usman Zabit, Olivier D. Bernal, Thierry Bosch:
A high performance real-time Interferometry Sensor System Architecture. 23-33
- Emad Jacob Maroun, Henrik Enggaard Hansen, Andreas Toftegaard Kristensen, Martin Schoeberl:
Time-predictable synchronization support with a shared scratchpad memory. 34-42
- Thomas Hiscock, Olivier Savry, Louis Goubin:
Lightweight instruction-level encryption for embedded processors using stream ciphers. 43-52 - Jayaraj U. Kidav, N. M. Sivamangai, Perumal M. Pillai, S. Raja M:
Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems. 53-72 - Apostolos P. Fournaris, Charalambos Dimopoulos, Athanassios Moschos, Odysseas G. Koufopavlou:
Design and leakage assessment of side channel attack resistant binary edwards Elliptic Curve digital signature algorithm architectures. 73-87 - Pradeep Kumar Sharma, Santosh Biswas, Pinaki Mitra:
Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip. 88-100 - Avinash Malik, HeeJong Park, Muhammad Nadeem, Zoran Salcic:
Memory management of safety-critical hard real-time systems designed in SystemJ. 101-119 - Wei-pei Huang, Bowen P. Y. Kwan, Weiyang Ding, Biao Min, Ray C. C. Cheung, Liqun Qi, Hong Yan:
High performance hardware architecture for singular spectrum analysis of Hankel tensors. 120-127 - Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
SCAC: Weakly-coupled execution model for massively parallel systems. 128-142 - Martín Vázquez, Lucas Leiva, Gustavo Sutter:
Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. 143-158 - Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi:
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations. 159-169 - Yiwen Zhang:
System level fixed priority energy management algorithm for embedded real time application. 170-177
- Gehad I. Alkady, Ramez M. Daoud, Hassanein H. Amer, Malak Y. ElSalamouny, Ihab Adly:
Failures in fault-tolerant FPGA-based controllers - A case study. 178-184
- Habib ul Hasan Khan, Ariel Podlubne, Diana Göhringer:
Intrusive FPGA-in-the-loop debugging using a rule-based inference system. 185-194 - Julián S. Bruno, Vicenç Almenar, Javier Valls:
FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems. 195-204
- Sidartha A. L. Carvalho, Daniel C. Cunha, Abel G. Silva-Filho:
Autonomous power management in mobile devices using dynamic frequency scaling and reinforcement learning for energy minimization. 205-220 - M. Mohamed Asan Basiri, Sandeep K. Shukla:
Asynchronous hardware implementations for crypto primitives. 221-236
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