default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroelectronics Journal, Volume 62
Volume 62, April 2017
- Sayeed Ahmad, Mohit Kumar Gupta, Naushad Alam
, Mohd. Hasan:
Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory. 1-11 - Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun:
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. 12-20 - Antonie C. Alberts, Saurabh Sinha:
A modified multiphase oscillator with improved phase noise performance. 21-29 - Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. 30-37 - Changqing Chen, Ghim Boon Ang, Jeffrey Lam, Zhihong Mai:
In-depth circuits edit analysis to reveal the implantation-related defect. 38-42 - Shubhankar Majumdar, Dhrubes Biswas:
Evaluating substrate's effect on RF switch performance via Verilog-A GaN HEMT model. 43-48 - Zohaib Hameed, Kambiz Moez:
Design of impedance matching circuits for RF energy harvesting systems. 49-56 - Muhammad Yasir Qadri, Nadia N. Qadri, Martin Fleury, Klaus D. McDonald-Maier:
Energy-efficient data prefetch buffering for low-end embedded processors. 57-64 - Nemat H. El-Hassan, T. Nandha Kumar, Haider Abbas F. Almurib:
Phase change memory cell emulator circuit design. 65-71 - Jakub Gronicz, Mika Pulkkinen, Mikail Yücetas, Kari Halonen:
Design and implementation of a 2 μA temperature-compensated MEMS-based real-time clock with ±4 ppm timekeeping accuracy. 72-78 - ByeongGi Jang, Abbas Syed Hayder, SungHan Do, SungHun Cho, Dong-Soo Lee, YoungGun Pu, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee:
A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR. 79-84 - Madalin Neagu, Salvador Manich:
Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis. 85-98 - Diomadson R. Belfort, Sebastian Yuri Cavalcanti Catunda, Hassan Aboushady:
4th order capacitively-coupled LC-based ΣΔ modulator. 99-107 - Mamata Dalui, Biplab K. Sikdar:
A cellular automata based self-correcting protocol processor for scalable CMPs. 108-119 - Behnam Samadpoor Rikan, Dong-Soo Lee, Kang-Yoon Lee:
A 6-bit 4 MS/s, VCM-based sub-radix-2 SAR ADC with inverter type comparator. 120-125 - Subba Ramaiah Kodigala, Somnath Chattopadhyay, Charles B. Overton:
Design and function of GaN MESFET terahertz signal generator by finite difference method. 126-136 - J. Jeba Johannah, Reeba Korah, G. Maria Kalavathy, Sivanandham:
Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI. 137-145
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:26 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
