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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 44
Volume 44, Number 1, January 2025
- Md. Mazharul Islam
, Shamiul Alam, Garrett S. Rose, Aly E. Fathy, Sumeet Kumar Gupta, Ahmedullah Aziz:
Harnessing Unipolar Threshold Switches for Enhanced Rectification. 2-10 - Ming-Che Li, Archisman Ghosh, Shreyas Sen:
Approximate DCT and Quantization Techniques for Energy-Constrained Image Sensors. 11-24 - Rozhin Yasaei, Luke Chen, Shih-Yuan Yu, Mohammad Abdullah Al Faruque:
Hardware Trojan Detection Using Graph Neural Networks. 25-38 - Junge Xu, Fan Zhang, Wenguang Jin, Kun Yang, Zeke Wang, Weixiong Jiang, Yajun Ha:
A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators. 39-51 - Seokjun Jang, Youngki Moon, Duyeon Won, Sungho Kang:
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks. 52-64 - Yiwen Zhang, Jin-Peng Ma, Zonghua Gu:
Partitioned Scheduling With Shared Resources on Imprecise Mixed-Criticality Multiprocessor Systems. 65-76 - Wei Wei, Chen Pan, Sahidul Islam, Jishnu Banerjee, Shyamala Palanisamy, Mimi Xie:
Intermittent OTA Code Update Framework for Tiny Energy Harvesting Devices. 77-90 - Libing Deng, Gang Zeng, Ryo Kurachi, Fei Peng, Renfa Li, Guoqi Xie:
Design Synthesis and Optimization Strategy for Low Delay and High Bandwidth Utilization in Time-Sensitive Networking. 91-104 - Alexander J. Edwards, Naimul Hassan, Jared Arzate, Alexander N. Chin, Dhritiman Bhattacharya, Mustafa M. Shihab, Peng Zhou, Xuan Hu, Jayasimha Atulasimha, Yiorgos Makris, Joseph S. Friedman:
Physically Secure Logic Locking With Nanomagnet Logic. 105-118 - Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu:
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator. 119-129 - Xuan Wang, Minxuan Zhou, Tajana Rosing:
Fast-OverlaPIM: A Fast Overlap-Driven Mapping Framework for Processing In-Memory Neural Network Acceleration. 130-143 - Mengying Zhao, Yuqing Xiong, Hao Zhang, Huichuan Zheng, Dongxiao Yu, Zhaoyan Shen:
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs. 144-156 - Zehua Dong, Boyu Zhang, Yucheng Jiang, Yu Yu, Han Li, Songping Mai:
PEPPR-DWS on FPGA: Elevating Universal Parallelism and Precision Through Pulse-Enhanced Push-Relabel and Diffusion Wave Search. 157-171 - Lihan Chen, Chen Dong, Qiaowen Wu, Ximeng Liu, Xiaodong Guo, Zhenyi Chen, Hao Zhang, Yang Yang:
GNN4HT: A Two-Stage GNN-Based Approach for Hardware Trojan Multifunctional Classification. 172-185 - Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli:
Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron. 186-199 - Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie:
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. 200-213 - Tianji Liu, Yang Sun, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young:
A Unified Parallel Framework for LUT Mapping and Logic Optimization. 214-226 - Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, Bei Yu:
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits. 227-240 - Mariam Issa, Hanning Chen, Junyao Wang, Mohsen Imani:
CyberRL: Brain-Inspired Reinforcement Learning for Efficient Network Intrusion Detection. 241-250 - Jianfeng Song, Rongjian Liang, Bo Yuan, Jiang Hu:
DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow. 251-265 - Fuxun Yu, Zirui Xu, Longfei Shangguan, Di Wang, Dimitrios Stamoulis, Rishi Madhok, Nikolaos Karianakis, Ang Li, Chenchen Liu, Yiran Chen, Xiang Chen:
Rethinking Latency-Aware DNN Design With GPU Tail Effect Analysis. 266-279 - Jonti Talukdar, Akshay Vyas, Krishnendu Chakrabarty:
Detection of Voltage Droop-Induced Timing Fault Attacks Due to Hardware Trojans. 280-293 - Keyu Huang, Chunbiao Li, Xin Zhang, Irene M. Moroz, Zuohua Liu:
Constructing a Memristive Chaotic Oscillator With 2-D Offset Boosting. 294-303 - Hairong Lin, Xiaoheng Deng, Fei Yu, Yichuang Sun:
Diversified Butterfly Attractors of Memristive HNN With Two Memristive Systems and Application in IoMT for Privacy Protection. 304-316 - Shan Yu, Yair Censor, Guojie Luo:
Floorplanning With I/O Assignment via Feasibility-Seeking and Superiorization Methods. 317-330 - Wei Wang, Min Lyu, Tianyang Niu, Qiliang Li, Liangliang Xu, Yinlong Xu:
Fast Acceleration Strategies for XOR-Based Erasure Codes. 331-344 - Youngkwang Lee, Hyojun Yun, Younwoo Yoo, Sungho Kang:
PETRA: Powerful Early Termination-Based Redundancy Analysis. 345-356 - Jonti Talukdar, Arjun Chaudhuri, Eduardo Ortega, Krishnendu Chakrabarty:
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks. 357-370 - Ruiyang Ma, Jiayi Huang, Shijian Zhang, Yuan Xie, Guojie Luo:
NoCFuzzer: Automating NoC Verification in UVM. 371-384 - Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen:
Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric. 385-389 - Aibin Yan, Yuting He, Zhengfeng Huang, Wenjie Yan, Jie Cui, Xiaolei Wang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications. 390-394 - Congyi Sun, Wenqing Song, Qinyu Chen, Chenyang Dai, Yuxiang Fu, Li Li:
An Energy Efficient Residual Spiking Neural Network Accelerator With Ternary Spikes. 395-400
Volume 44, Number 2, February 2025
- Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu:
Analytical Heterogeneous Die-to-Die 3-D Placement With Macros. 402-415 - Shujie Pang, Yuhui Deng, Zhaorui Wu, Genxiong Zhang, Jie Li, Xiao Qin:
RDA: A Read-Request Driven Adaptive Allocation Scheme for Improving SSD Performance. 416-429 - Kun Cao, Mingsong Chen, Stamatis Karnouskos, Shiyan Hu:
Reliability-Aware Personalized Deployment of Approximate Computation IoT Applications in Serverless Mobile Edge Computing. 430-443 - Zehong Yu, Yixiao Yang, Zhuo Su, Rui Wang, Yang Tao, Yu Jiang:
Knight: Optimizing Code Generation for Simulink Models With Loop Reshaping. 444-457 - Grzegorz Pastuszak:
Optimization of Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders. 458-468 - Meng Lian, Hu Peng, Mengchu Li, Yushen Zhang, Tsun-Ming Tseng, Bernhard Wolfrum, Ulf Schlichtmann:
Manufacturing Cycle Time Optimization for Inkjet-Printed Electronics. 469-482 - Yangruirui Zhou, Samuel M. D. Oliveira, Radhakrishna Sanka, David McIntyre, Douglas Densmore:
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices. 483-496 - Minjin Tang, Mei Wen, Jianchao Yang, Zeyu Xue, Junzhong Shen:
SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch. 497-511 - Cong Liu, Kaibo Wu, Haikun Liu, Hai Jin, Xiaofei Liao, Zhuohui Duan, Jiahong Xu, Huize Li, Yu Zhang, Jing Yang:
A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing. 512-524 - Weihong Xu, Saransh Gupta, Justin Morris, Xincheng Shen, Mohsen Imani, Baris Aksanli, Tajana Rosing:
Tri-HD: Energy-Efficient On-Chip Learning With In-Memory Hyperdimensional Computing. 525-539 - Kui Dai, Zheren Xie, Shuanglong Liu:
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA. 540-553 - Chuliang Guo, Binglei Lou, David Boland, Philip H. W. Leong:
Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs. 554-558 - Md. Imtiaz Rashid, Benjamin Carrion Schafer:
Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis. 559-567 - Yangfan Li, Mengquan Li, Cen Chen, Xiaofeng Zou, Hongen Shao, Fengxiao Tang, Kenli Li:
SimDiff: Point Cloud Acceleration by Utilizing Spatial Similarity and Differential Execution. 568-581 - Mahsa Akhsham, Mohammad Javad Dousti, Saeed Safari:
Neural Network-Based Control of Forced-Convection and Thermoelectric Coolers. 582-591 - Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
ClipFormer: Key-Value Clipping of Transformers on Memristive Crossbars for Write Noise Mitigation. 592-601 - Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng:
Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics. 602-612 - Haining Fang, Yujuan Tan, Ao Ren, Wei Zhuang, Yang Hua, ZhiYong Qin, Duo Liu:
DSAV: A Deep Sparse Acceleration Framework for Voxel-Based 3-D Object Detection. 613-626 - Weidong Cao, Jian Gao, Tianrui Ma, Rui Ma, Mouhacine Benosman, Xuan Zhang:
RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning. 627-640 - Nicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Ulf Schlichtmann, Giovanni Squillero:
Deep Learning Strategies for Labeling and Accuracy Optimization in Microcontroller Performance Screening. 641-654 - Siyuan Liang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer: Design, Synthesis, and Adaptation. 655-668 - Shiyuan Huang, Fangxin Liu, Tao Yang, Zongwu Wang, Ning Yang, Li Jiang:
SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm. 669-683 - Zekun Deng, Chunhua Wang, Hairong Lin, Quanli Deng, Yichuang Sun:
Memristor-Based Attention Network for Online Real-Time Object Tracking. 684-695 - Andrew B. Kahng, Zhiang Wang:
DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators. 696-708 - Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Jingru Tan, Jinlong Wang, Yuming Zhang, Yimen Zhang:
LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQN. 709-722 - Zhican Wang, Gang Wang, Guanghui He:
COSA Plus: Enhanced Co-Operative Systolic Arrays for Attention Mechanism in Transformers. 723-736 - Tianyun Ma, Yuanbo Wen, Xinkai Song, Pengwei Jin, Di Huang, Husheng Han, Ziyuan Nan, Zhongkai Yu, Shaohui Peng, Yongwei Zhao, Huaping Chen, Zidong Du, Xing Hu, Qi Guo:
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression. 737-750 - Yaoxiu Lian, Xinhao Yang, Ke Hong, Yu Wang, Ningyi Xu, Guohao Dai:
A Point Transformer Accelerator With Distribution-Aware Heuristic Distance Calculation. 751-764 - Sooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang:
A New Pipelined Output Data Reducer of BOST for Improved Parallelism. 765-776 - Kamilia Tahraoui, Thibault Vayssade, François Lefevre, Laurent Latorre, Florence Azaïs:
Digital-Based Solution for the Generation of FM/PM Test Stimuli. 777-790 - Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha:
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy. 791-804
Volume 44, Number 3, March 2025
- Kuiwen Xu, Jianguo Wang, Jialin Cai, Xuetiao Ma, Qinyi Lv, Shichang Chen, Jie Liu, Jun Liu:
Flexible Inverse Design of Microwave Filter Customized on Demand With Wavelet Transform Deep Learning. 806-817 - Aidong Zhao, Ruiyu Lyu, Xuyang Zhao, Zhaori Bi, Fan Yang, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng:
VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis. 818-831 - Zhenxin Zhao, Jun Liu, Wen-Sheng Zhao, Lihong Zhang:
Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation. 832-844 - Michael Sekyere, Isaac Bruce, Ruohan Yang, Degang Chen, Colin C. McAndrew, Xiankun Jin, Chen He, Doug Garrity:
Matching Critical Analog Circuit Components Up To Third-Order Gradients for All Possible Exact Matching Ratios. 845-857 - Egor Glukhov, Tianmu Li, Vaibhav Gupta, Puneet Gupta:
Learned Approximate Computing: Algorithm Hardware Co-Optimization. 858-866 - Jayeeta Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty:
Enhancing Analog IC Security Using Randomized Obfuscation Circuits. 867-881 - Xinrui Wang, Lang Feng, Zhongfeng Wang:
PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees. 882-896 - Sirong Zhao, Guoqi Xie, Wenhong Ma, Wei Ren, Kenli Li:
vmPTP: Precise Time Protocol for Inter-VM Communication in Embedded Virtualized Systems. 897-910 - Bruno Morais, Qucheng Jiang, Gunar Schirner:
Enabling ILP-Based DSE for Multigranularity, Unified Domain Platforms With DmTSAR-ILP. 911-922 - Zhouxuan Peng, Dan Feng, Jianxi Chen, Jing Hu, Yachun Liu, Jinlei Hu, Jintong Zhang, Tianyu Wan, Zuoning Chen:
AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems. 923-936 - Sercan Aygun, M. Hassan Najafi:
Sobol Sequence Optimization for Hardware-Efficient Vector Symbolic Architectures. 937-950 - Sugil Lee, Mohammed E. Fouda, Chenghao Quan, Jongeun Lee, Ahmed M. Eltawil, Fadi J. Kurdahi:
Mitigating the Impact of ReRAM I-V Nonlinearity and IR Drop via Fast Offline Network Training. 951-960 - Amir Bahador, Mohammad Hossein Moaiyeri, Reza Ghaderi:
Algorithmically Enhanced Design of Spintronic-Based Tunable True Random Number Generator for Dependable Stochastic Computing. 961-974 - Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho:
Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. 975-988 - Liao Huang, Yue Chen, Dajiang Liu:
Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations. 989-1002 - Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin:
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections. 1003-1016 - Alessandro Tempia Calvino, Giovanni De Micheli, Alan Mishchenko, Robert K. Brayton:
Enhancing Delay-Driven LUT Mapping With Boolean Decomposition. 1017-1030 - Haoyang Sun, Cong Jiang, Xun Ye, Dan Feng, Benjamin Tan, Yuzhe Ma, Kang Liu:
Interpretable CNN-Based Lithographic Hotspot Detection Through Error Marker Learning. 1031-1044 - Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie:
Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators. 1045-1058 - Qing Yao, Jing Chen, Kemeng Yang, Jiafei Yao, Jun Zhang, Yuxuan Dai, Weihua Tang, Bo Zhang, Yufeng Guo:
Efficient Automatic Design of IGBT Structural Parameters Using Differential Evolution and Machine Learning Model. 1059-1069 - Yi-Ting Hsieh, Tung-Wei Lin, Ya-Chu Chang, Hao-Yu Wu, Iris Hui-Ru Jiang:
Graceful Register Clustering and Rebanking for Power and Timing Balancing. 1070-1083 - Suwan Kim, Taewhan Kim:
Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach. 1084-1097 - Hao-Chiang Shao, Guan-Yu Chen, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu:
LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection. 1098-1111 - Hongduo Liu, Peiyu Liao, Mengchuan Zou, Bowen Pang, Xijun Li, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu:
Layout Decomposition via Boolean Satisfiability. 1112-1125 - Yifan Hua, Shengan Zheng, Weihan Kong, Cong Zhou, Linpeng Huang:
Phoenix: A Dynamically Reconfigurable Hybrid Memory System Combining Caching and Migration. 1126-1140 - Zheng Wu, Jinyi Shen, Xiaoling Yi, Li Shang, Fan Yang, Xuan Zeng:
Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning. 1141-1154 - Po-Yao Chuang, Francesco Lorenzelli, Cheng-Wen Wu, Erik Jan Marinissen:
Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency. 1155-1168 - Jongho Park, Sangjun Lee, Hyemin Kim, Jaeyoung Joung, Jaehyun Kim, Sungho Kang:
An Efficient Low-Power BIST for Automotive SoC With Periodic Pattern Type Selection. 1169-1179 - Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson W. K. Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu:
ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling. 1180-1192 - Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, Xuan Zeng:
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers. 1193-1198 - Kun Wu, Yuncheng Liu, Hui Gao, Jun Tao, Wei Xiong, Xin Li:
Efficient Design Optimization for Diffractive Deep Neural Networks. 1199-1203 - Songyu Sun, Xiao Dong, Qi Sun, Xunzhao Yin, Quan Chen, Cheng Zhuo:
Fast Machine-Learning-Driven Supply Noise-Aware Macromodeling for High-Speed Nonlinear Drivers. 1204-1208
Volume 44, Number 4, April 2025
- Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar:
Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs. 1210-1223 - Elias Trommer, Bernd Waschneck, Akash Kumar:
Fast Retraining of Approximate CNNs for High Accuracy. 1224-1237 - Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers. 1238-1249 - Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich:
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. 1250-1261 - Zizhan Chen, Tianyu Wang, Kai Zhang, Yang Guo, Zili Shao:
A Q-Learning-Based Display Energy Optimization Scheme for Android Systems. 1262-1275 - Yihao Liu, Yaoyao Ye:
An Efficient Branch-and-Bound Routing Optimization Method for Optical NoCs. 1276-1289 - Qimin Zhou, Hui Xu, Jingyu Li, Tuo Ma, Changlin Chen:
OPASCA: Outer Product-Based Accelerator With Unified Architecture for Sparse Convolution and Attention. 1290-1303 - Jefferson D. S. Silva, Thiago Melo D. Azevedo, Israel F. Araujo, Adenilton J. da Silva:
Linear Decomposition of Approximate Multicontrolled Single Qubit Gates. 1304-1312 - Ajay B. S, Phani Pavan K, Madhav Rao:
MC-QDSNN: Quantized Deep Evolutionary SNN With Multidendritic Compartment Neurons for Stress Detection Using Physiological Signals. 1313-1325 - Yuxian Jiang, Zhan Li, Zhihan Zhang, Hao Wang, Sheng Chang:
PEDSA: High-Throughput Pipeline-Based FPGA Accelerator for Convolutional Encoder-Decoder Segmentation Networks. 1326-1339 - Lan Huang, Teng Gao, Yang Feng, Kangping Wang:
MCSSA: A Stream-Based Multiconcurrency Systolic Sorting Array Combining Merge Tree. 1340-1353 - Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints. 1354-1365 - Samuel Coward, Theo Drane, George A. Constantinides:
Constraint-Aware E-Graph Rewriting for Hardware Performance Optimization. 1366-1379 - Yuhao Zhou, Zhen Wang, Xiangxue Kong, Hongyang Pan, Zhenxue He, Ying Zhang, Jianhui Jiang, Limin Xiao, Xiang Wang:
Multiobjective Optimization in Logic Synthesis Based on TB-RM Dual Logic. 1380-1393 - Wenqian Zhao, Shuo Yin, Chen Bai, Zixiao Wang, Bei Yu:
BAQE: Backend-Adaptive DNN Deployment via Synchronous Bayesian Quantization and Hardware Configuration Exploration. 1394-1405 - Jun Liu, Zhenglun Kong, Pu Zhao, Weihao Zeng, Hao Tang, Xuan Shen, Changdi Yang, Wenbin Zhang, Geng Yuan, Wei Niu, Xue Lin, Yanzhi Wang:
TSLA: A Task-Specific Learning Adaptation for Semantic Segmentation on Autonomous Vehicles Platform. 1406-1419 - Jienan Chen, Jun Tu, Hao Wang, Jie Zheng, Hao Liu, Shenglong Bai, Xiantuo He, Weikang Qian:
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method. 1420-1433 - Tingting Li, Liqiang Lu, Ziming Zhao, Ziqi Tan, Siwei Tan, Jianwei Yin:
QuST: Optimizing Quantum Neural Network Against Spatial and Temporal Noise Biases. 1434-1447 - Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie:
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. 1448-1461 - Xin Jian, Junyi Zhang, Yaoyao Li, Tianyu Yang, Amr Tolba, Osama Alfarraj, Keping Yu, Mohsen Guizani:
CircuitGTL: An Intelligent Circuit Design Methodology Across Electromagnetic Topologies With Graph Transfer Learning. 1462-1474 - Wenxun Wang, Wenyu Sun, Yongpan Liu:
Improving Transformer Inference Through Optimized Nonlinear Operations With Quantization-Approximation-Based Strategy. 1475-1488 - Zhixuan Dong, Longlong Yang, Cuiyang Ding, Changhao Yan, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions. 1489-1502 - Yihang Ma, Shijie Wang, Chao Yu, Jialin Cai:
Threshold Optimized DVR Model for RF Power Amplifier Using Particle Swarm Algorithm for 5G Application. 1503-1515 - Bing Wu, Yibo Liu, Jinpeng Liu, Huan Cheng, Xueliang Wei, Wei Tong, Dan Feng:
FADESIM: Enable Fast and Accurate Design Exploration for Memristive Accelerators Considering Nonidealities. 1529-1543 - Yang Dai, Leiyu Gao, Yukun Li, Jing Zuo, Yue Zhang, Wu Zhao:
Effect of Gate Structure on the Performances of Lateral AlGaN/GaN High-Electron-Mobility Avalanche-Transit-Time Transistor. 1544-1552 - Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files. 1553-1566 - Xingbo Wang, Chenxi Feng, Xinyu Kang, Qi Wang, Yucong Huang, Terry Tao Ye:
RV-SCNN: A RISC-V Processor With Customized Instruction Set for SNN and CNN Inference Acceleration on Edge Platforms. 1567-1580 - Hayoung Lee, Juyong Lee, Sungho Kang:
A Robust Test Architecture for Low-Power AI Accelerators. 1581-1594 - Zhengfeng Huang, Lei Ai, Xinyu Jiang, Xiaolei Wang, Yingchun Lu, Jun Pan, Tai Song, Xiaoqing Wen, Aibin Yan:
Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Based on Cross-Interlocking. 1595-1608 - Ranyang Zhou, Jacqueline T. Liu, Sabbir Ahmed, Nakul Kochar, Adnan Siraj Rakin, Shaahin Angizi:
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses. 1609-1613 - Yao Tong, Quan Chen:
A Predictive Readout Fidelity Model Considering Nonidealities for Readout Circuit Design in Superconducting Quantum Computers. 1614-1618
Volume 44, Number 5, May 2025
- Xuan Wang, Xiaomi Zhou, Shanshan Han, Ruicheng Dai, Xiaolong Shen, Menghui Xu, Leibin Ni, Wei Wu, Weikang Qian:
AccALS 2.0: Accelerating Approximate Logic Synthesis by Simultaneous Selection of Multiple Local Approximate Changes. 1620-1633 - Yao Zhang, Ming Tang:
ESM: A Plug-in Power Side Channel Shuffling Protection for Scalar Processors. 1634-1647 - Mieszko Ferens, Edlira Dushku, Sokol Kosta:
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks. 1648-1661 - Zhaohui Chen, Zhen Gu, Yanheng Lu, Xuanle Ren, Ruiguang Zhong, Wen-Jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie:
SAFE: A Scalable Homomorphic Encryption Accelerator for Vertical Federated Learning. 1662-1675 - Qingqiang He, Nan Guan, Shuai Zhao, Mingsong Lv:
Multipath Bound for DAG Tasks. 1676-1689 - Donghua Li, Hui Sun, Xiao Qin:
iCache: An Intelligent Cache Allocation Strategy for Multitenant in High-Performance Solid-State Disks. 1690-1703 - Liqiang Lu, Wuwei Tian, Xinghui Jia, Zixuan Song, Siwei Tan, Jianwei Yin:
SmartQCache: Fast and Precise Pulse Control With Near-Quantum Cache Design on FPGA. 1704-1716 - Guanglei Xu, Yuchong Hu, Dan Feng, Wenpeng He, Junyuan Huang:
CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory. 1717-1730 - Hanchen Jin, Zichao Yue, Zhongyuan Zhao, Yixiao Du, Chenhui Deng, Nitish Srivastava, Zhiru Zhang:
Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns. 1731-1744 - Xiaotian Sun, Xinyu Wang, Wanqian Li, Yinhe Han, Xiaoming Chen:
PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators. 1745-1759 - Jiahao Cai, Hamza Errahmouni Barkam, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin:
A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search. 1760-1773 - Hao Fu, Mingzheng Zhu, Fangzheng Chen, Chi Zhang, Jun Wu, Wei Xie, Xiang-Yang Li:
Effective and Efficient Parallel Qubit Mapper. 1774-1787 - Asif Mirza, Ryan E. Gloekler, Sudeep Pasricha, Mahdi Nikdast:
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators. 1788-1792 - Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima:
CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications. 1793-1806 - Roberto Bosio, Filippo Minnella, Teodoro Urso, Mario R. Casu, Luciano Lavagno, Mihai T. Lazarescu, Paolo Pasini:
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. 1807-1818 - Shuai Yuan, Weifeng He, Zhenhua Zhu, Fangxin Liu, Zhuoran Song, Guohao Dai, Guanghui He, Yanan Sun:
HyCTor: A Hybrid CNN-Transformer Network Accelerator With Flexible Weight/Output Stationary Dataflow and Multicore Extension. 1819-1832 - Anmol Singh Narwariya, Pabitra Das, Saqib Khursheed, Amit Acharyya:
Noninvasive Methodology for the Age Estimation of ICs Using Gaussian Process Regression. 1833-1844 - Xiong Cheng, Pengfei Zhang, Yiqi Zhou, Rui Wang, Zhixiang Zhai, Youyou Fan, Wenhua Gu, Xiaodong Huang, Daying Sun:
Bridging the Gap From Vague Design Requirements to Feasible Structure: Deep Learning Model for Parameterized MEMS Sensor Design. 1845-1855 - Xunzhao Yin, Qingrong Huang, Hamza Errahmouni Barkam, Franz Müller, Shan Deng, Alptekin Vardar, Sourav De, Zhouhang Jiang, Mohsen Imani, Ulf Schlichtmann, Xiaobo Sharon Hu, Cheng Zhuo, Thomas Kämpfe, Kai Ni:
A Homogeneous FeFET-Based Time-Domain Compute-in-Memory Fabric for Matrix-Vector Multiplication and Associative Search. 1856-1868 - Yuxiao Jiang, Kai Ni, Thomas Kämpfe, Cheng Zhuo, Zheyu Yan, Xunzhao Yin:
CSA-CiM: Enhancing Multifunctional Computing-in-Memory With Configurable Sense Amplifiers. 1869-1873 - Liang Chen, Wenxing Zhu, Min Tang, Sheldon X.-D. Tan, Jun-Fa Mao, Jianhua Zhang:
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis. 1874-1886 - Xiaoming Chen:
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations. 1887-1900 - Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi:
Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing. 1901-1914 - Ziyang Yu, Su Zheng, Wenqian Zhao, Shuo Yin, Xiaoxiao Liang, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine. 1915-1927 - Hongxi Wu, Xingquan Li, Liang Chen, Bei Yu, Wenxing Zhu:
Delay-Driven Rectilinear Steiner Tree Construction. 1928-1941 - Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization. 1942-1953 - Pruek Vanna-Iampikul, Seungmin Woo, Serhat Erdogan, Lingjun Zhu, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, Madhavan Swaminathan, Sung Kyu Lim:
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits. 1954-1967 - Bin-Han Lu, Peng Wang, Zhao-Yun Chen, Huan-Yu Liu, Tai-Ping Sun, Peng Duan, Yu-Chun Wu, Guo-Ping Guo:
CAMEL: Physically Inspired Crosstalk-Aware Mapping and Gate Scheduling for Frequency-Tunable Quantum Chips. 1968-1980 - Irith Pomeranz:
Direct Search Procedure for Functional Compaction With Improved Fault Coverage. 1981-1990 - Irith Pomeranz:
COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set. 1991-1999 - Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel:
SRAM Periphery Testing Using the Cell-Aware Test Methodology. 2000-2013 - Joonsik Yoon, Hayoung Lee, Youngki Moon, Seung Ho Shin, Sungho Kang:
A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM. 2014-2025 - Xiong Cheng, Pengfei Zhang, Yiqi Zhou, Daying Sun, Wenhua Gu, Yutao Yue, Xiaodong Huang:
Corrections to "A Bidirectional Deep Learning Approach for Designing MEMS Sensors". 2026-2027
Volume 44, Number 6, June 2025
- Supriyo Maji, Hyungjoo Park, Gi moon Hong, Souradip Poddar, David Z. Pan:
Multiobjective Optimization for Common-Centroid Placement of Analog Transistors. 2029-2039 - Chang Meng, Alan Mishchenko, Weikang Qian, Giovanni De Micheli:
Efficient Resubstitution-Based Approximate Logic Synthesis. 2040-2053 - Kilian Pfeiffer, Konstantinos Balaskas, Kostas Siozios, Jörg Henkel:
Energy-Aware Heterogeneous Federated Learning via Approximate DNN Accelerators. 2054-2066 - Abdul Khader Thalakkattu Moosa, Benjamin Tan, Ramesh Karri:
Scaling Attacks on Large Logic-Locked Designs. 2067-2079 - Zhiyuan Xiao, Chen Wang, Jian Shen, Q. M. Jonathan Wu, Debiao He:
Less Traces Are All It Takes: Efficient Side-Channel Analysis on AES. 2080-2092 - Wen Sheng Lim, Yu-Cheng Chen, Yu-Hsuan Chu, Chia-Heng Tu, Yuan-Hao Chang:
iSAFE: Enabling Evenness of Data Freshness in Multipriority Networked Intermittent Systems. 2093-2104 - Xingyue Qian, Chenyang Lv, Zhezhi He, Weikang Qian:
A Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization. 2105-2118 - Yongshang Li, Yu Zhang, Haoning Deng, Mingyu Chen, Zhenyu Li:
PauliForest: Connectivity-Aware Synthesis and Pauli-Oriented Qubit Mapping for Near-Term Quantum Simulation. 2119-2129 - Gaurav Narang, Janardhan Rao Doppa, Partha Pratim Pande:
Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units. 2130-2143 - Daniel Schönberger, Stefan Hillmich, Matthias Brandl, Robert Wille:
Shuttling for Scalable Trapped-Ion Quantum Computers. 2144-2155 - Ling Zhang, Xuefei Yang, Zhenlong Wan, Hang Liu, Wei Gu, Pingjing Liu, Qilin Dai, Shanwei Ye, Yingcheng Lin:
A High-Performance RDMA NIC With Ultrahighly Scalable Connections. 2156-2167 - Bachir Madani, Mohamed Salah Azzaz, Said Sadoudi, Redouane Kaibou, Bruno da Silva:
Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs. 2168-2180 - Hans Jakob Damsgaard, Konstantin Hoßfeld, Jari Nurmi, Thomas B. Preußer:
Parallel Accurate Minifloat MACCs for Neural Network Inference on Versal FPGAs. 2181-2194 - Anastasios Dimitriou, Lei Xun, Jonathon S. Hare, Geoff V. Merrett:
Realization of Early-Exit Dynamic Neural Networks on Reconfigurable Hardware. 2195-2203 - Chen Chen, Haoyang Zhang, Kaicheng Guo, Xingzi Yu, Weidong Qiu, Zhengwei Qi, Haibing Guan:
Exploring Efficient Hardware Accelerator for Learning-Based Image Compression. 2204-2217 - Chang Wu:
FPGA Technology Mapping With Adaptive Gate Decomposition. 2218-2225 - Jiaming Xu, Shan Huang, Jinhao Li, Guyue Huang, Yuan Xie, Yu Wang, Guohao Dai:
Enabling Efficient Sparse Multiplications on GPUs With Heuristic Adaptability. 2226-2239 - Han Zhang, Zhenyu Fan, Yinhao Zhou, Ying Li:
B-HTRecognizer: Bitwise Hardware Trojan Localization Using Graph Attention Networks. 2240-2252 - Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang:
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. 2253-2263 - Qing Zhang, Yuhang Zhang, Rui Chen, Wei Lu, Huajie Huang, Zhiqiang Li, Yongfu Li:
pFed-Litho: Lithography Modeling With a Personalized Federated Learning-Based Framework. 2264-2276 - Hao Lv, Lei Zhang, Ying Wang:
Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning. 2277-2286 - Maria Emmerich, Philipp Ebner, Robert Wille:
Automated Design for Multiorgan-on-Chip Geometries. 2287-2299 - Lijie Xie, Jiawei Shen, Peilong Feng, Andrea Mifsud, Adil Malik, Amir Nassibi, Vichaya Manatchinapisit, Christos Papavassiliou:
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation. 2300-2313 - Joshua Hanson, Paul Kuberry, Biliana S. Paskaleva, Pavel B. Bochev:
Nonintrusive Data-Driven Model Order Reduction for Circuits Based on Hammerstein Architectures. 2314-2327 - Wenjie Zhong, Tao Sun, Jiantao Zhou, Zhuowei Wang, Xiaoyu Song:
A Reduced State-Space Generation Method for Concurrent Systems Based on CPN-PR Model. 2328-2342 - Shunxiang Lan, Min Tang:
Equivalent Thermal Conductance Network (ETCN) Model for Domain Decomposition and Efficient Thermal Simulation of GaN HEMTs. 2343-2352 - Jie Xiao, Shuiliang Chai, Yanjiao Gao, Yuhao Huang, Fan Zhang, Tieming Chen:
HTs-GCN: Identifying Hardware Trojan Nodes in Integrated Circuits Using a Graph Convolutional Network. 2353-2366 - Xing Guo, Jiajia Zhang, Xu Meng, Zhenmin Li, Xiaoqing Wen, Patrick Girard, Bin Liang, Aibin Yan:
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications. 2367-2377 - Hao Gu, Youwen Wang, Xinglin Zheng, Keyu Peng, Ziran Zhu, Jianli Chen, Jun Yang:
Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction. 2378-2391 - Xiangpeng Hou, Junlong Zhou, Liying Li, Mingzhou Zhao, Peijin Cong, Zebin Wu, Shiyan Hu:
ILRM: Imitation Learning-Based Resource Management for Integrated CPU-GPU Edge Systems With Renewable Energy Sources. 2392-2397 - Xuhang Wang, Qiyue Huang, Xing Li, Haozhe Jiang, Qiang Xu, Xiaoyao Liang, Zhuoran Song:
Vision Transformer Acceleration via a Versatile Attention Optimization Framework. 2398-2411 - Huize Li, Dan Chen, Tulika Mitra:
SPLIM: Bridging the Gap Between Unstructured SpGEMM and Structured In-Situ Computing. 2412-2423 - Longlong Lu, Minxue Pan, Yifei Lu, Xuandong Li:
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection. 2424-2437
Volume 44, Number 7, July 2025
- Seunghyun Hwang, Michael Joseph Smith, Vinicius C. Do Nascimento, Qiang Qiu, Cheng-Kok Koh, Ganesh Subbarayan, Dan Jiao:
Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks. 2439-2450 - Chi Lai, Shi-Yu Huang:
Connectivity-Agnostic Built-In Self-Repair of Interconnects in a Chiplet IC. 2451-2460 - Shan Li, Zheliang Xu, Haihua Shen, Huawei Li:
Oxpecker: Leaking Secrets via Fetch Target Queue. 2461-2474 - Chaoqun Shen, Gang Qu, Jiliang Zhang:
Nested Speculative Execution Attacks via Runahead. 2475-2487 - Matteo Perotti, Samuel Riedel, Matheus A. Cavalcante, Luca Benini:
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. 2488-2502 - Yosab Bebawy, Aniebiet Micheal Ezekiel, Roman Obermaisser:
Superscalar Time-Triggered Versatile-Tensor Accelerator. 2503-2515 - Wenjing Xiao, Jianyu Wang, Dan Chen, Chenglong Shi, Xin Ling, Min Chen, Thomas Wu:
ChainPIM: A ReRAM-Based Processing-in-Memory Accelerator for HGNNs via Chain Structure. 2516-2529 - Yunping Zhao, Sheng Ma, Yuhua Tang, Hengzhu Liu, Dongsheng Li:
Tradeoff Performance and Energy Efficiency by Optimizing the Data Flow for PIM Architectures. 2530-2543 - Chen Zhang, Shijie Cao, Guohao Dai, Chenbo Geng, Zhuliang Yao, Wencong Xiao, Yunxin Liu, Ming Wu, Lintao Zhang, Guangyu Sun, Zhigang Ji, Runsheng Wang, Ru Huang:
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference. 2544-2557 - Jorge Koronis, Oscar Garnica, J. Ignacio Hidalgo, Juan Lanchares:
Reverse-Engineering Optimization Techniques of High-Level Synthesis: Practical Insights Into Accelerating Applications With AMD-Xilinx Vitis. 2558-2570 - Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli:
Area-Oriented Resubstitution For Networks of Look-Up Tables. 2571-2584 - Junfeng Liu, Liwei Ni, Lei Chen, Xing Li, Qinghua Zhao, Xingquan Li, Shuai Ma:
A Delay-Driven Iterative Technology Mapping Framework. 2585-2598 - Li Lu, Junchao Chen, Aneesh Balakrishnan, Markus Ulbricht, Milos Krstic:
Accelerate SEU Simulation-Based Fault Injection With Spatio-Temporal Graph Convolutional Networks. 2599-2612 - Jiaye Li, Jiagang Song, Jinjing Shi, Hang Xu, Hao Yu, Gang Chen, Shichao Zhang:
Robust Quantum Feature Selection With Sparse Optimization Circuit. 2613-2626 - Lancheng Zou, Su Zheng, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong:
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. 2627-2640 - Zhongpeng Ni, Jing Xia, Xinyu Zhou, Wa Kong, Heng Zhang, Chao Yu, Xiao-Wei Zhu:
Design and Analysis of Optimization Method for Ultra-Wideband PA Based on Improved MOEA/D Algorithm Using Mixed Objective Function. 2641-2654 - Haibin Zhao, Priyanjana Pal, Michael Hefenbrock, Yuhong Wang, Michael Beigl, Mehdi B. Tahoori:
Neural Evolutionary Architecture Search for Compact Printed Analog Neuromorphic Circuits. 2655-2668 - Yuhan Zhu, Genggeng Liu, Wenzhong Guo, Xing Huang:
FTCD: Fault-Tolerant Co-Design of Flow and Control Layers for Fully Programmable Valve Array Biochips. 2669-2682 - Arun Sankar Eenhakkattu Mana, Navajit Singh Baban, Maolin Zhang, Dongping Wang, Hanbin Ma, Tsung-Yi Ho, Krishnendu Chakrabarty:
Optimization of Droplet Routing in Microfluidic Biochips Using Calibrated Droplet-Shape Morphing. 2683-2696 - Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Jiaxi Jiang, Ziyi Wang, Peng Xu, Hong Xu, Bei Yu:
Prerouting Timing Prediction Across Different Technology Nodes. 2697-2710 - Zhenkun Lin, Genggeng Liu, Xing Huang, Yibo Lin, Jixin Zhang, Wen-Hao Liu, Ting-Chi Wang:
A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree. 2711-2724 - Yuzhou Chen, Zhenyu Li, Dongxu Lyu, Yansong Xu, Guanghui He:
Neural Rendering Acceleration With Deferred Neural Decoding and Voxel-Centric Data Flow. 2725-2737 - Changxu Liu, Hao Zhou, Lan Yang, Zheng Wu, Patrick Dai, Yinlong Li, Shiyong Wu, Fan Yang:
Myosotis: An Efficiently Pipelined and Parameterized Multiscalar Multiplication Architecture via Data Sharing. 2738-2750 - Qijun Zhang, Mengming Li, Andrea Mondelli, Zhiyao Xie:
An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities. 2751-2764 - Xuyang Zhao, Tianning Gao, Zheng Wu, Zhaori Bi, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration. 2765-2778 - Shaoqi Yang, Meng Zhang, Xuepeng Zhan, Peng Guo, Xiaohuan Zhao, Guangkuo Yang, Xinyi Guo, Jixuan Wu, Fei Wu, Jiezhi Chen:
Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling. 2779-2788 - Seung Ho Shin, Minho Cheong, Hayoung Lee, Byungsoo Kim, Sungho Kang:
A Novel CNN-Based Redundancy Analysis Using Parallel Solution Decision. 2789-2802 - Boyu Li, Zongwei Zhu, Weihong Liu, Qianyue Cao, Changlong Li, Cheng Ji, Xi Li, Xuehai Zhou:
Magnifier: A Chiplet Feature-Aware Test Case Generation Method for Deep Learning Accelerators. 2803-2816 - Hao Su, Wei Hu, Xuelin Zhang, Dan Zhu, Lingjuan Wu:
Toward Precise and Explainable Hardware Trojan Localization at LUT Level. 2817-2821 - Gil-Ho Kwak, Jaeho Kim, Tae-Hwan Kim:
SR-BIP: A Soft Error-Resilient Binary Neural Network Inference Processor. 2822-2826 - Ning Li, Dejian Li, Zhipeng Wu, Peiguang Jing, Sio Hang Pun, Yu Liu:
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration. 2827-2831 - Yanqiu Li, Zhiqiang Wang, Kuan Wang, Jun Yuan, Guoqing Xin, Xiaojie Shi:
A Modeling Method of Reverse Biased Electric Field for JBS Diodes Based on Schwarz-Christoffel Transformation. 2832-2835 - Christodoulos Peltekis, Giorgos Dimitrakopoulos:
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks. 2836-2840
Volume 44, Number 8, August 2025
- Pratyush Dhingra, Janardhan Rao Doppa, Partha Pratim Pande:
Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures. 2842-2855 - Shangshang Yao:
Approx-T: Design Methodology for Approximate Multiplication Units via Taylor-Expansion. 2856-2869 - Jiang Li, Yijun Cui, Chongyan Gu, Chenghua Wang, Weiqiang Liu, Shahar Kvatinsky:
A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme. 2870-2882 - Hongfei Wang, Caixue Wan, Hai Jin:
Efficient Modeling Attack on Multiplexer PUFs via Kronecker Matrix Multiplication. 2883-2896 - Hongyi Li, Qingyuan Yang, Songchen Ma, Rong Zhao, Xinglong Ji:
RoboSpike: Fully Utilizing the Heterogeneous System With Subcallback Scheduling in ROS 2. 2897-2910 - Zhaoyang Zeng, Yujuan Tan, Zhulin Ma, Jiali Li, Sanle Zhao, Duo Liu, Xianzhang Chen, Ao Ren:
CMCache: An Adaptive Cross-Level Data Placement Method for Multilevel Cache. 2911-2924 - Yin Deng, Guoqi Xie, Chenglai Xiong, Sirong Zhao, Wei Ren, Kenli Li:
Zram Instance Pool Framework for Adaptive Memory Compression in Resource-Sensitive Embedded Operating Systems. 2925-2938 - Liyan Chen, Pengyu Liu, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing:
Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System. 2939-2951 - Shang Wang, Qi Cao, Yongqiang Wang, Hang Chen, Zhenjiao Chen, Feng Liang:
Single-Pass: An Operation Unit-Based In-Memory Computing Architecture for Sparse Neural Networks. 2952-2965 - Yunqi Huang, Dingchao Gao, Shenggang Ying, Sanjiang Li:
DasAtom: A Divide-and-Shuttle Atom Approach to Quantum Circuit Transformation. 2966-2978 - Yufei Yang, Chenhao Xie, Liansheng Liu, Xiyuan Peng:
DynMap: A Heuristic Dynamic Mapper for CGRA Multitask Dynamic Resource Allocation. 2979-2991 - Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Honglan Jiang, Zhigang Mao, Qin Wang:
MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. 2992-3005 - Aoxiang Qin, Rongjie Yang, Minghua Shen, Nong Xiao:
PBS: Program Behavior-Aware Scheduling for High-Level Synthesis. 3006-3019 - Yongan Zhang, Yuecheng Li, Syed Shakib Sarwar, Huseyin Ekin Sumbul, Yonggan Fu, Haoran You, Cheng Wan, Yingyan Lin:
Re-CATA: Real-Time and Flexible Accelerator Design Framework for On-Device Codec Avatars. 3020-3033 - Rongliang Fu, Chao Wang, Bei Yu, Tsung-Yi Ho:
TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. 3034-3045 - Anup Kumar Biswas, Dimitri Kagaris:
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis. 3046-3059 - Wei Zi, Junhong Nie, Xiaoming Sun:
Shallow Quantum Circuit Implementation of Symmetric Functions With Limited Ancillary Qubits. 3060-3072 - Chee-An Yu, Yu-Tung Liu, Yu-Hao Cheng, Shao-Yu Wu, Hung-Ming Chen, C.-C. Jay Kuo:
GIRD: A Green IR-Drop Estimation Method. 3073-3084 - Ping Li, Zhong Guan:
Compact Geometric Feature Representation for Improved Capacitance Pattern-Matching in Parasitic Extraction. 3085-3098 - Dongho Kim, Junseo Lee, Seokhun Kim, Jihwan Park, Sangheon Lee, Hanwool Jeong:
Bayesian Learning-Enhanced Embedded Memory Design With Automated Circuit Variant Generation. 3099-3111 - Chandramouli N. Amarnath, Mohamed Mejri, Jackson Isenberg, Abhijit Chatterjee:
Error Resilient Online Reinforcement Learning Using Adaptive Statistical Checks. 3112-3125 - Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design. 3126-3139 - Xiao Dong, Songyu Sun, Yangfan Jiang, Jingtong Hu, Dawei Gao, Zhiguo Shi, Cheng Zhuo:
SPIRAL+: Efficient Signal-Power Integrity Co-Analysis for Interchiplet Links Validation. 3140-3153 - Zihao Lin, Haisen Zhang, Peng Gao, Fei Yu, Tingting Wu, Xiaoming Xiong, Shuting Cai:
GNN-Based Timing Prediction in Prerouting Stage With Multitask Learning Strategy. 3154-3164 - James A. Boyle, Mark Plagge, Suma George Cardwell, Frances S. Chance, Andreas Gerstlauer:
SANA-FE: Simulating Advanced Neuromorphic Architectures for Fast Exploration. 3165-3178 - Xin Zhang, Chunbiao Li, Tengfei Lei, Herbert Ho-Ching Iu, Tomasz Kapitaniak:
Coexisting Hyperchaos in a Memristive Neuromorphic Oscillator. 3179-3188 - Jaehyuk Lim, Donghwan Han, Juho Sung, Seokchan Yoon, Sanghyun Kang, Gwon Kim, Hyoung Won Baac, Changhwan Shin:
Device Design Guidelines to Boost Up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter. 3189-3196 - Dawei Wang, Qing Zhang, Hang Wan, Wen-Sheng Zhao:
Finite Element Approach Based Numerical Framework for Device Simulator. 3197-3207 - Zhenyu Wang, Pragnya Sudershan Nalla, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-Sun Seo, Vidya A. Chhabria, Jeff Zhang, Chaitali Chakrabarti, Ümit Y. Ogras, Yu Cao:
HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing. 3208-3221 - Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu:
IncreMacro: Incremental Macro Placement Refinement. 3222-3235 - Chaehyeon Shin, Jongsun Park:
DBB-ECC: Random Double Bit and Burst Error Correction Code for HBM3. 3236-3240 - Irith Pomeranz:
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test. 3241-3245
Volume 44, Number 9, September 2025
- Changhai Ou, Zhenfang Qiu, Xingshuo Han, Fan Zhang, Shihui Zheng, Fei Yan:
MinMaxEntropy: Bound Model Errors for Side-Channel Leakages From Information Theory. 3247-3259 - Wei-Che Cheng, Shih-Hsu Huang, Jin-Fu Li:
Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs. 3260-3273 - He Xu, Xiaokang Shi, Hansheng Liu, Yanwen Wang, Jiwu Lu, Haibo Zeng, Renfa Li, Di Wu:
MULSAM: Multidimensional Attention With Hardware Acceleration for Efficient Intrusion Detection on Vehicular CAN Bus. 3274-3288 - Yifan Cheng, Zehong Yu, Zhuo Su, Ting Chen, Xiaosong Zhang, Yu Jiang:
AccSiM: State-Aware Simulation Acceleration for Simulink Models. 3289-3302 - Zhangwei Yu, Yan Liu, Renfa Li, Wanli Chang:
LIDS: A Lightweight Intrusion Detection System for Controller Area Network. 3303-3312 - Hua Feng, Debao Wei, Qi Wang, Yongchao Wang, Liyan Qiao, Zongliang Huo:
Temperature Effects of Program Operation in 3-D nand Flash Memory: Observations, Analysis, and Solutions. 3313-3322 - Sosei Ikeda, Hiromitsu Awano, Takashi Sato:
Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir. 3323-3335 - Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Tommaso Marinelli, Valerio Pica, Gouri Sankar Kar:
Asymmetric and Adaptive Error Correction in STT-MRAM. 3336-3349 - Xinyu Chen, Zilu Chen, Pengcheng Zhu, Xueyun Cheng, Zhijin Guan:
Circuit Partitioning and Transmission Cost Optimization in Distributed Quantum Circuits. 3350-3362 - Shounak Chakraborty, Thanasin Bunnam, Jedsada Arunruerk, Sukarn Agarwal, Shengqi Yu, Rishad A. Shafik, Magnus Själander:
HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM-Based Caches. 3363-3368 - Rongliang Fu, Robert Wille, Nobuyuki Yoshikawa, Tsung-Yi Ho:
Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits. 3369-3380 - Satanu Maity, Manojit Ghose, Sudeep Pasricha:
A Framework for Near Memory Processing With Computation Offloading and Load Balancing. 3381-3394 - Yue Tang, Alex K. Jones, Jinjun Xiong, Peipei Zhou, Jingtong Hu:
MTrain: Enable Efficient CNN Training on Heterogeneous FPGA-Based Edge Servers. 3395-3408 - Boyu Long, Yinhe Han, Xian-He Sun, Xiaoming Chen:
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis. 3409-3422 - Muhammad Farhan Azmine, Ruizhe Li, Gauri Sharma, Yang Yi:
SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function. 3423-3436 - Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha:
Fast FPGA Accelerator of Graph Cut Algorithm With Threshold Global Relabel and Inertial Push. 3437-3450 - Haishuang Fan, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse. 3451-3464 - Yingxue Gao, Teng Wang, Yang Yang, Lei Gong, Xianglan Chen, Chao Wang, Xi Li, Xuehai Zhou:
Advancing Neuromorphic Architecture Toward Emerging Spiking Neural Network on FPGA. 3465-3478 - Haopeng Yan, Ying Wang, Peng Gao, Fei Yu, Yuzhe Ma, Xiaoming Xiong, Shuting Cai:
A Lightweight Heterogeneous Graph Embedding Framework for Hotspot Detection. 3479-3489 - Runzhen Xue, Mingyu Yan, Dengke Han, Ziheng Xiao, Zhimin Tang, Xiaochun Ye, Dongrui Fan:
SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration. 3490-3503 - Shen Zhang, Bin Ning, Guangyao Yan, Xinzhe Liu, Weixiong Jiang, Yajun Ha:
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models. 3504-3517 - Zirui Lian, Qianyue Cao, Chao Liang, Jing Cao, Zongwei Zhu, Zhi Yang, Cheng Ji, Changlong Li, Xuehai Zhou:
HaloFL: Efficient Heterogeneity-Aware Federated Learning Through Optimal Submodel Extraction and Dynamic Sparse Adjustment. 3518-3531 - Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari:
Optimizing DNN Inference on Multi-accelerator SoCs at Training-Time. 3532-3545 - Ruifeng Tu, Meng Zhang, Changsheng Xie, Fei Wu:
RaPC: Raw Bit Error Rate Aware Polar Coding for 3-D nand Flash Memory. 3546-3559 - K. Madhu Kiran, Rohit Dhiman:
Sampling-Biorthogonal Time-Domain Technique for Temperature-Dependent Transient Analysis of Coaxial-TGVs in 3-D Integration. 3560-3570 - Jaehyuk Lim, Seokchan Yoon, Juho Sung, Sanghyun Kang, Gwon Kim, Hyoung Won Baac, Changhwan Shin:
Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM. 3571-3580 - Na Bai, Fudong Wang, Yaohua Xu, Shaowei Wang, Xiaoqing Wen:
Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments. 3581-3591 - Qianqi Zhao, Jing He, Tong Qu, Wentian Wu, Qianhui Li, Qi Wang, Zongliang Huo, Tian-Chun Ye:
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash. 3592-3605 - Heetae Kim, Hyojoon Yun, Doohyun Yoon, Sungho Kang:
An Efficient Test Scheduling Method Based on Dynamic Pairing. 3606-3616 - Jian Hu, Zhenlei Liu:
Context Aware Deep Learning-Based Fault Localization for Hardware Design Code. 3617-3628 - Huaixi Lu, Yue Xing, Aarti Gupta, Sharad Malik:
Hierarchical Formal Verification of Hardware. 3629-3642 - Kai Wang, Dejun Xu, Jing Tian:
An Improved Two-Step Attack on Lattice-Based Cryptography: A Case Study of Kyber. 3643-3647 - Hyojoon Yun, Hyeonchan Lim, Hayoung Lee, Sungho Kang:
Multistage Enhanced Diagnosis With Fault Candidate Reduction. 3648-3652
Volume 44, Number 10, October 2025
- Peng Xu, Jindong Tu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu:
PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation. 3654-3667 - Suhasini Komarraju, Akhil Tammana, Chandramouli N. Amarnath, Abhijit Chatterjee:
OATT: Outlier-Oriented Alternative Testing and Post-Manufacture Tuning of Analog/Mixed-Signal Circuits. 3668-3682 - Zhenyu Guan, Yongqing Zhu, Luchang Lei, Hongyang Jia, Yi Chen, Bo Zhang, Changrui Ren, Jin Dong, Song Bian:
MCHEAS: Optimizing Large-Parameter NTT Over Multicluster In-Situ FHE Accelerating System. 3683-3696 - Le Wu, Liji Wu, Xiangmin Zhang:
Catch the Star: Weight Recovery Attack Using Side-Channel Star Map Against DNN Accelerator. 3697-3709 - Jiaojiao Wu, Li Cai, Zhigang Cai, Fengxiang Zhang, Jianwei Liao:
Improving I/O Performance and Fairness in NVMe SSDs With Pooling Portions of Cache Partitions. 3710-3723 - Wentian Wu, Qianhui Li, Tong Qu, Qi Wang, Zongliang Huo, Tian-Chun Ye:
POFGSP: Priority-Based Out-of-Order Scheduling and Fine-Grain Status Polling for SSD Performance Improvement. 3724-3737 - Fang-Yi Gu, Ing-Chao Lin, Bing Li, Ulf Schlichtmann, Grace Li Zhang:
Efficient Model Switching in RRAM-Based DNN Accelerators. 3738-3751 - Wei Zhao, Dan Feng, Wei Tong, Xueliang Wei, Bing Wu:
CMD: A Cache-Assisted GPU Memory Deduplication Architecture. 3752-3763 - Michel Takken, Maria Emmerich, Robert Wille:
An Abstract Simulator for Species Concentrations in Channel-Based Microfluidic Devices. 3764-3775 - Zixu Li, Wang Wang, Manni Li, Jiayu Yang, Zijian Huang, Xin Zhong, Yinyin Lin, Chengchen Wang, Xiankui Xiong:
GPOS: A General and Precise Offloading Strategy for High Generality of DNN Acceleration by OCP and NDP Co-Optimizing. 3776-3789 - Simon Toni Hofmann, Marcel Walter, Robert Wille:
Efficient and Scalable Post-Layout Optimization for Field-Coupled Nanotechnologies. 3790-3803 - Jianhua Gao, Zhi Zhou, Xingze Huang, Juan Wang, Yizhuo Wang, Weixing Ji:
PTPS: Precision-Aware Task Partitioning and Scheduling for SpMV on CPU-FPGA Heterogeneous Platforms. 3804-3815 - Haishuang Fan, Rui Meng, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine. 3816-3829 - Liwei Ni, Rui Wang, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu, Guojie Luo, Zhufei Chu, Weikang Qian, Xiaoyan Yang, Biwei Xie, Xingquan Li, Huawei Li:
OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis. 3830-3843 - Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda, Josse Van Delm, Arne Symons, Luca Benini, Marian Verhelst, Daniele Jahier Pagliari, Alessio Burrello:
MATCH: Model-Aware TVM-Based Compilation for Heterogeneous Edge Devices. 3844-3857 - Abhik Kumar Khan, Sudip Roy, Bhargab B. Bhattacharya, Sukanta Bhattacharjee:
Efficient Sample Preparation With Fully Programmable Valve Arrays. 3858-3867 - Alexandra Küster, Rainer Dorsch, Christian Haubelt:
Toward Fast Heterogeneous Virtual Prototypes: Increasing the Solver Efficiency in SystemC AMS. 3868-3881 - Rameez Raja Shaik, Kumar Prasannajit Pradhan:
Evaluation of FONOS FDSOI FET for Synapse-Inspired Artificial Neural Network. 3882-3889 - Milind Kumar, Reetwik Bhadra, Amitesh Kumar:
Ultralow Power Zirconium Electrolyte-Based Synaptic Device for Neuromorphic Computing. 3890-3895 - Peng Cao, Yusen Qin, Guoqing He, Wenjie Ding, Xu Cheng, Zhanhua Zhang, Yuyang Ye:
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning. 3896-3909 - Ruisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar:
ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection. 3910-3923 - Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
An Efficient Placement Speedup Technique Based on Graph Signal Processing. 3924-3937 - Qianxi Chen, Yujiao Deng, Qiang Wu, Zhixiong Di:
An r-DFA-Based Layout Pattern Match Method Supporting Fuzzy Matching. 3938-3947 - Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Jian Chen, Zhixue He, Xingquan Li:
iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree. 3948-3961 - Pengwei Jin, Zhe Fan, Yongwei Zhao, Zidong Du, Hongrui Guo, Ziyuan Nan, Yifan Hao, Chongxiao Li, Tianyun Ma, Zhenxing Zhang, Xiaqing Li, Wei Li, Xing Hu, Qi Guo, Zhiwei Xu, Tianshi Chen:
SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity. 3962-3975 - Xiaohang Wang, Miao Xu, Amit Kumar Singh, Yingtao Jiang, Mei Yang:
On Optimizing Inter- and Intra-Chiplet Interconnection Topologies for Robust Multi-Chiplet Systems. 3976-3989 - Hashan Roshantha Mendis, Chih-Hsuan Yen, Chih-Kai Kang, Pi-Cheng Hsiu:
Intermittent-Friendly Neural Architecture Search: Demystifying Accuracy and Overhead Tradeoffs. 3990-4003 - Yipei Yan, Deyun Lyu, Zhenya Zhang, Paolo Arcaini, Jianjun Zhao:
Automated Generation of Benchmarks for Falsification of STL Specifications. 4004-4017 - Jindong Tu, Yapeng Li, Pengjia Li, Peng Xu, Qianru Zhang, Sanping Wan, Yongsheng Sun, Bei Yu, Tinghuan Chen:
SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits. 4018-4031 - Yibo Dong, Yu Chen, Jianwen Li, Geguang Pu, Ofer Strichman:
Revisiting Assumptions Ordering in CAR-Based Model Checking. 4032-4037 - Yang Wang, Hanlong Chen, Wang Lin, Zuohua Ding:
Formal Synthesis of Neural Barrier Certificates for Dynamical Systems via DC Programming. 4038-4042 - Veeti Lahtinen, Santeri Porrasmaa, Altti Heikkinen, Miikka Tenhunen, Jussi Ryynänen, Marko Kosunen:
Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters. 4043-4047 - Guangze Hong, An Wang, Congming Wei, Yaoling Ding, Shaofei Sun, Jingqi Zhang, Liehuang Zhu:
Make It Easy! Timing Leakage Analysis on Cryptographic Chips Based on Horizontal Leakage. 4048-4052 - Marcelo Danigno, Mateus Fogaça, Rafael B. Schvittz, Paulo F. Butzen:
Placement Refinement Strategies for Security Closure. 4053-4058
Volume 44, Number 11, November 2025
- Yixi Tang, Wenjie Feng, Xinyu Zhou, Weiwei Wang, Quan Xue, Wenquan Che:
Broadband Symmetric Doherty Power Amplifier With Enhanced Back-Off Range Using Multiparameters Optimization Method. 4060-4072 - Kihwan Kim, Xuan Truong Nguyen, Dongsuk Jeon, Hyuk-Jae Lee:
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration. 4073-4085 - Jun Mai, Kun Cao, Tongquan Wei:
Personalized Federated Learning With State-Adaptive IoT Device Scheduling in Mobile-Edge Computing. 4086-4099 - Jiliang Zhang, Zhenyu Wang, Lin Ding:
DA PUF for IoT Security with 0.02% BER at 0.96 to 1.44 V and -40 °C to 125 °C. 4100-4112 - Pantha Protim Sarker, Upoma Das, Mohammad Bin Monjil, Jingbo Zhou, Farimah Farahmandi, Mark Tehranipoor:
GEM-Water: Generation of EM-Based Watermark With Hidden FSM for SoC IPs to Combat Piracy. 4113-4126 - Zihan Zou, Xinming Yan, Chen Zhang, Shikuang Chen, Guang Yang, Han Yan, Hao Cai, Bo Liu:
PF²A-ViT: Parameter-Free and Feature-Aware Dynamic Token Pruning Accelerator With Complementary Quantization-Encoding for Vision Transformer. 4127-4140 - Teng Luo, Tengfei Xia, Jiayuan Chen, Zhihua Fan, Wenming Li, Yudong Mu, Xuejun An, Xiaochun Ye, Dongrui Fan:
A RISC-V Extended Infrastructure for CNNs Through Pipelined Computing and Data Dependence Optimization. 4141-4154 - Morteza Adelkhani, Ali Suvizi, Farzaneh Arzaghi, Sara Zamani, Mohammad Salehi, Muhammad Shafique:
LPCR: Information-Theory-Based Low-Power Code Reordering for Serial Links in Network-on-Chip. 4155-4166 - Jinhong Mo, Xiongfei Zhai, Min Yu, Yi Fang, Guojun Han:
SC-GC-LDPC for nand Flash Memory: Construction and Decoding. 4167-4180 - Yongkun Wu, Xiaomeng Wang, Jia Chen, Zhenhua Zhu, Jingyu He, Pingcheng Dong, Yonghao Tan, Xin Zhao, Liang Chang, Yu Wang, Fengbin Tu, Chi-Ying Tsui, Kwang-Ting Cheng:
Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimization. 4181-4194 - Dong Huang, Dan Feng, Qiankun Liu, Bo Ding, Wei Zhao, Xueliang Wei, Wei Tong, Shu Li, Feng Zhu, Maojun Yuan, Jie Yang:
An Efficient Independent Read Scheme for Contemporary QLC SSDs. 4195-4208 - M. B. Rakesh, Pabitra Das, Sai Pranav K. R, Amit Acharyya:
GRIPT: Graph Attention-Assisted Inductive Methodology for Fast and Accurate Average Power Estimation From RTL Simulation Skipping Gate-Level Simulation. 4209-4221 - Shan Cao, Meiling Yang, Yintao Liu, Yu Li, Beining Zhao, Xinyu Chen, Zhiyuan Jiang:
A Heterogeneous CNN Compilation Framework for RISC-V CPU and NPU Integration Based on ONNX-MLIR. 4222-4235 - Renzo Andri, Enrico Reggiani, Lukas Cavigelli:
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation. 4236-4248 - Jiayao Ling, Gang Li, Xiaolong Lin, Cheng Gu, Xing Li, Jian Cheng, Xiaoyao Liang:
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations. 4249-4262 - Su Zheng, Wenqian Zhao, Shuyuan Sun, Fan Yang, Bei Yu, Martin D. F. Wong:
Streamlining Computational Lithography With Efficient Pattern Database. 4263-4275 - Jun Li, Wei Wang, Wu-Jun Li:
Hardware Computation Graph for DNN Accelerator Design Automation Without Inter-PU Templates. 4276-4289 - Liu He, Yujin Wang, Zongle Huang, Shupei Fan, Chen Tang, Shuyuan Zhang, Luchang Lei, Huazhong Yang, Yongpan Liu, Hongyang Jia:
SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution. 4290-4303 - Ziwei Yu, Shuai Yan, Yaxing Zhou, Xiaoyu Xu, Zhuoxiang Ren:
AIL-DNN: Modeling of IC Interconnect Parasitic Capacitances Based on Adaptive Incremental Learning. 4304-4312 - Jingrou Wu, Chuang Hu, Jin Zhang, Dan Wang, Jing Jiang:
Gemini+: Enhancing Real-Time Video Analytics With Dual-Image FPGAs. 4313-4326 - Jiawei Xu, Yi Zheng, Dimitrios Stathis, Ruijia Wang, Ruisi Shen, Lirong Zheng, Zhuo Zou, Ahmed Hemani:
MemMIMO: A Simulation Framework for Memristor-Based Massive MIMO Acceleration. 4327-4340 - Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng:
Adaptive ILT via Multi-Level Lithography Simulation. 4341-4354 - Naoki Nonaka, Masaki Kuramochi, Yukihide Kohira, Rina Azuma, Tomomi Matsui, Atsushi Takahashi, Chikaaki Kodama:
Fast Mask Optimization Under Process Variation Using Guided Local Search on Quadratic Programming. 4355-4366 - Hao Gu, Jian Gu, Keyu Peng, Jianli Chen, Jun Yang, Ziran Zhu:
Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints. 4381-4394 - Ahmed Mamdouh, Haoran Geng, Michael T. Niemier, Xiaobo Sharon Hu, Dayane Reis:
Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM. 4395-4404 - Zhihao Xu, Shikai Guo, Guilin Zhao, Peiyu Zou, Xiaochen Li, He Jiang:
A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers. 4405-4418 - Shao-Chun Hung, Arjun Chaudhuri, Krishnendu Chakrabarty:
Reinforcement-Learning-Based Test Point Insertion for Power-Safe Testing in Monolithic 3-D ICs. 4419-4432 - Yupeng Hu, Yapeng Li, Jindong Tu, Tinghuan Chen, Qi Sun, Cheng Zhuo:
Hierarchical Behavioral Learning-Based Dynamic Electromigration Analysis for Signal Networks. 4433-4437 - Sungju Kim, Hyungcheol Shin:
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String. 4438-4442 - Haoyang Xu, Xing Huang, Zhen Zhuang, Zhiwen Yu, Bin Guo, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong:
Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging. 4367-4380
Volume 44, Number 12, December 2025
- Hao Nan Huang, Hong Zhao, Jing Liu:
MOMC3D: A Novel Multiobjective Optimization Method With Mixed-Coding Strategy for Standard Cells in Chip 3-D Placement. 4444-4457 - Kun Wang, Jing Zhang, Jie Liu, Feiya Yan, Changsheng Chen, Jing Yang:
Multiobjective Coverage Optimization for 3-D Heterogeneous Wireless Sensor Networks. 4458-4471 - Yujie Zhang, Huiying Lan, Ehsan Aghapour, Zhiyuan Ning, Peng Zan, Weidong Shao, Anuj Pathania, Tulika Mitra:
Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs. 4472-4485 - Yong Peng, Li Peng, Shaocong Sun, Lujia Yin, Qiao Li, Jie Zhang:
FlexHMB: A Flexible HMB Design Toward Bufferless Mobile Flash. 4486-4499 - Shih-Han Chang, Tung Lin, Chien-Nan Jimmy Liu:
Mitigating Computation Errors of In-RRAM Computing Through Network Retraining With IR-Drop and Data Allocation Effects. 4500-4509 - Jiahao Sun, Yijian Zhang, Yuzhuo Liu, Fangxin Liu, Li Jiang, Rui Yang:
A Sub- 10 μs In-Memory-Search Collision Detection Accelerator Based on RRAM-TCAMs. 4510-4523 - Aolin You, Erxiang Ren, Daniel Zheng Fang, Cheng Qu, Li Luo, Hongwei Guo, Qi Wei, Xinjun Liu, Fei Qiao:
Denoise on Sensor: A Near-Sensor Compute-in-Memory Macro for Visual Perception Denoising via Concatnation-Eliminating. 4524-4537 - Zhelong Wang, Wei W. Xing, Ning Xu, Yuanqing Cheng:
Carbon Nanotube Interconnect Optimizations With Bayesian Neural Network and Bayesian Optimization. 4538-4549 - Priyanjana Pal, Brojogopal Sapui, Dennis D. Weller, Mehdi B. Tahoori:
Efficient Analog Error Correction for Printed Unary-Encoded Computing. 4550-4563 - Fei Yu, Shaoqi He, Wei Yao, Shuo Cai, Quan Xu:
Bursting Firings in Memristive Hopfield Neural Network With Image Encryption and Hardware Implementation. 4564-4576 - Liang Yan, Xiaoyang Lu, Sheng Xu, Xiaoming Chen, Xingqi Zou, Yinhe Han, Xian-He Sun:
ProMiner: Enhancing Locality, Parallelism, and Offloading for Graph Mining on Processing-in-Memory Systems. 4577-4590 - Shams-Ul-Haq, Erfan Abbasian, Maedeh Orouji, Sajad A. Loan, Tabassum Khurshid:
Synthesis of a CNTFET-Based Ternary Full Adder Using a Carry-Less Ternary Half Adder. 4591-4600 - Kezhen Zhang, Riling Li, Mingsheng Ying:
A Divide-And-Conquer Pebbling Strategy for Oracle Synthesis in Quantum Computing. 4601-4614 - Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, Bei Yu:
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. 4615-4628 - Songyu Sun, Xiao Dong, Yanliang Sha, Qi Sun, Quan Chen, Zhou Jin, Cheng Zhuo:
LiTformer: Efficient Signal Integrity Analysis for High-Speed Link Transmitters Using Non-Autoregressive Transformer. 4629-4642 - Ximing Liu, Yongwei Zhao, Mo Zou, Yang Liu, Yifan Hao, Xiaqing Li, Rui Zhang, Yuanbo Wen, Xing Hu, Zidong Du, Qi Guo, Tianshi Chen:
VariPar: Variation-Aware Workload Partitioning in Chiplet-Based DNN Accelerators. 4643-4656 - Jing He, Qianqi Zhao, Xuhong Qiang, Qi Wang, Qianhui Li, Zongliang Huo:
Hybrid Neural Network Model for Raw Bit Error Rate Prediction of 3-D TLC NAND Flash Memory. 4657-4666 - Yaroslav Popryho, Debjit Pal, Inna Partin-Vaisband:
NetVGE: Netwise Hardware Trojan Detection at RTL Using Variable Dependency and Knowledge Graph Embedding. 4667-4678 - Zixiao Wang, Wenqian Zhao, Yunheng Shen, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu:
DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion. 4679-4690 - Juhwan Park, Huijun Kim, Hanggyo Jung, Changho Ra, Jongwook Jeon:
Impact of Interconnect on Ferroelectric FinFET-Based Logic-in-Memory Circuits at 3-nm Technology Node. 4691-4700 - Quanli Deng, Chunhua Wang, Yichuang Sun, Cong Xu, Hairong Lin, Zekun Deng:
Memristor-Based Brain Emotional Learning Neural Network With Attention Mechanism and Its Application. 4701-4713 - Tianshu Hou, Farid N. Najm, Ngai Wong, Hai-Bao Chen:
Novel Partitioning-Based Approach for Electromigration Assessment With Neural Networks. 4714-4727 - Linmeng Xu, Yu Chang, Liyu Liu, Kai Qiao, Zefang Xu, Jieying Wang, Chang Su, Mengyan Fang, Fei Yin, Xing Wang:
A New Verilog-A SPAD Circuit Model Integrating Crosstalk for Large-Scale Array. 4728-4739 - Xiangyu Ran, Chuxiong Lin, Yuxuan Qin, Jieyu Li, Ling Yang, Weifeng He:
An Ultraspeed Middle Voltage and Timing Analyzer With Near-SPICE Accuracy for Charge-Recycling Buses. 4740-4751 - Yuhang Li, Mei Wen, Junzhong Shen, Zhaoyun Chen, Yang Shi, Tianyu Wang, Zili Shao:
MAP-SIM: A DNN-Specific Mapping Optimization Framework for Shared-Memory CPU-Systolic Array Architectures. 4752-4764 - Chuandong Chen, Disi Lin, Qinghai Liu, Huan He, Zhifeng Lin, Genggeng Liu, Jianli Chen, Yao-Wen Chang:
A Matching-Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints. 4765-4778 - Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu:
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning. 4779-4792 - Jingchen Zhu, Chenhao Xue, Yiqi Chen, Zhao Wang, Chen Zhang, Yu Shen, Yifan Chen, Zekang Cheng, Yu Jiang, Tianqi Wang, Yibo Lin, Wei Hu, Bin Cui, Runsheng Wang, Yun Liang, Guangyu Sun:
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models. 4793-4806 - Andrea Calabrese, Stefano Quer, Giovanni Squillero:
Flying-Probe Testing: A Trajectory Planner and a Benchmark Suite. 4807-4817 - Irith Pomeranz:
Hazard-Based Functionally Possible Transition Faults With High Functional Switching Activities. 4818-4827 - Rui Li, Lin Li, Heng Yu, Masahiro Fujita, Weixiong Jiang, Yajun Ha:
RefSCAT-2.0: Formal Verification of Large-Scale Optimized Multipliers via Quantum-Inspired Ant Colony Optimization-Based Reference Generation. 4828-4841
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