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ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 1
Volume 1, Number 1, March 2008
- Duncan A. Buell
, Wayne Luk:
Introduction. 1:1-1:2 - André DeHon, Mike Hutton:
Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. 2:1-2:3 - Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa:
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. 3:1-3:31 - Satish Sivaswamy, Kia Bazargan:
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. 4:1-4:35 - Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow:
A Desktop Computer with a Reconfigurable Pentium®. 5:1-5:15 - Wenyi Feng, Sinan Kaptanoglu:
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy. 6:1-6:28 - Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk:
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. 7:1-7:25
Volume 1, Number 2, June 2008
- Tim Güneysu, Christof Paar, Jan Pelzl:
Special-Purpose Hardware for Solving the Elliptic Curve Discrete Logarithm Problem. 8:1-8:21 - Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Brandon Harris, Roger D. Chamberlain:
Mercury BLASTP: Accelerating Protein Sequence Alignment. 9:1-9:44 - N. Pete Sedcole, Peter Y. K. Cheung:
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. 10:1-10:28 - Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs. 11:1-11:21 - David B. Thomas, Wayne Luk:
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. 12:1-12:29
Volume 1, Number 3, September 2008
- Julien Lamoureux, Steven J. E. Wilton:
On the trade-off between power and flexibility of FPGA clock networks. 13:1-13:33 - David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning:
An open-source HyperTransport core. 14:1-14:21 - John Sachs Beeckler, Warren J. Gross:
Particle graphics on reconfigurable hardware. 15:1-15:27 - David Grant, Guy G. Lemieux:
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. 16:1-16:24 - Pao-Ann Hsiung, Chao-Sheng Lin, Chih-Feng Liao:
Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures. 17:1-17:30
Volume 1, Number 4, January 2009
- Scott Y. L. Chin, Steven J. E. Wilton:
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. 18:1-18:20 - Ningyi Xu, Xiongfei Cai, Rui Gao, Lei Zhang, Feng-Hsiung Hsu:
FPGA Acceleration of RankBoost in Web Search Engines. 19:1-19:19 - Cameron D. Patterson, Steven W. Ellingson, Brian S. Martin, K. Deshpande, John H. Simonetti, Michael Kavic, Sean E. Cutchin:
Searching for Transient Pulses with the ETA Radio Telescope. 20:1-20:19 - Esam El-Araby, Iván González, Tarek A. El-Ghazawi:
Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing. 21:1-21:23 - Brian Holland, Karthik Nagarajan, Alan D. George:
RAT: RC Amenability Test for Rapid Performance Prediction. 22:1-22:31 - S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot:
Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic. 23:1-23:21 - Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung:
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. 24:1-24:28
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