default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI Design, Volume 2010
Volume 2010, 2010
- Jun Zhao, Yong-Bin Kim:
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops. 946710:1-946710:11 - Kamakshy Selvajyothi
, P. A. Janakiraman:
FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters. 512312:1-512312:14 - Chandradevi Ulaganathan, Neena Nambiar, Kimberly Cornett, Robert L. Greenwell, Jeremy A. Yager, Benjamin S. Prothro, Kevin Tham, Suheng Chen, Richard S. Broughton, Guoyuan Fu, Benjamin J. Blalock, Charles L. Britton Jr., M. Nance Ericson, H. Alan Mantooth, Mohammad M. Mojarradi, Richard W. Berger, John D. Cressler:
A SiGe BiCMOS Instrumentation Channel for Extreme Environment Applications. 156829:1-156829:12 - Yao Xu, Ashok Kumar Srivastava, Ashwani K. Sharma:
Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance. 864165:1-864165:8 - Jianchao Lu, Baris Taskin:
Post-CTS Delay Insertion. 451809:1-451809:9 - Saumil G. Merchant, Gregory D. Peterson:
Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments. 251210:1-251210:25 - Bo Marr, Jason George, Brian P. Degnan, David V. Anderson, Paul E. Hasler:
Error Immune Logic for Low-Power Probabilistic Computing. 460312:1-460312:9 - Akila Gothandaraman, Gregory D. Peterson, G. Lee Warren, Robert J. Hinde, Robert J. Harrison:
A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs. 946486:1-946486:8 - JunKyu Lee, Gregory D. Peterson, Robert J. Harrison, Robert J. Hinde:
Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators. 930821:1-930821:11 - Kumar Yelamarthi, Chien-In Henry Chen:
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations. 230783:1-230783:13 - Reza Hashemian:
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs. 297083:1-297083:12 - Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. 706548:1-706548:8 - P. Sumathi, P. A. Janakiraman:
FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme. 213043:1-213043:11 - Kofi M. Odame, Paul E. Hasler:
Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping. 687498:1-687498:8 - Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee:
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey. 670476:1-670476:9 - Boppana Lakshmi, A. S. Dhar:
CORDIC Architectures: A Survey. 794891:1-794891:19 - Tooraj Nikoubin, Poona Bahrebar, Sara Pouri, Keivan Navi, Vaez Iravani:
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits. 264390:1-264390:17 - Parag K. Lala, Adam Mathews, James Patrick Parkerson:
An Approach for Implementing State Machines with Online Testability. 639747:1-639747:7 - Gregory D. Peterson, Ethan D. Farquhar, Benjamin J. Blalock:
Selected Papers from the Midwest Symposium on Circuits and Systems. 538454:1-538454:2 - Sergio Saponara, Tommaso Baldetti, Luca Fanucci:
A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation. 169079:1-169079:7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-02 01:14 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
