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The Journal of VLSI Signal Processing, Volume 44
Volume 44, Numbers 1-2, August 2006
- S. C. Chan, Xuemei Xie

:
Biorthogonal Recombination Nonuniform Cosine-Modulated Filter Banks and their Multiplier-Less Realizations. 5-23 - Lijun Gao, Keshab K. Parhi

:
Models for Architectural Power and Power Grid Noise Analysis on Data Bus. 25-46 - Sangjin Hong, Shu-Shin Chin, Petar M. Djuric

, Miodrag Bolic:
Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters. 47-62 - Ioannis Gasteratos, Antonios Gasteratos, Ioannis Andreadis:

An Algorithm for Adaptive Mean Filtering and Its Hardware Implementation. 63-78 - Tero Kangas, Timo D. Hämäläinen, Kimmo Kuusilinna:

Scalable Architecture for SoC Video Encoders. 79-95 - Kai Man Tsui, Shing-Chow Chan:

Error Analysis and Efficient Realization of the Multiplier-Less FFT-Like Transformation (ML-FFT) and Related Sinusoidal Transformations. 97-115 - Yung-Chi Chang, Chih-Wei Hsu, Wei-Min Chao, Liang-Gee Chen:

Interactive Content-aware Video Streaming System with Fine Granularity Scalability. 117-134 - Salvatore Carta, Danilo Pani

, Luigi Raffo
:
Reconfigurable Coprocessor for Multimedia Application Domain. 135-152 - Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis

, Konstantinos Tatas
, Antonios Argyriou
, Dimitrios Soudris
, Antonios Thanailakis:
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. 153-171 - Vince D. Calhoun

, Tülay Adali:
Complex Infomax: Convergence and Approximation of Infomax with Complex Nonlinearities. 173-190 - Michael Hosemann, Gerhard P. Fettweis:

On enhancing SIMD-controlled DSPs for performing recursive filtering. 191
Volume 44, Number 3, September 2006
- Yuanbin Guo, Joseph R. Cavallaro

:
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems. 195-217 - Zhan Guo, Peter Nilsson:

A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection. 219-230 - Junhyung Um, Taewhan Kim:

Resource Sharing Combined with Layout Effects in High-Level Synthesis. 231-243 - Subash Chandar G., Mahesh Mehendale, R. Govindarajan:

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. 245-267 - Young-Jun Kim, Taewhan Kim:

A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. 269-283

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