default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDThe Journal of Signal Processing Systems, Volume 50
Volume 50, Number 1, January 2008
- Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen
:
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder. 1-17 - Yu Li, Yun He, Shunliang Mei:
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC. 19-32 - Jonah Probell:
Architecture Considerations for Multi-Format Programmable Video Processors. 33-39 - Yanmei Qu, Yun He, Shunliang Mei:
A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC. 41-51 - Sung Dae Kim, Myung Hoon Sunwoo:
ASIP Approach for Implementation of H.264/AVC. 53-67 - Tsu-Ming Liu, Chen-Yi Lee:
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. 69-80 - Lingfeng Li, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto:
A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC. 81-95
Volume 50, Number 2, February 2008
- Shuvra S. Bhattacharyya, Jarmo Takala, Georgi Gaydadjiev:
Introduction to the Special Issue on Embedded Computing Systems for DSP. 97-98 - Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas:
Calibration of Abstract Performance Models for System-Level Design Space Exploration. 99-114 - Ye Wen, Selim Gurun, Navraj Chohan, Richard Wolski, Chandra Krintz:
Accurate and Scalable Simulation of Network of Heterogeneous Sensor Devices. 115-136 - Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal:
Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications. 137-161 - Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya:
Memory-constrained Block Processing for DSP Software Optimization. 163-177 - Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis:
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path. 179-200 - Mladen Berekovic, Tim Niggemeier:
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. 201-229 - Eero Aho, Jarno Vanne, Timo D. Hämäläinen:
Configurable Data Memory for Multimedia Processing. 231-249 - Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl:
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. 251-261
Volume 50, Number 3, March 2008
- Li Teng, Laiwan Chan:
Discovering Biclusters by Iteratively Sorting with Weighted Correlation Coefficient in Gene Expression Data. 267-280 - Benson S. Y. Lam, Alan Wee-Chung Liew, David K. Smith, Hong Yan:
A Regularized Clustering Algorithm Based on Calculus of Variations. 281-292 - Zhaohui Gan, Tommy W. S. Chow, Di Huang:
Effective Gene Selection Method Using Bayesian Discriminant Based Criterion and Genetic Algorithms. 293-304 - Yu-Ping Wang, Maheswar Gunampally, Jie Chen, Douglas Bittel, Merlin G. Butler, Wei-Wen Cai:
A Comparison of Fuzzy Clustering Approaches for Quantification of Microarray Gene Expression. 305-320 - Robin Kramer, Dong Xu:
Projecting Gene Expression Trajectories through Inducing Differential Equations from Microarray Time Series Experiments. 321-329 - Sujimarn Suwannaroj, Mahesan Niranjan:
Enhancing Automatic Construction of Gene Subnetworks by Integrating Multiple Sources of Information. 331-340
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 01:27 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
