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ORCIDBibTeX records: Fady Abouzeid
@inproceedings{DBLP:conf/dft/ThometPDBARGR21,
author = {S{\'{e}}bastien Thomet and
Serge De Paoli and
Jean{-}Marc Daveau and
Val{\'{e}}rie Bertin and
Fady Abouzeid and
Philippe Roche and
Fakhreddine Ghaffari and
Olivier Romain},
editor = {Luigi Dilillo and
Luca Cassano and
Athanasios Papadimitriou},
title = {{FIRECAP:} Fail-Reason Capturing hardware module for a {RISC-V} based
System on a Chip},
booktitle = {36th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2021, Athens, Greece,
October 6-8, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DFT52944.2021.9568317},
doi = {10.1109/DFT52944.2021.9568317},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/ThometPDBARGR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LallementACDRA18,
author = {Guenole Lallement and
Fady Abouzeid and
Martin Cochet and
Jean{-}Marc Daveau and
Philippe Roche and
Jean{-}Luc Autran},
title = {A 2.7 pJ/cycle 16 MHz, 0.7 {\(\mathrm{\mu}\)}W Deep Sleep Power {ARM}
Cortex-M0+ Core SoC in 28 nm {FD-SOI}},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {7},
pages = {2088--2100},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2018.2821167},
doi = {10.1109/JSSC.2018.2821167},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LallementACDRA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LallementAGRA18,
author = {Guenole Lallement and
Fady Abouzeid and
Thierry Di Gilio and
Philippe Roche and
Jean{-}Luc Autran},
title = {A 140 nW, 32.768 kHz, 1.9 ppm/{\textdegree}C Leakage-Based Digitally
Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm
{FD-SOI}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {197--200},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579291},
doi = {10.1109/ASSCC.2018.8579291},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/LallementAGRA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DebizetLARA18,
author = {Yvan Debizet and
Gu{\'{e}}nol{\'{e}} Lallement and
Fady Abouzeid and
Philippe Roche and
Jean{-}Luc Autran},
title = {Q-Learning-based Adaptive Power Management for IoT System-on-Chips
with Embedded Power States},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351385},
doi = {10.1109/ISCAS.2018.8351385},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DebizetLARA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/CochetCLARA17,
author = {Martin Cochet and
Sylvain Clerc and
Guenole Lallement and
Fady Abouzeid and
Philippe Roche and
Jean{-}Luc Autran},
title = {A 0.40pJ/cycle 981 {\(\mu\)}m\({}^{\mbox{2}}\) voltage scalable digital
frequency generator for SoC clocking},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
Korea (South), November 6-8, 2017},
pages = {69--72},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASSCC.2017.8240218},
doi = {10.1109/ASSCC.2017.8240218},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/CochetCLARA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/LallementACDRA17,
author = {Guenole Lallement and
Fady Abouzeid and
Martin Cochet and
Jean{-}Marc Daveau and
Philippe Roche and
Jean{-}Luc Autran},
title = {A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off {ARM} Cortex-M0+ core
in 28nm {FD-SOI}},
booktitle = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
Leuven, Belgium, September 11-14, 2017},
pages = {153--162},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ESSCIRC.2017.8094550},
doi = {10.1109/ESSCIRC.2017.8094550},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/LallementACDRA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/RossiPLGGTCBPBC16,
author = {Davide Rossi and
Antonio Pullini and
Igor Loi and
Michael Gautschi and
Frank Kagan G{\"{u}}rkaynak and
Adam Teman and
Jeremy Constantin and
Andreas Burg and
Ivan Miro Panades and
Edith Beign{\'{e}} and
Fabien Clermidy and
Fady Abouzeid and
Philippe Flatresse and
Luca Benini},
title = {193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator
for energy efficient parallel and sequential digital processing},
booktitle = {2016 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
XIX, Yokohama, Japan, April 20-22, 2016},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CoolChips.2016.7503670},
doi = {10.1109/COOLCHIPS.2016.7503670},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/RossiPLGGTCBPBC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AbouzeidBCDGNSR16,
author = {Fady Abouzeid and
Christophe Bernicot and
Sylvain Clerc and
Jean{-}Marc Daveau and
Gilles Gasiot and
Daniel Noblet and
Dimitri Soussan and
Philippe Roche},
title = {30{\%} static power improvement on {ARM} Cortex\({}^{\mbox{{\textregistered}}}\)-A53
using static biasing-anticipation},
booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
pages = {37--40},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ESSCIRC.2016.7598237},
doi = {10.1109/ESSCIRC.2016.7598237},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/AbouzeidBCDGNSR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BeigneVPWFABBBBCGGCNTT15,
author = {Edith Beign{\'{e}} and
Alexandre Valentian and
Ivan Miro Panades and
Robin Wilson and
Philippe Flatresse and
Fady Abouzeid and
Thomas Benoist and
Christian Bernard and
Sebastien Bernard and
Olivier Billoint and
Sylvain Clerc and
Bastien Giraud and
Anuj Grover and
Julien Le Coz and
Jean{-}Philippe Noel and
Olivier Thomas and
Yvain Thonnart},
title = {A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits {VLIW} {DSP} Embedding
{F} {MAX} Tracking},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {125--136},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2369503},
doi = {10.1109/JSSC.2014.2369503},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BeigneVPWFABBBBCGGCNTT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AbouzeidCBCDCGS15,
author = {Fady Abouzeid and
Sylvain Clerc and
Cyril Bottoni and
Benjamin Coeffic and
Jean{-}Marc Daveau and
Damien Croain and
Gilles Gasiot and
Dimitri Soussan and
Philippe Roche},
editor = {Wolfgang Pribyl and
Franz Dielacher and
Gernot Hueber},
title = {28nm {FD-SOI} technology and design platform for sub-10pJ/cycle and
SER-immune 32bits processors},
booktitle = {{ESSCIRC} Conference 2015 - 41\({}^{\mbox{st}}\) European Solid-State
Circuits Conference, Graz, Austria, September 14-18, 2015},
pages = {108--111},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ESSCIRC.2015.7313840},
doi = {10.1109/ESSCIRC.2015.7313840},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/AbouzeidCBCDCGS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/BottoniCDGACNR15,
author = {Cyril Bottoni and
Benjamin Coeffic and
Jean{-}Marc Daveau and
Gilles Gasiot and
Fady Abouzeid and
Sylvain Clerc and
Lirida A. B. Naviner and
Philippe Roche},
title = {Frequency and voltage effects on {SER} on a 65nm Sparc-V8 microprocessor
under radiation test},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2015, Monterey,
CA, USA, April 19-23, 2015},
pages = {12},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/IRPS.2015.7112830},
doi = {10.1109/IRPS.2015.7112830},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/irps/BottoniCDGACNR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ClercAPDBCGMWRN15,
author = {Sylvain Clerc and
Fady Abouzeid and
Darayus Adil Patel and
Jean{-}Marc Daveau and
Cyril Bottoni and
Lorenzo Ciampolini and
Fabien Giner and
David Meyer and
Robin Wilson and
Philippe Roche and
Sylvie Naudet and
Arnaud Virazel and
Alberto Bosio and
Patrick Girard},
title = {Design and performance parameters of an ultra-low voltage, single
supply 32bit processor implemented in 28nm {FDSOI} technology},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {366--370},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085453},
doi = {10.1109/ISQED.2015.7085453},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ClercAPDBCGMWRN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ClercSACDBBVZCS15,
author = {Sylvain Clerc and
Mehdi Saligane and
Fady Abouzeid and
Martin Cochet and
Jean{-}Marc Daveau and
Cyril Bottoni and
David Bol and
Julien De Vos and
Dominique Zamora and
Benjamin Coeffic and
Dimitri Soussan and
Damien Croain and
Mehdi Naceur and
Pierre Schamberger and
Philippe Roche and
Dennis Sylvester},
title = {8.4 {A} 0.33V/-40{\textdegree}C process/temperature closed-loop compensation
SoC embedding all-digital clock multiplier and {DC-DC} converter exploiting
{FDSOI} 28nm back-gate biasing},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062970},
doi = {10.1109/ISSCC.2015.7062970},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ClercSACDBBVZCS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AbouzeidBAFCCGWR14,
author = {Fady Abouzeid and
Audrey Bienfait and
Kaya Can Akyel and
Anis Feki and
Sylvain Clerc and
Lorenzo Ciampolini and
Fabien Giner and
Robin Wilson and
Philippe Roche},
title = {Scalable 0.35 {V} to 1.2 {V} {SRAM} Bitcell Design From 65 nm {CMOS}
to 28 nm {FDSOI}},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {7},
pages = {1499--1505},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2014.2316219},
doi = {10.1109/JSSC.2014.2316219},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AbouzeidBAFCCGWR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WilsonBFVABBBBC14,
author = {Robin Wilson and
Edith Beign{\'{e}} and
Philippe Flatresse and
Alexandre Valentian and
Fady Abouzeid and
Thomas Benoist and
Christian Bernard and
Sebastien Bernard and
Olivier Billoint and
Sylvain Clerc and
Bastien Giraud and
Anuj Grover and
Julien Le Coz and
Ivan Miro Panades and
Jean{-}Philippe No{\"{e}}l and
Bertrand Pelloux{-}Prayer and
Philippe Roche and
Olivier Thomas and
Yvain Thonnart and
David Turgis and
Fabien Clermidy and
Philippe Magarshack},
title = {27.1 {A} 460MHz at 397mV, 2.6GHz at 1.3V, 32b {VLIW} DSP, embedding
{FMAX} tracking},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {452--453},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757509},
doi = {10.1109/ISSCC.2014.6757509},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WilsonBFVABBBBC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BeigneVGTBTBMBMFNAPGCRCEW13,
author = {Edith Beign{\'{e}} and
Alexandre Valentian and
Bastien Giraud and
Olivier Thomas and
Thomas Benoist and
Yvain Thonnart and
Serge Bernard and
Guillaume Moritz and
Olivier Billoint and
Y. Maneglia and
Philippe Flatresse and
Jean{-}Philippe Noel and
Fady Abouzeid and
Bertrand Pelloux{-}Prayer and
Anuj Grover and
Sylvain Clerc and
Philippe Roche and
Julien Le Coz and
Sylvain Engels and
Robin Wilson},
editor = {Enrico Macii},
title = {Ultra-wide voltage range designs in fully-depleted silicon-on-insulator
FETs},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {613--618},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.135},
doi = {10.7873/DATE.2013.135},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BeigneVGTBTBMBMFNAPGCRCEW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AbouzeidBACCR13,
author = {Fady Abouzeid and
Audrey Bienfait and
Kaya Can Akyel and
Sylvain Clerc and
Lorenzo Ciampolini and
Philippe Roche},
title = {Scalable 0.35V to 1.2V {SRAM} bitcell design from 65nm {CMOS} to 28nm
{FDSOI}},
booktitle = {{ESSCIRC} 2013 - Proceedings of the 39th European Solid-State Circuits
Conference, Bucharest, Romania, September 16-20, 2013},
pages = {205--208},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ESSCIRC.2013.6649108},
doi = {10.1109/ESSCIRC.2013.6649108},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/AbouzeidBACCR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AbouzeidCPAR12,
author = {Fady Abouzeid and
Sylvain Clerc and
Bertrand Pelloux{-}Prayer and
Fabrice Argoud and
Philippe Roche},
title = {28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V,
10MHz/700MHz, 252bits frame error-decoder},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
2012, Bordeaux, France, September 17-21, 2012},
pages = {153--156},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ESSCIRC.2012.6341282},
doi = {10.1109/ESSCIRC.2012.6341282},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/AbouzeidCPAR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/ClercAGGR12,
author = {Sylvain Clerc and
Fady Abouzeid and
Gilles Gasiot and
David Gauthier and
Philippe Roche},
title = {A 65nm {SRAM} achieving 250mV retention and 350mV, 1MHz, 55fJ/bit
access energy, with bit-interleaved radiation Soft Error tolerance},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
2012, Bordeaux, France, September 17-21, 2012},
pages = {313--316},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ESSCIRC.2012.6341317},
doi = {10.1109/ESSCIRC.2012.6341317},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/ClercAGGR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/ClercAGGSR12,
author = {Sylvain Clerc and
Fady Abouzeid and
Gilles Gasiot and
David Gauthier and
Dimitri Soussan and
Philippe Roche},
title = {A 0.32V, 55fJ per bit access energy, {CMOS} 65nm bit-interleaved {SRAM}
with radiation Soft Error tolerance},
booktitle = {{IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2012, Austin, TX, USA, May 30 - June 1, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICICDT.2012.6232860},
doi = {10.1109/ICICDT.2012.6232860},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/ClercAGGSR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/AbouzeidCFRSS11,
author = {Fady Abouzeid and
Sylvain Clerc and
Fabian Firmin and
Marc Renaudin and
Tiempo Sas and
Gilles Sicard},
title = {40nm {CMOS} 0.35V-Optimized Standard Cell Libraries for Ultra-Low
Power Applications},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {35:1--35:17},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970369},
doi = {10.1145/1970353.1970369},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/AbouzeidCFRSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/ClercAAKKR11,
author = {Sylvain Clerc and
Fady Abouzeid and
Fabrice Argoud and
Abhay Kumar and
Rajesh Kumar and
Philippe Roche},
title = {A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using
ultra-low voltage circuit design platform},
booktitle = {18th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2011, Beirut, Lebanon, December 11-14, 2011},
pages = {117--120},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICECS.2011.6122228},
doi = {10.1109/ICECS.2011.6122228},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/ClercAAKKR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/AbouzeidCFRS09,
author = {Fady Abouzeid and
Sylvain Clerc and
Fabian Firmin and
Marc Renaudin and
Gilles Sicard},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {A 45nm {CMOS} 0.35v-optimized standard cell library for ultra-low
power applications},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {225--230},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594288},
doi = {10.1145/1594233.1594288},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/AbouzeidCFRS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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