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ORCIDBibTeX records: Charles Augustine
@article{DBLP:journals/dt/AugustineL23,
author = {Charles Augustine and
Hai Helen Li},
title = {{ISLPED} 2022: An Experience of a Hybrid Conference in the Time of
{COVID-19}},
journal = {{IEEE} Des. Test},
volume = {40},
number = {1},
pages = {105--107},
year = {2023},
url = {https://doi.org/10.1109/MDAT.2022.3208552},
doi = {10.1109/MDAT.2022.3208552},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/AugustineL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/EckertSWAID23,
author = {Charles Eckert and
Arun Subramaniyan and
Xiaowei Wang and
Charles Augustine and
Ravishankar Iyer and
Reetuparna Das},
title = {Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural
Networks},
journal = {{IEEE} Trans. Computers},
volume = {72},
number = {6},
pages = {1539--1553},
year = {2023},
url = {https://doi.org/10.1109/TC.2022.3214151},
doi = {10.1109/TC.2022.3214151},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/EckertSWAID23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/AugustineMLVBMT23,
author = {Charles Augustine and
Pascal Meinerzhagen and
Wootaek Lim and
A. Veerabathini and
M. Bright and
K. Mojjada and
Jim Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop
Monitor Using Coupled Ring Oscillators in Intel 4 {CMOS}},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185254},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185254},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/AugustineMLVBMT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/islped/2022,
editor = {Hai Helen Li and
Charles Augustine and
Ayse Kivilcim Coskun and
Swaroop Ghosh},
title = {{ISLPED} '22: {ACM/IEEE} International Symposium on Low Power Electronics
and Design, Boston, MA, USA, August 1 - 3, 2022},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3531437},
doi = {10.1145/3531437},
isbn = {978-1-4503-9354-6},
timestamp = {Mon, 15 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/2022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/WangGYBBNAID21,
author = {Xiaowei Wang and
Vidushi Goyal and
Jiecao Yu and
Valeria Bertacco and
Andrew Boutros and
Eriko Nurvitadhi and
Charles Augustine and
Ravi R. Iyer and
Reetuparna Das},
title = {Compute-Capable Block RAMs for Efficient Deep Learning Acceleration
on FPGAs},
booktitle = {29th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2021, Orlando, FL, USA, May 9-12, 2021},
pages = {88--96},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FCCM51124.2021.00018},
doi = {10.1109/FCCM51124.2021.00018},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/WangGYBBNAID21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nas/WangANIZD21,
author = {Xiaowei Wang and
Charles Augustine and
Eriko Nurvitadhi and
Ravi R. Iyer and
Li Zhao and
Reetuparna Das},
title = {Cache Compression with Efficient in-SRAM Data Comparison},
booktitle = {{IEEE} International Conference on Networking, Architecture and Storage,
{NAS} 2021, Riverside, CA, USA, October 24-26, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/NAS51552.2021.9605440},
doi = {10.1109/NAS51552.2021.9605440},
timestamp = {Sat, 20 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nas/WangANIZD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AugustineAMORSM21,
author = {Charles Augustine and
A. Afzal and
U. Misgar and
Abdullah A. Owahid and
A. Raman and
K. Subramanian and
Feroze Merchant and
James W. Tschanz and
Muhammad M. Khellah},
title = {All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm
4-Core x86 {IP}},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492376},
doi = {10.23919/VLSICIRCUITS52068.2021.9492376},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AugustineAMORSM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AhmedKALWRTD20,
author = {Khondker Zakir Ahmed and
Harish K. Krishnamurthy and
Charles Augustine and
Xiaosen Liu and
Sheldon Weng and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Variation-Adaptive Integrated Computational Digital {LDO} in 22-nm
{CMOS} With Fast Transient Response},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {4},
pages = {977--987},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2961854},
doi = {10.1109/JSSC.2019.2961854},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AhmedKALWRTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BangLAMKTD20,
author = {Suyoung Bang and
Wootaek Lim and
Charles Augustine and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {25.1 {A} Fully Synthesizable Distributed and Scalable All-Digital
{LDO} in 10nm {CMOS}},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {380--382},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063040},
doi = {10.1109/ISSCC19947.2020.9063040},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BangLAMKTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AugustinePMTKD20,
author = {Charles Augustine and
Somnath Paul and
Turbo Majumder and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162815},
doi = {10.1109/VLSICIRCUITS18222.2020.9162815},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AugustinePMTKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KulkarniMATTKD20,
author = {Jaydeep P. Kulkarni and
Andres Malavasi and
Charles Augustine and
Carlos Tokunaga and
Jim Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin,
Noise-Tolerant, High-Density, 1R1W 8T-Bitcell {SRAM} in 10nm FinFET
{CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162822},
doi = {10.1109/VLSICIRCUITS18222.2020.9162822},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KulkarniMATTKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PaulMAMUKKCYBOL20,
author = {Somnath Paul and
Turbo Majumder and
Charles Augustine and
Andres F. Malavasi and
S. Usirikayala and
Raghavan Kumar and
Jisna Kollikunnel and
S. Chhabra and
Satish Yada and
M. L. Barajas and
C. Ornelas and
Dan Lake and
Muhammad M. Khellah and
Jim Tschanz and
Vivek De},
title = {A 0.05pJ/Pixel 70fps {FHD} 1Meps Event-Driven Visual Data Processing
Unit},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162948},
doi = {10.1109/VLSICIRCUITS18222.2020.9162948},
timestamp = {Mon, 03 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/PaulMAMUKKCYBOL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MeinerzhagenTMV19,
author = {Pascal Andreas Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Xiang Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An Energy-Efficient Graphics Processor in 14-nm Tri-Gate {CMOS} Featuring
Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep,
and {\textdollar}\{V\}{\_}\{{\textbackslash}text\{MIN\}\}{\textdollar}
Optimization},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {1},
pages = {144--157},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2875097},
doi = {10.1109/JSSC.2018.2875097},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MeinerzhagenTMV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/WangYAID19,
author = {Xiaowei Wang and
Jiecao Yu and
Charles Augustine and
Ravi R. Iyer and
Reetuparna Das},
title = {Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks},
booktitle = {25th {IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2019, Washington, DC, USA, February 16-20, 2019},
pages = {81--93},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/HPCA.2019.00029},
doi = {10.1109/HPCA.2019.00029},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/WangYAID19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AhmedKALWRTD19,
author = {Khondker Zakir Ahmed and
Harish K. Krishnamurthy and
Charles Augustine and
Xiaosen Liu and
Sheldon Weng and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Variation-Adaptive Integrated Computational Digital {LDO} in 22nm
{CMOS} with Fast Transient Response},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {124},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778070},
doi = {10.23919/VLSIC.2019.8778070},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AhmedKALWRTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biocas/PedroniSMPAC18,
author = {Bruno U. Pedroni and
Sadique Sheik and
Hesham Mostafa and
Somnath Paul and
Charles Augustine and
Gert Cauwenberghs},
title = {Small-footprint Spiking Neural Networks for Power-efficient Keyword
Spotting},
booktitle = {2018 {IEEE} Biomedical Circuits and Systems Conference, BioCAS 2018,
Cleveland, OH, USA, October 17-19, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/BIOCAS.2018.8584832},
doi = {10.1109/BIOCAS.2018.8584832},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/biocas/PedroniSMPAC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MeinerzhagenTMV18,
author = {Pascal Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Chris Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An energy-efficient graphics processor featuring fine-grain {DVFS}
with integrated voltage regulators, execution-unit turbo, and retentive
sleep in 14nm tri-gate {CMOS}},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {38--40},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310172},
doi = {10.1109/ISSCC.2018.8310172},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MeinerzhagenTMV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChoKTAKRTKD17,
author = {Minki Cho and
Stephen T. Kim and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution
Core Using Adaptive Voltage Scaling and Dynamic Power Gating},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {50--63},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2601319},
doi = {10.1109/JSSC.2016.2601319},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChoKTAKRTKD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/NeftciAPD17,
author = {Emre Neftci and
Charles Augustine and
Somnath Paul and
Georgios Detorakis},
title = {Event-driven random backpropagation: Enabling neuromorphic deep learning
machines},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050529},
doi = {10.1109/ISCAS.2017.8050529},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/NeftciAPD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SheikPAC17,
author = {Sadique Sheik and
Somnath Paul and
Charles Augustine and
Gert Cauwenberghs},
title = {Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike
Pattern Detection},
journal = {CoRR},
volume = {abs/1701.01495},
year = {2017},
url = {http://arxiv.org/abs/1701.01495},
eprinttype = {arXiv},
eprint = {1701.01495},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SheikPAC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1709-10205,
author = {Georgios Detorakis and
Sadique Sheik and
Charles Augustine and
Somnath Paul and
Bruno U. Pedroni and
Nikil D. Dutt and
Jeffrey L. Krichmar and
Gert Cauwenberghs and
Emre Neftci},
title = {Neural and Synaptic Array Transceiver: {A} Brain-Inspired Computing
Framework for Embedded Learning},
journal = {CoRR},
volume = {abs/1709.10205},
year = {2017},
url = {http://arxiv.org/abs/1709.10205},
eprinttype = {arXiv},
eprint = {1709.10205},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1709-10205.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimSMJ0TAKRTKD16,
author = {Stephen T. Kim and
Yi{-}Chun Shih and
Kaushik Mazumdar and
Rinkle Jain and
Joseph F. Ryan and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Enabling Wide Autonomous {DVFS} in a 22 nm Graphics Execution Core
Using a Digitally Controlled Fully Integrated Voltage Regulator},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {18--30},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2457920},
doi = {10.1109/JSSC.2015.2457920},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimSMJ0TAKRTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KulkarniTANATD16,
author = {Jaydeep P. Kulkarni and
Carlos Tokunaga and
Paolo A. Aseron and
Trang Nguyen and
Charles Augustine and
James W. Tschanz and
Vivek De},
title = {A 409 {GOPS/W} Adaptive and Resilient Domino Register File in 22 nm
Tri-Gate {CMOS} Featuring In-Situ Timing Margin and Error Detection
for Tolerance to Within-Die Variation, Voltage Droop, Temperature
and Aging},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {117--129},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2463083},
doi = {10.1109/JSSC.2015.2463083},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KulkarniTANATD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/VenkatesanKSARR16,
author = {Rangharajan Venkatesan and
Vivek Joy Kozhikkottu and
Mrigank Sharad and
Charles Augustine and
Arijit Raychowdhury and
Kaushik Roy and
Anand Raghunathan},
title = {Cache Design with Domain Wall Memory},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {4},
pages = {1010--1024},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2506581},
doi = {10.1109/TC.2015.2506581},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/VenkatesanKSARR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biocas/SheikPAC16,
author = {Sadique Sheik and
Somnath Paul and
Charles Augustine and
Gert Cauwenberghs},
title = {Membrane-dependent neuromorphic learning rule for unsupervised spike
pattern detection},
booktitle = {{IEEE} Biomedical Circuits and Systems Conference, BioCAS 2016, Shanghai,
China, October 17-19, 2016},
pages = {164--167},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/BioCAS.2016.7833757},
doi = {10.1109/BIOCAS.2016.7833757},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/biocas/SheikPAC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biocas/PedroniSJDPANC16,
author = {Bruno U. Pedroni and
Sadique Sheik and
Siddharth Joshi and
Georgios Detorakis and
Somnath Paul and
Charles Augustine and
Emre Neftci and
Gert Cauwenberghs},
title = {Forward table-based presynaptic event-triggered spike-timing-dependent
plasticity},
booktitle = {{IEEE} Biomedical Circuits and Systems Conference, BioCAS 2016, Shanghai,
China, October 17-19, 2016},
pages = {580--583},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/BioCAS.2016.7833861},
doi = {10.1109/BIOCAS.2016.7833861},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/biocas/PedroniSJDPANC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SheikPAKKCN16,
author = {Sadique Sheik and
Somnath Paul and
Charles Augustine and
Chinnikrishna Kothapalli and
Muhammad M. Khellah and
Gert Cauwenberghs and
Emre Neftci},
title = {Synaptic sampling in hardware spiking neural networks},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {2090--2093},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7538991},
doi = {10.1109/ISCAS.2016.7538991},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SheikPAKKCN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChoKTAKRTKD16,
author = {Minki Cho and
Stephen T. Kim and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution
core using adaptive voltage scaling and dynamic power gating},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {152--153},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417952},
doi = {10.1109/ISSCC.2016.7417952},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChoKTAKRTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/PedroniSJDPANC16,
author = {Bruno U. Pedroni and
Sadique Sheik and
Siddharth Joshi and
Georgios Detorakis and
Somnath Paul and
Charles Augustine and
Emre Neftci and
Gert Cauwenberghs},
title = {Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent
Plasticity},
journal = {CoRR},
volume = {abs/1607.03070},
year = {2016},
url = {http://arxiv.org/abs/1607.03070},
eprinttype = {arXiv},
eprint = {1607.03070},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/PedroniSJDPANC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/NeftciAPD16,
author = {Emre Neftci and
Charles Augustine and
Somnath Paul and
Georgios Detorakis},
title = {Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning
Machines},
journal = {CoRR},
volume = {abs/1612.05596},
year = {2016},
url = {http://arxiv.org/abs/1612.05596},
eprinttype = {arXiv},
eprint = {1612.05596},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/NeftciAPD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimSMJRTAKRTKD15,
author = {Stephen T. Kim and
Yi{-}Chun Shih and
Kaushik Mazumdar and
Rinkle Jain and
Joseph F. Ryan and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {8.6 Enabling wide autonomous {DVFS} in a 22nm graphics execution core
using a digitally controlled hybrid LDO/switched-capacitor {VR} with
fast droop mitigation},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062972},
doi = {10.1109/ISSCC.2015.7062972},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimSMJRTAKRTKD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KulkarniTANATD15,
author = {Jaydeep P. Kulkarni and
Carlos Tokunaga and
Paolo A. Aseron and
Trang Nguyen and
Charles Augustine and
James W. Tschanz and
Vivek De},
title = {4.7 {A} 409GOPS/W adaptive and resilient domino register file in 22nm
tri-gate {CMOS} featuring in-situ timing margin and error detection
for tolerance to within-die variation, voltage droop, temperature
and aging},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062936},
doi = {10.1109/ISSCC.2015.7062936},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KulkarniTANATD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TokunagaRAKSKJB14,
author = {Carlos Tokunaga and
Joseph F. Ryan and
Charles Augustine and
Jaydeep P. Kulkarni and
Yi{-}Chun Shih and
Stephen T. Kim and
Rinkle Jain and
Keith A. Bowman and
Arijit Raychowdhury and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {5.7 {A} graphics execution core in 22nm {CMOS} featuring adaptive
clocking, selective boosting and state-retentive sleep},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {108--109},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757359},
doi = {10.1109/ISSCC.2014.6757359},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TokunagaRAKSKJB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/MojumderFAGCR13,
author = {Niladri Narayan Mojumder and
Xuanyao Fong and
Charles Augustine and
Sumeet Kumar Gupta and
Sri Harsha Choday and
Kaushik Roy},
title = {Dual pillar spin-transfer torque MRAMs for low power applications},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {9},
number = {2},
pages = {14:1--14:17},
year = {2013},
url = {https://doi.org/10.1145/2463585.2463590},
doi = {10.1145/2463585.2463590},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/MojumderFAGCR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChenBAZT13,
author = {Chia{-}Hsiang Chen and
Keith A. Bowman and
Charles Augustine and
Zhengya Zhang and
Jim Tschanz},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {Minimum supply voltage for sequential logic circuits in a 22nm technology},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {181--186},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629291},
doi = {10.1109/ISLPED.2013.6629291},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ChenBAZT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SharadAPR12,
author = {Mrigank Sharad and
Charles Augustine and
Georgios Panagopoulos and
Kaushik Roy},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {Cognitive computing with spin-based neural networks},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {1262--1263},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228594},
doi = {10.1145/2228360.2228594},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SharadAPR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PanagopoulosAR12,
author = {Georgios Panagopoulos and
Charles Augustine and
Kaushik Roy},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {A framework for simulating hybrid {MTJ/CMOS} circuits: Atoms to system
approach},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {1443--1446},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176592},
doi = {10.1109/DATE.2012.6176592},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PanagopoulosAR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ijcnn/SharadAPR12,
author = {Mrigank Sharad and
Charles Augustine and
Georgios Panagopoulos and
Kaushik Roy},
title = {Spin based neuron-synapse module for ultra low power programmable
computational networks},
booktitle = {The 2012 International Joint Conference on Neural Networks (IJCNN),
Brisbane, Australia, June 10-15, 2012},
pages = {1--7},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/IJCNN.2012.6252609},
doi = {10.1109/IJCNN.2012.6252609},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/ijcnn/SharadAPR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/VenkatesanKARRR12,
author = {Rangharajan Venkatesan and
Vivek Joy Kozhikkottu and
Charles Augustine and
Arijit Raychowdhury and
Kaushik Roy and
Anand Raghunathan},
editor = {Naresh R. Shanbhag and
Massimo Poncino and
Pai H. Chou and
Ajith Amerasekera},
title = {TapeCache: a high density, energy efficient cache based on domain
wall memory},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12,
Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
pages = {185--190},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2333660.2333707},
doi = {10.1145/2333660.2333707},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/VenkatesanKARRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/SharadAPR12,
author = {Mrigank Sharad and
Charles Augustine and
Georgios Panagopoulos and
Kaushik Roy},
editor = {Csaba Andras Moritz},
title = {Ultra low energy analog image processing using spin based neurons},
booktitle = {Proceedings of the 2012 {IEEE/ACM} International Symposium on Nanoscale
Architectures, {NANOARCH} 2012, Amsterdam, The Netherlands, July 4-6,
2012},
pages = {211--217},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2765491.2765529},
doi = {10.1145/2765491.2765529},
timestamp = {Wed, 11 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nanoarch/SharadAPR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1206-3227,
author = {Mrigank Sharad and
Charles Augustine and
Georgios Panagopoulos and
Kaushik Roy},
title = {Proposal For Neuromorphic Hardware Using Spin Devices},
journal = {CoRR},
volume = {abs/1206.3227},
year = {2012},
url = {http://arxiv.org/abs/1206.3227},
eprinttype = {arXiv},
eprint = {1206.3227},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1206-3227.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/VenkatesanCARR11,
author = {Rangharajan Venkatesan and
Vinay K. Chippa and
Charles Augustine and
Kaushik Roy and
Anand Raghunathan},
title = {Energy efficient many-core processor for recognition and mining using
spin-based memory},
booktitle = {Proceedings of the 2011 {IEEE/ACM} International Symposium on Nanoscale
Architectures, {NANOARCH} 2011, San Diego, CA, USA, June 8-9, 2011},
pages = {122--128},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/NANOARCH.2011.5941493},
doi = {10.1109/NANOARCH.2011.5941493},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/VenkatesanCARR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/AugustinePBSSR11,
author = {Charles Augustine and
Georgios Panagopoulos and
Behtash Behin{-}Aein and
Srikant Srinivasan and
Angik Sarkar and
Kaushik Roy},
title = {Low-power functionality enhanced computation architecture using spin-based
devices},
booktitle = {Proceedings of the 2011 {IEEE/ACM} International Symposium on Nanoscale
Architectures, {NANOARCH} 2011, San Diego, CA, USA, June 8-9, 2011},
pages = {129--136},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/NANOARCH.2011.5941494},
doi = {10.1109/NANOARCH.2011.5941494},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/AugustinePBSSR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/MoradiAGKCWMR10,
author = {Farshad Moradi and
Charles Augustine and
Ashish Goel and
Georgios Karakonstantis and
Tuan Vu Cao and
Dag T. Wisland and
Hamid Mahmoodi and
Kaushik Roy},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Data-dependant sense-amplifier flip-flop for low power applications},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617468},
doi = {10.1109/CICC.2010.5617468},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/MoradiAGKCWMR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/KarakonstantisAR10,
author = {Georgios Karakonstantis and
Charles Augustine and
Kaushik Roy},
title = {A self-consistent model to estimate {NBTI} degradation and a comprehensive
on-line system lifetime enhancement technique},
booktitle = {16th {IEEE} International On-Line Testing Symposium {(IOLTS} 2010),
5-7 July, 2010, Corfu, Greece},
pages = {3--8},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/IOLTS.2010.5560240},
doi = {10.1109/IOLTS.2010.5560240},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/KarakonstantisAR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/AugustineBFR09,
author = {Charles Augustine and
Behtash Behin{-}Aein and
Xuanyao Fong and
Kaushik Roy},
editor = {Kazutoshi Wakabayashi},
title = {A design methodology and device/circuit/architecture compatible simulation
framework for low-power magnetic quantum cellular automata systems},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {847--852},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796586},
doi = {10.1109/ASPDAC.2009.4796586},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/AugustineBFR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/AugustineRGLR09,
author = {Charles Augustine and
Arijit Raychowdhury and
Yunfei Gao and
Mark S. Lundstrom and
Kaushik Roy},
title = {{PETE:} {A} device/circuit analysis framework for evaluation and comparison
of charge based emerging devices},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {80--85},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810273},
doi = {10.1109/ISQED.2009.4810273},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/AugustineRGLR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiASR08,
author = {Jing Li and
Charles Augustine and
Sayeef S. Salahuddin and
Kaushik Roy},
editor = {Limor Fix},
title = {Modeling of failure probability and statistical design of spin-torque
transfer magnetic random access memory {(STT} {MRAM)} array for yield
enhancement},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {278--283},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391540},
doi = {10.1145/1391469.1391540},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiASR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/BanerjeeAR08,
author = {Nilanjan Banerjee and
Charles Augustine and
Kaushik Roy},
editor = {Cristiana Bolchini and
Yong{-}Bin Kim and
Dimitris Gizopoulos and
Mohammad Tehranipoor},
title = {Fault-Tolerance with Graceful Degradation in Quality: {A} Design Methodology
and Its Application to Digital Signal Processing Systems},
booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}},
pages = {323--331},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DFT.2008.43},
doi = {10.1109/DFT.2008.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/BanerjeeAR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/OsterholtzAMRSS92,
author = {Louise Osterholtz and
Charles Augustine and
Arthur E. McNair and
Ivica Rogina and
Hiroaki Saito and
Tilo Sloboda and
Joe Tebelskis and
Alex Waibel},
title = {Testing generality in {JANUS:} a multi-lingual speech translation
system},
booktitle = {1992 {IEEE} International Conference on Acoustics, Speech, and Signal
Processing, {ICASSP} '92, San Francisco, California, USA, March 23-26,
1992},
pages = {209--212},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ICASSP.1992.225935},
doi = {10.1109/ICASSP.1992.225935},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/icassp/OsterholtzAMRSS92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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