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ORCIDBibTeX records: Davor Capalija
@article{DBLP:journals/micro/VasiljevicBCSIB21,
author = {Jasmina Vasiljevic and
Ljubisa Bajic and
Davor Capalija and
Stanislav Sokorac and
Dragoljub Ignjatovic and
Lejla Bajic and
Milos Trajkovic and
Ivan Hamer and
Ivan Matosevic and
Aleksandar Cejkov and
Utku Aydonat and
Tony Zhou and
Syed Zohaib Gilani and
Armond Paiva and
Joseph Chu and
Djordje Maksimovic and
Stephen Alexander Chin and
Zahi Moudallal and
Akhmed Rakhmati and
Sean Nijjar and
Almeet Bhullar and
Boris Drazic and
Charles Lee and
James Sun and
Kei{-}Ming Kwong and
James Connolly and
Miles Dooley and
Hassan Farooq and
Joy Yu Ting Chen and
Matthew Walker and
Keivan Dabiri and
Kyle Mabee and
Rakesh Shaji Lal and
Namal Rajatheva and
Renjith Retnamma and
Shripad Karodi and
Daniel Rosen and
Emilio Munoz and
Andrew Lewycky and
Aleksandar Knezevic and
Raymond Kim and
Allan Rui and
Alexander Drouillard and
David Thompson},
title = {Compute Substrate for Software 2.0},
journal = {{IEEE} Micro},
volume = {41},
number = {2},
pages = {50--55},
year = {2021},
url = {https://doi.org/10.1109/MM.2021.3061912},
doi = {10.1109/MM.2021.3061912},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/VasiljevicBCSIB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NurvitadhiCMMNC18,
author = {Eriko Nurvitadhi and
Jeffrey J. Cook and
Asit K. Mishra and
Debbie Marr and
Kevin Nealis and
Philip Colangelo and
Andrew C. Ling and
Davor Capalija and
Utku Aydonat and
Sergey Y. Shumarayev and
Aravind Dasu},
editor = {Jason Helge Anderson and
Kia Bazargan},
title = {In-Package Domain-Specific ASICs for Intel{\textregistered} Stratix{\textregistered}
10 FPGAs: {A} Case Study of Accelerating Deep Learning Using TensorTile
ASIC(Abstract Only)},
booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
pages = {287},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3174243.3174966},
doi = {10.1145/3174243.3174966},
timestamp = {Sat, 28 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/NurvitadhiCMMNC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/NurvitadhiCMMNC18,
author = {Eriko Nurvitadhi and
Jeffrey J. Cook and
Asit K. Mishra and
Debbie Marr and
Kevin Nealis and
Philip Colangelo and
Andrew C. Ling and
Davor Capalija and
Utku Aydonat and
Aravind Dasu and
Sergey Y. Shumarayev},
title = {In-Package Domain-Specific ASICs for Intel{\textregistered} Stratix{\textregistered}
10 FPGAs: {A} Case Study of Accelerating Deep Learning Using TensorTile
{ASIC}},
booktitle = {28th International Conference on Field Programmable Logic and Applications,
{FPL} 2018, Dublin, Ireland, August 27-31, 2018},
pages = {106--110},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FPL.2018.00027},
doi = {10.1109/FPL.2018.00027},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/NurvitadhiCMMNC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ChiuLCBA18,
author = {Gordon R. Chiu and
Andrew C. Ling and
Davor Capalija and
Andrew Bitar and
Mohamed S. Abdelfattah},
editor = {Chris Chu and
Ismail Bustany},
title = {Flexibility: FPGAs and {CAD} in Deep Learning Acceleration},
booktitle = {Proceedings of the 2018 International Symposium on Physical Design,
{ISPD} 2018, Monterey, CA, USA, March 25-28, 2018},
pages = {34--41},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3177540.3177561},
doi = {10.1145/3177540.3177561},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ChiuLCBA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AydonatOCLC17,
author = {Utku Aydonat and
Shane O'Connell and
Davor Capalija and
Andrew C. Ling and
Gordon R. Chiu},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {An OpenCL{\texttrademark} Deep Learning Accelerator on Arria 10},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {55--64},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021738},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AydonatOCLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YingerNCLMSMS17,
author = {Jack Yinger and
Eriko Nurvitadhi and
Davor Capalija and
Andrew C. Ling and
Debbie Marr and
Krishnan Srivatsan and
Duncan J. M. Moss and
Suchit Subhaschandra},
title = {Customizable {FPGA} OpenCL matrix multiply design template for deep
neural networks},
booktitle = {International Conference on Field Programmable Technology, {FPT} 2017,
Melbourne, Australia, December 11-13, 2017},
pages = {259--262},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FPT.2017.8280155},
doi = {10.1109/FPT.2017.8280155},
timestamp = {Mon, 17 Feb 2020 13:32:07 +0100},
biburl = {https://dblp.org/rec/conf/fpt/YingerNCLMSMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwocl/LingAOCC17,
author = {Andrew C. Ling and
Utku Aydonat and
Shane O'Connell and
Davor Capalija and
Gordon R. Chiu},
editor = {Simon McIntosh{-}Smith and
Ben Bergen},
title = {Creating High Performance Applications with Intel's {FPGA} OpenCL{\texttrademark}
{SDK}},
booktitle = {Proceedings of the 5th International Workshop on OpenCL, {IWOCL} 2017,
Toronto, Canada, May 16-18, 2017},
pages = {11:1},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3078155.3078169},
doi = {10.1145/3078155.3078169},
timestamp = {Mon, 21 Dec 2020 16:56:10 +0100},
biburl = {https://dblp.org/rec/conf/iwocl/LingAOCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/AydonatOCLC17,
author = {Utku Aydonat and
Shane O'Connell and
Davor Capalija and
Andrew C. Ling and
Gordon R. Chiu},
title = {An OpenCL(TM) Deep Learning Accelerator on Arria 10},
journal = {CoRR},
volume = {abs/1701.03534},
year = {2017},
url = {http://arxiv.org/abs/1701.03534},
eprinttype = {arXiv},
eprint = {1701.03534},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/AydonatOCLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/CapalijaA14,
author = {Davor Capalija and
Tarek S. Abdelrahman},
title = {Tile-based bottom-up compilation of custom mesh-of-functional-units
{FPGA} overlays},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927456},
doi = {10.1109/FPL.2014.6927456},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/CapalijaA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/CapalijaA13,
author = {Davor Capalija and
Tarek S. Abdelrahman},
title = {Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {24},
number = {2},
pages = {392--405},
year = {2013},
url = {https://doi.org/10.1109/TPDS.2012.135},
doi = {10.1109/TPDS.2012.135},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/CapalijaA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/CapalijaA13,
author = {Davor Capalija and
Tarek S. Abdelrahman},
title = {A high-performance overlay architecture for pipelined execution of
data flow graphs},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645515},
doi = {10.1109/FPL.2013.6645515},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/CapalijaA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/CapalijaA11,
author = {Davor Capalija and
Tarek S. Abdelrahman},
editor = {Paul Chow and
Michael J. Wirthlin},
title = {Towards Synthesis-Free {JIT} Compilation to Commodity FPGAs},
booktitle = {{IEEE} 19th Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2011, Salt Lake City, Utah, USA, 1-3 May
2011},
pages = {202--205},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FCCM.2011.25},
doi = {10.1109/FCCM.2011.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/CapalijaA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/FortCVB06,
author = {Blair Fort and
Davor Capalija and
Zvonko G. Vranesic and
Stephen Dean Brown},
title = {A Multithreaded Soft Processor for SoPC Area Reduction},
booktitle = {14th {IEEE} Symposium on Field-Programmable Custom Computing Machines
{(FCCM} 2006), 24-26 April 2006, Napa, CA, USA, Proceedings},
pages = {131--142},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/FCCM.2006.10},
doi = {10.1109/FCCM.2006.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/FortCVB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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