Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Lawrence T. Clark
@article{DBLP:journals/mj/VashishthaC22,
author = {Vinay Vashishtha and
Lawrence T. Clark},
title = {{ASAP5:} {A} predictive {PDK} for the 5 nm node},
journal = {Microelectron. J.},
volume = {126},
pages = {105481},
year = {2022},
url = {https://doi.org/10.1016/j.mejo.2022.105481},
doi = {10.1016/J.MEJO.2022.105481},
timestamp = {Fri, 08 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/VashishthaC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ClarkDYCBANWBM22,
author = {Lawrence T. Clark and
Alen Duvnjak and
Clifford Young{-}Sciortino and
Matthew Cannon and
John S. Brunhaver and
Sapan Agarwal and
Jereme Neuendank and
Donald Wilson and
Hugh J. Barnaby and
Matthew J. Marinella},
title = {Self-correcting Flip-flops for Triple Modular Redundant Logic in a
12-nm Technology},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {1205--1209},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937935},
doi = {10.1109/ISCAS48785.2022.9937935},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ClarkDYCBANWBM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/VashishthaC21,
author = {Vinay Vashishtha and
Lawrence T. Clark},
title = {Comparing bulk-Si FinFET and gate-all-around FETs for the 5 {\unicode{8203}}nm
technology node},
journal = {Microelectron. J.},
volume = {107},
pages = {104942},
year = {2021},
url = {https://doi.org/10.1016/j.mejo.2020.104942},
doi = {10.1016/J.MEJO.2020.104942},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/VashishthaC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ClarkAH19,
author = {Lawrence T. Clark and
James Adams and
Keith E. Holbert},
title = {Reliable techniques for integrated circuit identification and true
random number generation using 1.5-transistor flash memory},
journal = {Integr.},
volume = {65},
pages = {263--272},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.10.001},
doi = {10.1016/J.VLSI.2017.10.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ClarkAH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ClarkMKB19,
author = {Lawrence T. Clark and
Sai Bharadwaj Medapuram and
Divya Kiran Kadiyala and
John S. Brunhaver},
title = {Physically Unclonable Functions Using Foundry {SRAM} Cells},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {3},
pages = {955--966},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2018.2873777},
doi = {10.1109/TCSI.2018.2873777},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/ClarkMKB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/BrunhaverUC19,
author = {John S. Brunhaver and
Richard Uhrie and
Lawrence T. Clark},
title = {Itemization and Track Limitations of Fan-Out-Free Functions for Static
{CMOS} Functional Cells},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {7},
pages = {1164--1168},
year = {2019},
url = {https://doi.org/10.1109/TCSII.2018.2875334},
doi = {10.1109/TCSII.2018.2875334},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/BrunhaverUC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ClarkMK18,
author = {Lawrence T. Clark and
Sai Bharadwaj Medapuram and
Divya Kiran Kadiyala},
title = {{SRAM} Circuits for True Random Number Generation Using Intrinsic
Bit Instability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2027--2037},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2840049},
doi = {10.1109/TVLSI.2018.2840049},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ClarkMK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ClarkV17,
author = {Lawrence T. Clark and
Vinay Vashishtha},
title = {Design with sub-10 nm FinFET technologies},
booktitle = {2017 {IEEE} Custom Integrated Circuits Conference, {CICC} 2017, Austin,
TX, USA, April 30 - May 3, 2017},
pages = {1--87},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/CICC.2017.7993720},
doi = {10.1109/CICC.2017.7993720},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ClarkV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/VashishthaVC17,
author = {Vinay Vashishtha and
Manoj Vangala and
Lawrence T. Clark},
editor = {Sri Parameswaran},
title = {{ASAP7} predictive design kit development and cell design technology
co-optimization: Invited paper},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {992--998},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203889},
doi = {10.1109/ICCAD.2017.8203889},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/VashishthaVC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VashishthaVSC17,
author = {Vinay Vashishtha and
Manoj Vangala and
Parv Sharma and
Lawrence T. Clark},
title = {Robust 7-nm {SRAM} design on a predictive {PDK}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050316},
doi = {10.1109/ISCAS.2017.8050316},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VashishthaVSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/VashishthaDMC17,
author = {Vinay Vashishtha and
Ankita Dosi and
Lovish Masand and
Lawrence T. Clark},
title = {Design technology co-optimization of back end of line design rules
for a 7 nm predictive process design kit},
booktitle = {18th International Symposium on Quality Electronic Design, {ISQED}
2017, Santa Clara, CA, USA, March 14-15, 2017},
pages = {149--154},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISQED.2017.7918308},
doi = {10.1109/ISQED.2017.7918308},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/VashishthaDMC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ClarkAH17,
author = {Lawrence T. Clark and
James Adams and
Keith E. Holbert},
title = {Integrated circuit identification and true random numbers using 1.5-transistor
flash memory},
booktitle = {18th International Symposium on Quality Electronic Design, {ISQED}
2017, Santa Clara, CA, USA, March 14-15, 2017},
pages = {244--249},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISQED.2017.7918323},
doi = {10.1109/ISQED.2017.7918323},
timestamp = {Thu, 11 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ClarkAH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mse/ClarkVHDW17,
author = {Lawrence T. Clark and
Vinay Vashishtha and
David M. Harris and
Samuel Dietrich and
Zunyan Wang},
title = {Design flows and collateral for the {ASAP7} 7nm FinFET predictive
process design kit},
booktitle = {2017 {IEEE} International Conference on Microelectronic Systems Education,
{MSE} 2017, Lake Louise, AB, Canada, May 11-12, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MSE.2017.7945071},
doi = {10.1109/MSE.2017.7945071},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/mse/ClarkVHDW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ClarkVSGSCRY16,
author = {Lawrence T. Clark and
Vinay Vashishtha and
Lucian Shifren and
Aditya Gujja and
Saurabh Sinha and
Brian Cline and
Chandarasekaran Ramamurthy and
Greg Yeric},
title = {{ASAP7:} {A} 7-nm finFET predictive process design kit},
journal = {Microelectron. J.},
volume = {53},
pages = {105--115},
year = {2016},
url = {https://doi.org/10.1016/j.mejo.2016.04.006},
doi = {10.1016/J.MEJO.2016.04.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/ClarkVSGSCRY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ClarkPRH16,
author = {Lawrence T. Clark and
Dan W. Patterson and
Chandarasekaran Ramamurthy and
Keith E. Holbert},
title = {An Embedded Microprocessor Radiation Hardened by Microarchitecture
and Circuits},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {2},
pages = {382--395},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2419661},
doi = {10.1109/TC.2015.2419661},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ClarkPRH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChellappaC16,
author = {Srivatsan Chellappa and
Lawrence T. Clark},
title = {SRAM-Based Unique Chip Identifier Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {4},
pages = {1213--1222},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2445751},
doi = {10.1109/TVLSI.2015.2445751},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChellappaC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/RosaCC15,
author = {Jos{\'{e}} M. de la Rosa and
Patrick Chiang and
Lawrence T. Clark},
title = {Guest Editorial: Special Section on the 2014 {IEEE} Custom Integrated
Circuits Conference {(CICC} 2014)},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {62-I},
number = {8},
pages = {1897--1898},
year = {2015},
url = {https://doi.org/10.1109/TCSI.2015.2458411},
doi = {10.1109/TCSI.2015.2458411},
timestamp = {Fri, 03 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/RosaCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/VashishthaCCGGF15,
author = {Vinay Vashishtha and
Lawrence T. Clark and
Srivatsan Chellappa and
Anudeep R. Gogulamudi and
Aditya Gujja and
Chad Farnsworth},
title = {A soft-error hardened process portable embedded microprocessor},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338366},
doi = {10.1109/CICC.2015.7338366},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/VashishthaCCGGF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KumarCC15,
author = {Sushil Kumar and
Srivatsan Chellappa and
Lawrence T. Clark},
title = {Temporal pulse-clocked multi-bit flip-flop mitigating {SET} and {SEU}},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {814--817},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7168758},
doi = {10.1109/ISCAS.2015.7168758},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KumarCC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PrivatC15,
author = {Aymeric Privat and
Lawrence T. Clark},
title = {Simple and accurate single event charge collection macro modeling
for circuit simulation},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {1858--1861},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169019},
doi = {10.1109/ISCAS.2015.7169019},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PrivatC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VashishthaGC15,
author = {Vinay Vashishtha and
Aditya Gujja and
Lawrence T. Clark},
title = {Delay and power tradeoffs for static and dynamic register files},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {2900--2903},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169293},
doi = {10.1109/ISCAS.2015.7169293},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VashishthaGC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChellappaRVC15,
author = {Srivatsan Chellappa and
Chandarasekaran Ramamurthy and
Vinay Vashishtha and
Lawrence T. Clark},
title = {Advanced encryption system with dynamic pipeline reconfiguration for
minimum energy operation},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {201--206},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085425},
doi = {10.1109/ISQED.2015.7085425},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChellappaRVC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ClarkKALK14,
author = {Lawrence T. Clark and
David Kidd and
Vineet Agrawal and
Samuel Leshner and
Gokul Krishnan},
title = {Independent {N} and {P} process monitors for body bias based process
corner correction},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6946092},
doi = {10.1109/CICC.2014.6946092},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ClarkKALK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PrivatCB14,
author = {Aymeric Privat and
Lawrence T. Clark and
Hugh J. Barnaby},
title = {Transient response exploration of {SRAM} cell metastable states caused
by ionizing radiation with 3D mixed mode simulation},
booktitle = {21st {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},
pages = {443--446},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICECS.2014.7050017},
doi = {10.1109/ICECS.2014.7050017},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PrivatCB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ShambhulingaiahCKC14,
author = {Sandeep Shambhulingaiah and
Srivatsan Chellappa and
Sushil Kumar and
Lawrence T. Clark},
title = {Methodology to optimize critical node separation in hardened flip-flops},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
2014, Santa Clara, CA, USA, March 3-5, 2014},
pages = {486--490},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISQED.2014.6783364},
doi = {10.1109/ISQED.2014.6783364},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ShambhulingaiahCKC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ClarkS14,
author = {Lawrence T. Clark and
Sandeep Shambhulingaiah},
title = {Methodical Design Approaches to Radiation Effects Analysis and Mitigation
in Flip-Flop Circuits},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2014, Tampa,
FL, USA, July 9-11, 2014},
pages = {595--600},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISVLSI.2014.74},
doi = {10.1109/ISVLSI.2014.74},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ClarkS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/RogenmoserC13,
author = {Robert Rogenmoser and
Lawrence T. Clark},
title = {Reducing Transistor Variability for High Performance Low Power Chips},
journal = {{IEEE} Micro},
volume = {33},
number = {2},
pages = {18--26},
year = {2013},
url = {https://doi.org/10.1109/MM.2013.10},
doi = {10.1109/MM.2013.10},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/RogenmoserC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MhambreyMC13,
author = {Siddhesh S. Mhambrey and
Satendra Kumar Maurya and
Lawrence T. Clark},
title = {Low Complexity Out-of-Order Issue Logic Using Static Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {380--384},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2184310},
doi = {10.1109/TVLSI.2012.2184310},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MhambreyMC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/AgrawalKKKLBZRRWCRHEMTYMW13,
author = {Vineet Agrawal and
N. Kepler and
David Kidd and
Gokul Krishnan and
Samuel Leshner and
T. Bakishev and
D. Zhao and
P. Ranade and
R. Roy and
M. Wojko and
Lawrence T. Clark and
Robert Rogenmoser and
M. Hori and
Taiji Ema and
S. Moriwaki and
T. Tsuruta and
T. Yamada and
J. Mitani and
S. Wakayama},
title = {Low power ARM{\textregistered} Cortex{\texttrademark}-M0 {CPU} and
{SRAM} using Deeply Depleted Channel {(DDC)} transistors with Vdd
scaling and body bias},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658514},
doi = {10.1109/CICC.2013.6658514},
timestamp = {Mon, 23 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/AgrawalKKKLBZRRWCRHEMTYMW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ClarkLT13,
author = {Lawrence T. Clark and
Samuel Leshner and
George Tien},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {{SRAM} cell optimization for low {AVT} transistors},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {57--63},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629267},
doi = {10.1109/ISLPED.2013.6629267},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/ClarkLT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/MauryaC11,
author = {Satendra Kumar Maurya and
Lawrence T. Clark},
title = {A Specialized Static Content Addressable Memory for Longest Prefix
Matching in Internet Protocol Routing},
journal = {J. Low Power Electron.},
volume = {7},
number = {3},
pages = {350--363},
year = {2011},
url = {https://doi.org/10.1166/jolpe.2011.1142},
doi = {10.1166/JOLPE.2011.1142},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/MauryaC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MauryaC11,
author = {Satendra Kumar Maurya and
Lawrence T. Clark},
title = {A Dynamic Longest Prefix Matching Content Addressable Memory for {IP}
Routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {6},
pages = {963--972},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2042826},
doi = {10.1109/TVLSI.2010.2042826},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MauryaC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ChellappaDC11,
author = {Srivatsan Chellappa and
Aritra Dey and
Lawrence T. Clark},
editor = {Rakesh Patel and
Tom Andre and
Aurangzeb Khan},
title = {Improved circuits for microchip identification using {SRAM} mismatch},
booktitle = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
Jose, CA, USA, Sept. 19-21, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CICC.2011.6055318},
doi = {10.1109/CICC.2011.6055318},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ChellappaDC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ClarkCC11,
author = {Lawrence T. Clark and
Tai{-}Hua Chen and
Vikas Chaudhary},
title = {Efficient voltage conversion for {SRAM} low standby power modes},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {73--76},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5937504},
doi = {10.1109/ISCAS.2011.5937504},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ClarkCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ClarkPHH11,
author = {Lawrence T. Clark and
David E. Pettit and
Keith E. Holbert and
Nathan D. Hindman},
title = {Validation of and delay variation in total ionizing dose hardened
standard cell libraries},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {2051--2054},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5938000},
doi = {10.1109/ISCAS.2011.5938000},
timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ClarkPHH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/YaoCPH10,
author = {Xiaoyin Yao and
Lawrence T. Clark and
Dan W. Patterson and
Keith E. Holbert},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Single event transient mitigation in cache memory using transient
error checking circuits},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617439},
doi = {10.1109/CICC.2010.5617439},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/YaoCPH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChellappaNYHVCCC10,
author = {Srivatsan Chellappa and
Jia Ni and
Xiaoyin Yao and
Nathan D. Hindman and
Jyothi Velamala and
Min Chen and
Yu Cao and
Lawrence T. Clark},
editor = {Sachin S. Sapatnekar},
title = {In-situ characterization and extraction of {SRAM} variability},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {711--716},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837454},
doi = {10.1145/1837274.1837454},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/ChellappaNYHVCCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MhambreyCMB10,
author = {Siddhesh S. Mhambrey and
Lawrence T. Clark and
Satendra Kumar Maurya and
Krzysztof S. Berezowski},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Out-of-order issue logic using sorting networks},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {385--388},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785570},
doi = {10.1145/1785481.1785570},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/MhambreyCMB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MauryaC10,
author = {Satendra Kumar Maurya and
Lawrence T. Clark},
title = {Fast and scalable priority encoding using static {CMOS}},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {433--436},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537688},
doi = {10.1109/ISCAS.2010.5537688},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MauryaC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ClarkC10,
author = {Lawrence T. Clark and
Vikas Chaudhary},
title = {Fast low power translation lookaside buffers using hierarchical {NAND}
match lines},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {3493--3496},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537832},
doi = {10.1109/ISCAS.2010.5537832},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ClarkC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DesaiHC09,
author = {Nishith N. Desai and
Jonathan R. Haigh and
Lawrence T. Clark},
title = {Reducing process variation impact on replica-timed static random access
memory sense timing},
journal = {Integr.},
volume = {42},
number = {4},
pages = {437--448},
year = {2009},
url = {https://doi.org/10.1016/j.vlsi.2009.03.002},
doi = {10.1016/J.VLSI.2009.03.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DesaiHC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SamsonC09,
author = {Giby Samson and
Lawrence T. Clark},
title = {Low-Power Race-Free Programmable Logic Arrays},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {3},
pages = {935--946},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2013764},
doi = {10.1109/JSSC.2009.2013764},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SamsonC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ClarkCH09,
author = {Lawrence T. Clark and
Anthony Chan Carusone and
Payam Heydari},
title = {Introduction to the Special Issue on the 2008 {IEEE} Custom Integrated
Circuits Conference},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {8},
pages = {2083--2084},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2028056},
doi = {10.1109/JSSC.2009.2028056},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ClarkCH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/MauryaC09,
author = {Satendra Kumar Maurya and
Lawrence T. Clark},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {Low power fast and dense longest prefix match content addressable
memory for {IP} routers},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {389--394},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594333},
doi = {10.1145/1594233.1594333},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/MauryaC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/ChaudharyCSC08,
author = {Vikas Chaudhary and
Tai{-}Hua Chen and
F. Sheerin and
Lawrence T. Clark},
title = {Critical race-free low-power nand match line content addressable memory
tagged cache memory},
journal = {{IET} Comput. Digit. Tech.},
volume = {2},
number = {1},
pages = {40--44},
year = {2008},
url = {https://doi.org/10.1049/iet-cdt:20070040},
doi = {10.1049/IET-CDT:20070040},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/ChaudharyCSC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HaighC08,
author = {Jonathan R. Haigh and
Lawrence T. Clark},
title = {High performance set associative translation lookaside buffers for
low power microprocessors},
journal = {Integr.},
volume = {41},
number = {4},
pages = {509--523},
year = {2008},
url = {https://doi.org/10.1016/j.vlsi.2007.11.003},
doi = {10.1016/J.VLSI.2007.11.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HaighC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcp/BadrudduzaWSC08,
author = {Sayeed A. Badrudduza and
Ziyan Wang and
Giby Samson and
Lawrence T. Clark},
title = {Leakage Controlled Read Stable Static Random Access Memories},
journal = {J. Comput.},
volume = {3},
number = {4},
pages = {39--49},
year = {2008},
url = {http://www.jcomputers.us/index.php?m=content\&\#38;c=index\&\#38;a=show\&\#38;catid=57\&\#38;id=632},
doi = {10.4304/JCP.3.4.39-49},
timestamp = {Thu, 25 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcp/BadrudduzaWSC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ClarkGH08,
author = {Lawrence T. Clark and
Ranjit Gharpurey and
Payam Heydari},
title = {Introduction to the Special Issue on the {IEEE} 2007 Custom Integrated
Circuits Conference},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {8},
pages = {1714--1716},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2008.925600},
doi = {10.1109/JSSC.2008.925600},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ClarkGH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SamsonABC08,
author = {Giby Samson and
Nagaraj Ananthapadmanabhan and
Sayeed A. Badrudduza and
Lawrence T. Clark},
title = {Low-Power Dynamic Memory Word Line Decoding for Static Random Access
Memories},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {11},
pages = {2524--2532},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2008.2005813},
doi = {10.1109/JSSC.2008.2005813},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SamsonABC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ShringarpureCVAU08,
author = {Rahul Shringarpure and
Lawrence T. Clark and
Sameer M. Venugopal and
David R. Allee and
Shrinivas G. Uppili},
title = {Amorphous silicon logic circuits on flexible substrates},
booktitle = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference,
{CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September
21-24, 2008},
pages = {181--184},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/CICC.2008.4672053},
doi = {10.1109/CICC.2008.4672053},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ShringarpureCVAU08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CaoC07,
author = {Yu Cao and
Lawrence T. Clark},
title = {Mapping Statistical Process Variations Toward Circuit Performance
Variability: An Analytical Modeling Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {10},
pages = {1866--1873},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895613},
doi = {10.1109/TCAD.2007.895613},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CaoC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/BadrudduzaC07,
author = {Sayeed A. Badrudduza and
Lawrence T. Clark},
title = {Six and Seven Transistor Leakage Suppressed {SRAM} Cells with Improved
Read Stability},
booktitle = {Proceedings of the {IEEE} 2007 Custom Integrated Circuits Conference,
{CICC} 2007, DoubleTree Hotel, San Jose, California, USA, September
16-19, 2007},
pages = {225--228},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/CICC.2007.4405719},
doi = {10.1109/CICC.2007.4405719},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/BadrudduzaC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ClarkKK07,
author = {Lawrence T. Clark and
Mohammed Kabir and
Jonathan E. Knudsen},
title = {A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity},
booktitle = {Proceedings of the {IEEE} 2007 Custom Integrated Circuits Conference,
{CICC} 2007, DoubleTree Hotel, San Jose, California, USA, September
16-19, 2007},
pages = {571--574},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/CICC.2007.4405796},
doi = {10.1109/CICC.2007.4405796},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ClarkKK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BadrudduzaSC07,
author = {Sayeed A. Badrudduza and
Giby Samson and
Lawrence T. Clark},
title = {{LCSRAM:} {A} Leakage Controlled Six-transistor Static Random Access
Memory Cell with Intrinsically High Read Stability},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {621--626},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.96},
doi = {10.1109/VLSID.2007.96},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BadrudduzaSC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/ChenCC06,
author = {Tai{-}Hua Chen and
Jinhui Chen and
Lawrence T. Clark},
title = {Subthreshold to Above Threshold Level Shifter Design},
journal = {J. Low Power Electron.},
volume = {2},
number = {2},
pages = {251--258},
year = {2006},
url = {https://doi.org/10.1166/jolpe.2006.071},
doi = {10.1166/JOLPE.2006.071},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/ChenCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/BadrudduzaSC06,
author = {Sayeed A. Badrudduza and
Giby Samson and
Lawrence T. Clark},
title = {Static Random Access Memory Cells with Intrinsically High Read Stability
and Low Standby Power},
journal = {J. Low Power Electron.},
volume = {2},
number = {3},
pages = {412--424},
year = {2006},
url = {https://doi.org/10.1166/jolpe.2006.102},
doi = {10.1166/JOLPE.2006.102},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jolpe/BadrudduzaSC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCC06,
author = {Jinhui Chen and
Lawrence T. Clark and
Tai{-}Hua Chen},
title = {An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {10},
pages = {2344--2353},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2006.881549},
doi = {10.1109/JSSC.2006.881549},
timestamp = {Fri, 15 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChenCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaudharyC06,
author = {Vikas Chaudhary and
Lawrence T. Clark},
title = {Low-power high-performance nand match line content addressable memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {8},
pages = {895--905},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.878476},
doi = {10.1109/TVLSI.2006.878476},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaudharyC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SamsonC06,
author = {Giby Samson and
Lawrence T. Clark},
title = {A 0.13 {\(\mu\)}m Low-power Race-free Programmable Logic Array},
booktitle = {Proceedings of the {IEEE} 2006 Custom Integrated Circuits Conference,
{CICC} 2006, DoubleTree Hotel, San Jose, California, USA, September
10-13, 2006},
pages = {313--316},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/CICC.2006.320899},
doi = {10.1109/CICC.2006.320899},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/SamsonC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SamsonC06,
author = {Giby Samson and
Lawrence T. Clark},
editor = {Gang Qu and
Yehea I. Ismail and
Narayanan Vijaykrishnan and
Hai Zhou},
title = {Circuit architecture for low-power race-free programmable logic arrays},
booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006,
Philadelphia, PA, USA, April 30 - May 1, 2006},
pages = {416--421},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1127908.1128003},
doi = {10.1145/1127908.1128003},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SamsonC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ClarkRB05,
author = {Lawrence T. Clark and
Franco Ricci and
Manish Biyani},
title = {Low standby power state storage for sub-130-nm technologies},
journal = {{IEEE} J. Solid State Circuits},
volume = {40},
number = {2},
pages = {498--506},
year = {2005},
url = {https://doi.org/10.1109/JSSC.2004.840987},
doi = {10.1109/JSSC.2004.840987},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ClarkRB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HaighWMBSC05,
author = {Jonathan R. Haigh and
Michael W. Wilkerson and
Jay B. Miller and
Timothy S. Beatty and
Stephen J. Strazdus and
Lawrence T. Clark},
title = {A low-power 2.5-GHz 90-nm level 1 cache and memory management unit},
journal = {{IEEE} J. Solid State Circuits},
volume = {40},
number = {5},
pages = {1190--1199},
year = {2005},
url = {https://doi.org/10.1109/JSSC.2005.845971},
doi = {10.1109/JSSC.2005.845971},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HaighWMBSC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/WissmillerKALAC05,
author = {Kyle R. Wissmiller and
Jonathan E. Knudsen and
Travis J. Alward and
Zi P. Li and
David R. Allee and
Lawrence T. Clark},
title = {Reducing power in flexible a-Si digital circuits while preserving
state},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {219--222},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568646},
doi = {10.1109/CICC.2005.1568646},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/WissmillerKALAC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CaoC05,
author = {Yu Cao and
Lawrence T. Clark},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Mapping statistical process variations toward circuit performance
variability: an analytical modeling approach},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {658--663},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065752},
doi = {10.1145/1065579.1065752},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CaoC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ChenCC05,
author = {Jinhui Chen and
Lawrence T. Clark and
Yu Cao},
title = {Robust Design of High Fan-In/Out Subthreshold Circuits},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {405--410},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.96},
doi = {10.1109/ICCD.2005.96},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ChenCC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ClarkMB04,
author = {Lawrence T. Clark and
M. Morrow and
W. Brown},
title = {Reverse-body bias and supply collapse for low effective standby power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {9},
pages = {947--956},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.832930},
doi = {10.1109/TVLSI.2004.832930},
timestamp = {Thu, 14 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ClarkMB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ClarkPB04,
author = {Lawrence T. Clark and
Rakesh Patel and
Timothy S. Beatty},
editor = {Rajiv V. Joshi and
Kiyoung Choi and
Vivek Tiwari and
Kaushik Roy},
title = {Managing standby and active mode leakage power in deep sub-micron
design},
booktitle = {Proceedings of the 2004 International Symposium on Low Power Electronics
and Design, 2004, Newport Beach, California, USA, August 9-11, 2004},
pages = {274--279},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1013235.1013239},
doi = {10.1145/1013235.1013239},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ClarkPB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/Clark03,
author = {Lawrence T. Clark},
title = {Trends and challenges for wireless embedded DSPs},
booktitle = {Proceedings of the {IEEE} Custom Integrated Circuits Conference, {CICC}
2003, San Jose, CA, USA, September 21 - 24, 2003},
pages = {171--176},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CICC.2003.1249384},
doi = {10.1109/CICC.2003.1249384},
timestamp = {Mon, 15 Nov 2021 17:53:34 +0100},
biburl = {https://dblp.org/rec/conf/cicc/Clark03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ClarkCW03,
author = {Lawrence T. Clark and
Byungwoo Choi and
Michael W. Wilkerson},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {Reducing translation lookaside buffer active power},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {10--13},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871512},
doi = {10.1145/871506.871512},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ClarkCW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ClarkDDR02,
author = {Lawrence T. Clark and
Neil Deutscher and
Shay Demmons and
Franco Ricci},
editor = {Vivek De and
Mary Jane Irwin and
Ingrid Verbauwhede and
Christian Piguet},
title = {Standby power management for a 0.18{\(\mathrm{\mu}\)}m microprocessor},
booktitle = {Proceedings of the 2002 International Symposium on Low Power Electronics
and Design, 2002, Monterey, California, USA, August 12-14, 2002},
pages = {7--12},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/566408.566413},
doi = {10.1145/566408.566413},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ClarkDDR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ClarkHMBLSMVY01,
author = {Lawrence T. Clark and
Eric J. Hoffman and
Jay B. Miller and
Manish Biyani and
Yuyun Liao and
Stephen J. Strazdus and
Michael Morrow and
Kimberley E. Velarde and
Mark A. Yarch},
title = {An embedded 32-b microprocessor core for low-power and high-performance
applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {36},
number = {11},
pages = {1599--1608},
year = {2001},
url = {https://doi.org/10.1109/4.962279},
doi = {10.1109/4.962279},
timestamp = {Wed, 08 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ClarkHMBLSMVY01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ClarkT96,
author = {Lawrence T. Clark and
Gregory F. Taylor},
title = {High fan-in circuit design},
journal = {{IEEE} J. Solid State Circuits},
volume = {31},
number = {1},
pages = {91--96},
year = {1996},
url = {https://doi.org/10.1109/4.485870},
doi = {10.1109/4.485870},
timestamp = {Mon, 18 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ClarkT96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KrickCDWFDB94,
author = {Robert F. Krick and
Lawrence T. Clark and
Daniel J. Deleganes and
Keng L. Wong and
Roshan Fernando and
Goutam Debnath and
Jashojiban Banik},
title = {A 150 MHz 0.6 {\(\mu\)}m BiCMOS superscalar microprocessor},
journal = {{IEEE} J. Solid State Circuits},
volume = {29},
number = {12},
pages = {1455--1463},
year = {1994},
url = {https://doi.org/10.1109/4.340418},
doi = {10.1109/4.340418},
timestamp = {Tue, 09 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KrickCDWFDB94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/neco/RaoWCAG90,
author = {Arun Rao and
Mark R. Walker and
Lawrence T. Clark and
Lex A. Akers and
Robert O. Grondin},
title = {{VLSI} Implementation of Neural Classifiers},
journal = {Neural Comput.},
volume = {2},
number = {1},
pages = {35--43},
year = {1990},
url = {https://doi.org/10.1162/neco.1990.2.1.35},
doi = {10.1162/NECO.1990.2.1.35},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/neco/RaoWCAG90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-03-11 23:27 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
