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ORCIDBibTeX records: Philippe Flatresse
@inproceedings{DBLP:conf/isscc/MoursyRJQGPCWPP21,
author = {Yasser Moursy and
Thiago Raupp da Rosa and
Lionel Jure and
Anthony Quelen and
S{\'{e}}bastien Genevey and
Lionel Pierrefeu and
Emmanuel G. Collins Jr. and
Joerg Winkler and
Jonathan Park and
Ga{\"{e}}l Pillonnet and
Vincent Huard and
Andrea Bonzo and
Philippe Flatresse},
title = {A 0.021mm\({}^{\mbox{2}}\) PVT-Aware Digital-Flow-Compatible Adaptive
Back-Biasing Regulator with Scalable Drivers Achieving 450{\%} Frequency
Boosting and 30{\%} Power Reduction in 22nm {FDSOI} Technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {492--494},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365782},
doi = {10.1109/ISSCC42613.2021.9365782},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/MoursyRJQGPCWPP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MauroRPFB20,
author = {Alfio Di Mauro and
Davide Rossi and
Antonio Pullini and
Philippe Flatresse and
Luca Benini},
title = {Performance-aware predictive-model-based on-chip body-bias regulation
strategy for an {ULP} multi-core cluster in 28 nm {UTBB} {FD-SOI}},
journal = {Integr.},
volume = {72},
pages = {194--207},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.12.006},
doi = {10.1016/J.VLSI.2019.12.006},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MauroRPFB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2007-13667,
author = {Alfio Di Mauro and
Davide Rossi and
Antonio Pullini and
Philippe Flatresse and
Luca Benini},
title = {Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation
Strategy for an {ULP} Multi-Core Cluster in 28nm {UTBB} {FD-SOI}},
journal = {CoRR},
volume = {abs/2007.13667},
year = {2020},
url = {https://arxiv.org/abs/2007.13667},
eprinttype = {arXiv},
eprint = {2007.13667},
timestamp = {Wed, 29 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2007-13667.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/MhiraHAFB18,
author = {Souhir Mhira and
Vincent Huard and
D. Arora and
Philippe Flatresse and
Alain Bravaix},
title = {Resilient automotive products through process, temperature and aging
compensation schemes},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2018, Burlingame,
CA, USA, March 11-15, 2018},
pages = {3},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IRPS.2018.8353568},
doi = {10.1109/IRPS.2018.8353568},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/irps/MhiraHAFB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MauroRPFB18,
author = {Alfio Di Mauro and
Davide Rossi and
Antonio Pullini and
Philippe Flatresse and
Luca Benini},
title = {Live Demonstration: Body-Bias Based Performance Monitoring and Compensation
for a Near-Threshold Multi-Core Cluster in 28nm {FD-SOI} Technology},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351586},
doi = {10.1109/ISCAS.2018.8351586},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/MauroRPFB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/QuelenPFB18,
author = {Anthony Quelen and
Ga{\"{e}}l Pillonnet and
Philippe Flatresse and
Edith Beign{\'{e}}},
title = {A 2.5{\(\mu\)}W 0.0067mm\({}^{\mbox{2}}\) automatic back-biasing compensation
unit achieving 50{\%} leakage reduction in {FDSOI} 28nm over 0.35-to-1V
{VDD} range},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {304--306},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310305},
doi = {10.1109/ISSCC.2018.8310305},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/QuelenPFB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/RossiLPMBCBF17,
author = {Davide Rossi and
Igor Loi and
Antonio Pullini and
Thomas Christoph M{\"{u}}ller and
Andreas Burg and
Francesco Conti and
Luca Benini and
Philippe Flatresse},
title = {A Self-Aware Architecture for {PVT} Compensation and Power Nap in
Near Threshold Processors},
journal = {{IEEE} Des. Test},
volume = {34},
number = {6},
pages = {46--53},
year = {2017},
url = {https://doi.org/10.1109/MDAT.2017.2750907},
doi = {10.1109/MDAT.2017.2750907},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/RossiLPMBCBF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/GiardBMBTGFB17,
author = {Pascal Giard and
Alexios Balatsoukas{-}Stimming and
Thomas Christoph M{\"{u}}ller and
Andrea Bonetti and
Claude Thibeault and
Warren J. Gross and
Philippe Flatresse and
Andreas Burg},
title = {PolarBear: {A} 28-nm {FD-SOI} {ASIC} for Decoding of Polar Codes},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {7},
number = {4},
pages = {616--629},
year = {2017},
url = {https://doi.org/10.1109/JETCAS.2017.2745704},
doi = {10.1109/JETCAS.2017.2745704},
timestamp = {Thu, 25 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/GiardBMBTGFB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/RossiPLGGTCBPBC17,
author = {Davide Rossi and
Antonio Pullini and
Igor Loi and
Michael Gautschi and
Frank Kagan G{\"{u}}rkaynak and
Adam Teman and
Jeremy Constantin and
Andreas Burg and
Ivan Miro Panades and
Edith Beign{\'{e}} and
Fabien Clermidy and
Philippe Flatresse and
Luca Benini},
title = {Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster},
journal = {{IEEE} Micro},
volume = {37},
number = {5},
pages = {20--31},
year = {2017},
url = {https://doi.org/10.1109/MM.2017.3711645},
doi = {10.1109/MM.2017.3711645},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/RossiPLGGTCBPBC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/BonettiTFB17,
author = {Andrea Bonetti and
Adam Teman and
Philippe Flatresse and
Andreas Burg},
title = {Multipliers-Driven Perturbation of Coefficients for Low-Power Operation
in Reconfigurable {FIR} Filters},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {9},
pages = {2388--2400},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2698138},
doi = {10.1109/TCSI.2017.2698138},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/BonettiTFB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GroverVPDTGNPMB17,
author = {Anuj Grover and
G. S. Visweswaran and
Chittoor R. Parthasarathy and
Mohammad Daud and
David Turgis and
Bastien Giraud and
Jean{-}Philippe Noel and
Ivan Miro Panades and
Guillaume Moritz and
Edith Beign{\'{e}} and
Philippe Flatresse and
Promod Kumar and
Shamsi Azmi},
title = {A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved {SRAM} With 8 {T}
{SRAM} Cell and Data Dependent Write Assist in 28-nm {UTBB-FDSOI}
{CMOS}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {64-I},
number = {9},
pages = {2438--2447},
year = {2017},
url = {https://doi.org/10.1109/TCSI.2017.2705116},
doi = {10.1109/TCSI.2017.2705116},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GroverVPDTGNPMB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MauroRPFB17,
author = {Alfio Di Mauro and
Davide Rossi and
Antonio Pullini and
Philippe Flatresse and
Luca Benini},
title = {Temperature and process-aware performance monitoring and compensation
for an {ULP} multi-core cluster in 28nm {UTBB} {FD-SOI} technology},
booktitle = {27th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2017, Thessaloniki, Greece, September 25-27,
2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/PATMOS.2017.8106979},
doi = {10.1109/PATMOS.2017.8106979},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MauroRPFB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1708-09603,
author = {Pascal Giard and
Alexios Balatsoukas{-}Stimming and
Thomas Christoph M{\"{u}}ller and
Andrea Bonetti and
Claude Thibeault and
Warren J. Gross and
Philippe Flatresse and
Andreas Burg},
title = {PolarBear: {A} 28-nm {FD-SOI} {ASIC} for Decoding of Polar Codes},
journal = {CoRR},
volume = {abs/1708.09603},
year = {2017},
url = {http://arxiv.org/abs/1708.09603},
eprinttype = {arXiv},
eprint = {1708.09603},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1708-09603.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ZimmerLPKJKBBCL16,
author = {Brian Zimmer and
Yunsup Lee and
Alberto Puggelli and
Jaehwa Kwak and
Ruzica Jevtic and
Ben Keller and
Steven Bailey and
Milovan Blagojevic and
Pi{-}Feng Chiu and
Hanh{-}Phuc Le and
Po{-}Hung Chen and
Nicholas Sutardja and
Rimas Avizienis and
Andrew Waterman and
Brian C. Richards and
Philippe Flatresse and
Elad Alon and
Krste Asanovic and
Borivoje Nikolic},
title = {A {RISC-V} Vector Processor With Simultaneous-Switching Switched-Capacitor
{DC-DC} Converters in 28 nm {FDSOI}},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {4},
pages = {930--942},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2016.2519386},
doi = {10.1109/JSSC.2016.2519386},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ZimmerLPKJKBBCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coolchips/RossiPLGGTCBPBC16,
author = {Davide Rossi and
Antonio Pullini and
Igor Loi and
Michael Gautschi and
Frank Kagan G{\"{u}}rkaynak and
Adam Teman and
Jeremy Constantin and
Andreas Burg and
Ivan Miro Panades and
Edith Beign{\'{e}} and
Fabien Clermidy and
Fady Abouzeid and
Philippe Flatresse and
Luca Benini},
title = {193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator
for energy efficient parallel and sequential digital processing},
booktitle = {2016 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
XIX, Yokohama, Japan, April 20-22, 2016},
pages = {1--3},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/CoolChips.2016.7503670},
doi = {10.1109/COOLCHIPS.2016.7503670},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/coolchips/RossiPLGGTCBPBC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BlagojevicCKFVN16,
author = {Milovan Blagojevic and
Martin Cochet and
Ben Keller and
Philippe Flatresse and
Andrei Vladimirescu and
Borivoje Nikolic},
title = {A fast, flexible, positive and negative adaptive body-bias generator
in 28nm {FDSOI}},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573479},
doi = {10.1109/VLSIC.2016.7573479},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/BlagojevicCKFVN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BeigneVPWFABBBBCGGCNTT15,
author = {Edith Beign{\'{e}} and
Alexandre Valentian and
Ivan Miro Panades and
Robin Wilson and
Philippe Flatresse and
Fady Abouzeid and
Thomas Benoist and
Christian Bernard and
Sebastien Bernard and
Olivier Billoint and
Sylvain Clerc and
Bastien Giraud and
Anuj Grover and
Julien Le Coz and
Jean{-}Philippe Noel and
Olivier Thomas and
Yvain Thonnart},
title = {A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits {VLIW} {DSP} Embedding
{F} {MAX} Tracking},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {125--136},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2369503},
doi = {10.1109/JSSC.2014.2369503},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BeigneVPWFABBBBCGGCNTT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/Rossi0MPLGTCFB15,
author = {Davide Rossi and
Francesco Conti and
Andrea Marongiu and
Antonio Pullini and
Igor Loi and
Michael Gautschi and
Giuseppe Tagliavini and
Alessandro Capotondi and
Philippe Flatresse and
Luca Benini},
title = {{PULP:} {A} parallel ultra low power platform for next generation
IoT applications},
booktitle = {2015 {IEEE} Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August
22-25, 2015},
pages = {1--39},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477325},
doi = {10.1109/HOTCHIPS.2015.7477325},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/Rossi0MPLGTCFB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZimmerLPKJKBBCL15,
author = {Brian Zimmer and
Yunsup Lee and
Alberto Puggelli and
Jaehwa Kwak and
Ruzica Jevtic and
Ben Keller and
Stevo Bailey and
Milovan Blagojevic and
Pi{-}Feng Chiu and
Hanh{-}Phuc Le and
Po{-}Hung Chen and
Nicholas Sutardja and
Rimas Avizienis and
Andrew Waterman and
Brian C. Richards and
Philippe Flatresse and
Elad Alon and
Krste Asanovic and
Borivoje Nikolic},
title = {A {RISC-V} vector processor with tightly-integrated switched-capacitor
{DC-DC} converters in 28nm {FDSOI}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
2015},
pages = {316},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSIC.2015.7231305},
doi = {10.1109/VLSIC.2015.7231305},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ZimmerLPKJKBBCL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JacquetHFWACGLRCGMUDACNMCVM14,
author = {David Jacquet and
Frederic Hasbani and
Philippe Flatresse and
Robin Wilson and
Franck Arnaud and
Giorgio Cesana and
Thierry Di Gilio and
Christophe Lecocq and
Tanmoy Roy and
Amit Chhabra and
Chiranjeev Grover and
Olivier Minez and
Jacky Uginet and
Guy Durieu and
Cyril Adobati and
Davide Casalotto and
Frederic Nyer and
Patrick Menut and
Andreia Cathelin and
Indavong Vongsavady and
Philippe Magarshack},
title = {A 3 GHz Dual Core Processor {ARM} Cortex {TM} -A9 in 28 nm {UTBB}
{FD-SOI} {CMOS} With Ultra-Wide Voltage Range and Energy Efficiency
Optimization},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {4},
pages = {812--826},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2295977},
doi = {10.1109/JSSC.2013.2295977},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JacquetHFWACGLRCGMUDACNMCVM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/Flatresse14,
author = {Philippe Flatresse},
editor = {Yuan Xie and
Tanay Karnik and
Muhammad M. Khellah and
Renu Mehra},
title = {Process and design solutions for exploiting {FD-SOI} technology towards
energy efficient SOCs},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'14,
La Jolla, CA, {USA} - August 11 - 13, 2014},
pages = {127--130},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2627369.2631640},
doi = {10.1145/2627369.2631640},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/Flatresse14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WilsonBFVABBBBC14,
author = {Robin Wilson and
Edith Beign{\'{e}} and
Philippe Flatresse and
Alexandre Valentian and
Fady Abouzeid and
Thomas Benoist and
Christian Bernard and
Sebastien Bernard and
Olivier Billoint and
Sylvain Clerc and
Bastien Giraud and
Anuj Grover and
Julien Le Coz and
Ivan Miro Panades and
Jean{-}Philippe No{\"{e}}l and
Bertrand Pelloux{-}Prayer and
Philippe Roche and
Olivier Thomas and
Yvain Thonnart and
David Turgis and
Fabien Clermidy and
Philippe Magarshack},
title = {27.1 {A} 460MHz at 397mV, 2.6GHz at 1.3V, 32b {VLIW} DSP, embedding
{FMAX} tracking},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {452--453},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757509},
doi = {10.1109/ISSCC.2014.6757509},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WilsonBFVABBBBC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WeinerBSBFN14,
author = {Matthew Weiner and
Milovan Blagojevic and
Sergey Skotnikov and
Andreas Burg and
Philippe Flatresse and
Borivoje Nikolic},
title = {27.7 {A} scalable 1.5-to-6Gb/s 6.2-to-38.1mW {LDPC} decoder for 60GHz
wireless networks in 28nm {UTBB} {FDSOI}},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {464--465},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757515},
doi = {10.1109/ISSCC.2014.6757515},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WeinerBSBFN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BeigneVGTBTBMBMFNAPGCRCEW13,
author = {Edith Beign{\'{e}} and
Alexandre Valentian and
Bastien Giraud and
Olivier Thomas and
Thomas Benoist and
Yvain Thonnart and
Serge Bernard and
Guillaume Moritz and
Olivier Billoint and
Y. Maneglia and
Philippe Flatresse and
Jean{-}Philippe Noel and
Fady Abouzeid and
Bertrand Pelloux{-}Prayer and
Anuj Grover and
Sylvain Clerc and
Philippe Roche and
Julien Le Coz and
Sylvain Engels and
Robin Wilson},
editor = {Enrico Macii},
title = {Ultra-wide voltage range designs in fully-depleted silicon-on-insulator
FETs},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {613--618},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.135},
doi = {10.7873/DATE.2013.135},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BeigneVGTBTBMBMFNAPGCRCEW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MagarshackFC13,
author = {Philippe Magarshack and
Philippe Flatresse and
Giorgio Cesana},
editor = {Enrico Macii},
title = {{UTBB} {FD-SOI:} a process/design symbiosis for breakthrough energy-efficiency},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {952--957},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.200},
doi = {10.7873/DATE.2013.200},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MagarshackFC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AkyelCTPKFLG13,
author = {Kaya Can Akyel and
Lorenzo Ciampolini and
Olivier Thomas and
Bertrand Pelloux{-}Prayer and
Shishir Kumar and
Philippe Flatresse and
Christophe Lecocq and
G{\'{e}}rard Ghibaudo},
title = {Multiple-pulse dynamic stability and failure analysis of low-voltage
6T-SRAM bitcells in 28nm {UTBB-FDSOI}},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {1452--1455},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572130},
doi = {10.1109/ISCAS.2013.6572130},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AkyelCTPKFLG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FlatresseGNPGAAPCTECWU13,
author = {Philippe Flatresse and
Bastien Giraud and
Jean{-}Philippe Noel and
Bertrand Pelloux{-}Prayer and
Fabien Giner and
Deepak{-}Kumar Arora and
Franck Arnaud and
Nicolas Planes and
Julien Le Coz and
Olivier Thomas and
Sylvain Engels and
Giorgio Cesana and
Robin Wilson and
Pascal Urard},
title = {Ultra-wide body-bias range {LDPC} decoder in 28nm {UTBB} {FDSOI} technology},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {424--425},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487798},
doi = {10.1109/ISSCC.2013.6487798},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FlatresseGNPGAAPCTECWU13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Pelloux-PrayerVGTNFB13,
author = {Bertrand Pelloux{-}Prayer and
Alexandre Valentian and
Bastien Giraud and
Yvain Thonnart and
Jean{-}Philippe Noel and
Philippe Flatresse and
Edith Beign{\'{e}}},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Fine grain multi-VT co-integration methodology in {UTBB} {FD-SOI}
technology},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {168--173},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673270},
doi = {10.1109/VLSI-SOC.2013.6673270},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Pelloux-PrayerVGTNFB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/JoshiLFDJBG12,
author = {Smriti Joshi and
Anne Lombardot and
Philippe Flatresse and
Carmelo D'Agostino and
Andre Juge and
Edith Beign{\'{e}} and
St{\'{e}}phane Girard},
title = {Statistical Estimation of Dominant Physical Parameters for Leakage
Variability in 32 Nanometer CMOS, Under Supply Voltage Variations},
journal = {J. Low Power Electron.},
volume = {8},
number = {1},
pages = {113--124},
year = {2012},
url = {https://doi.org/10.1166/jolpe.2012.1166},
doi = {10.1166/JOLPE.2012.1166},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jolpe/JoshiLFDJBG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/AmadorHPCCREFA11,
author = {N. Ruiz Amador and
Vincent Huard and
E. Pion and
Florian Cacho and
Damien Croain and
V. Robert and
Sylvain Engels and
Philippe Flatresse and
Lorena Anghel},
editor = {Rakesh Patel and
Tom Andre and
Aurangzeb Khan},
title = {Bottom-up digital system-level reliability modeling},
booktitle = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
Jose, CA, USA, Sept. 19-21, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CICC.2011.6055343},
doi = {10.1109/CICC.2011.6055343},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/AmadorHPCCREFA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/CozFEVBRCU11,
author = {Julien Le Coz and
Philippe Flatresse and
Sylvain Engels and
Alexandre Valentian and
Marc Belleville and
Christine Raynaud and
Damien Croain and
Pascal Urard},
title = {Comparison of 65nm {LP} bulk and {LP} {PD-SOI} with adaptive power
gate body bias for an {LDPC} codec},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {336--337},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746343},
doi = {10.1109/ISSCC.2011.5746343},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/CozFEVBRCU11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/EntringerFGAN06,
author = {Christophe Entringer and
Philippe Flatresse and
Philippe Galy and
Florence Aza{\"{\i}}s and
Pascal Nouet},
title = {Electro-thermal short pulsed simulation for {SOI} technology},
journal = {Microelectron. Reliab.},
volume = {46},
number = {9-11},
pages = {1482--1485},
year = {2006},
url = {https://doi.org/10.1016/j.microrel.2006.07.015},
doi = {10.1016/J.MICROREL.2006.07.015},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/EntringerFGAN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtdt/CasuF02,
author = {Mario R. Casu and
Philippe Flatresse},
title = {Converting an Embedded Low-Power {SRAM} from Bulk to {PD-SOI}},
booktitle = {10th {IEEE} International Workshop on Memory Technology, Design, and
Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
pages = {163--167},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/MTDT.2002.1029780},
doi = {10.1109/MTDT.2002.1029780},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtdt/CasuF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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