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BibTeX records: Sandeep Kumar Goel
@inproceedings{DBLP:conf/itc/ChandraKPTGSNTA23, author = {Anshuman Chandra and Moiz Khan and Ankita Patidar and Fumiaki Takashima and Sandeep Kumar Goel and Bharath Shankaranarayanan and Vuong Nguyen and Vistrita Tyagi and Manish Arora}, title = {A Case Study on {IEEE} 1838 Compliant Multi-Die 3DIC {DFT} Implementation}, booktitle = {{IEEE} International Test Conference, {ITC} 2023, Anaheim, CA, USA, October 7-15, 2023}, pages = {11--20}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.1109/ITC51656.2023.00011}, doi = {10.1109/ITC51656.2023.00011}, timestamp = {Tue, 09 Jan 2024 17:03:11 +0100}, biburl = {https://dblp.org/rec/conf/itc/ChandraKPTGSNTA23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/Goel22, author = {Sandeep Kumar Goel}, editor = {Laleh Behjat and Stephen Yang}, title = {Challenges and Solutions for 3D Fabric: {A} Foundry Perspective}, booktitle = {{ISPD} 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27 - 30, 2022}, pages = {93}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3505170.3511045}, doi = {10.1145/3505170.3511045}, timestamp = {Thu, 14 Apr 2022 14:53:52 +0200}, biburl = {https://dblp.org/rec/conf/ispd/Goel22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/GoelPL22, author = {Sandeep Kumar Goel and Sandeep Pendharkar and Chunsheng Liu}, title = {Innovative Practices Track: Test of 3D ICs {\&} Chiplets}, booktitle = {40th {IEEE} {VLSI} Test Symposium, {VTS} 2022, San Diego, CA, USA, April 25-27, 2022}, pages = {1}, publisher = {{IEEE}}, year = {2022}, url = {https://doi.org/10.1109/VTS52500.2021.9794242}, doi = {10.1109/VTS52500.2021.9794242}, timestamp = {Wed, 22 Jun 2022 15:24:48 +0200}, biburl = {https://dblp.org/rec/conf/vts/GoelPL22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/LinHTTHCHHCGFRL20, author = {Mu{-}Shan Lin and Tze{-}Chiang Huang and Chien{-}Chun Tsai and King{-}Ho Tam and Kenny Cheng{-}Hsiang Hsieh and Ching{-}Fang Chen and Wen{-}Hung Huang and Chi{-}Wei Hu and Yu{-}Chi Chen and Sandeep Kumar Goel and Chin{-}Ming Fu and Stefan Rusu and Chao{-}Chieh Li and Sheng{-}Yao Yang and Mei Wong and Shu{-}Chun Yang and Frank Lee}, title = {A 7-nm 4-GHz Arm{\({^1}\)}-Core-Based CoWoS{\({^1}\)} Chiplet Design for High-Performance Computing}, journal = {{IEEE} J. Solid State Circuits}, volume = {55}, number = {4}, pages = {956--966}, year = {2020}, url = {https://doi.org/10.1109/JSSC.2019.2960207}, doi = {10.1109/JSSC.2019.2960207}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/LinHTTHCHHCGFRL20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsic/LinHTTHCHHCGFRL19, author = {Mu{-}Shan Lin and Tze{-}Chiang Huang and Chien{-}Chun Tsai and King{-}Ho Tam and Kenny Cheng{-}Hsiang Hsieh and Tom Chen and Wen{-}Hung Huang and Jack Hu and Yu{-}Chi Chen and Sandeep Kumar Goel and Chin{-}Ming Fu and Stefan Rusu and Chao{-}Chieh Li and Sheng{-}Yao Yang and Mei Wong and Shu{-}Chun Yang and Frank Lee}, title = {A 7nm 4GHz Arm\({}^{\mbox{{\textregistered}}}\)-core-based CoWoS\({}^{\mbox{{\textregistered}}}\) Chiplet Design for High Performance Computing}, booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019}, pages = {28}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.23919/VLSIC.2019.8778161}, doi = {10.23919/VLSIC.2019.8778161}, timestamp = {Thu, 02 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/vlsic/LinHTTHCHHCGFRL19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/IngelssonGLM15, author = {Urban Ingelsson and Sandeep Kumar Goel and Erik Larsson and Erik Jan Marinissen}, title = {Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption}, journal = {{IEEE} Trans. Computers}, volume = {64}, number = {12}, pages = {3335--3347}, year = {2015}, url = {https://doi.org/10.1109/TC.2015.2409840}, doi = {10.1109/TC.2015.2409840}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tc/IngelssonGLM15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/LiGLC15, author = {Zipeng Li and Sandeep Kumar Goel and Frank Lee and Krishnendu Chakrabarty}, title = {Efficient observation-point insertion for diagnosability enhancement in digital circuits}, booktitle = {2015 {IEEE} International Test Conference, {ITC} 2015, Anaheim, CA, USA, October 6-8, 2015}, pages = {1--10}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/TEST.2015.7342380}, doi = {10.1109/TEST.2015.7342380}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/LiGLC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChiMGW14, author = {Chun{-}Chuan Chi and Erik Jan Marinissen and Sandeep Kumar Goel and Cheng{-}Wen Wu}, title = {Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {22}, number = {11}, pages = {2388--2401}, year = {2014}, url = {https://doi.org/10.1109/TVLSI.2013.2293192}, doi = {10.1109/TVLSI.2013.2293192}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ChiMGW14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsi-dat/GoelWAML14, author = {Sandeep Kumar Goel and Min{-}Jer Wang and Saman Adham and Ashok Mehta and Frank Lee}, title = {Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS\({}^{\mbox{TM}}\)/3D ICs}, booktitle = {Technical Papers of 2014 International Symposium on {VLSI} Design, Automation and Test, {VLSI-DAT} 2014, Hsinchu, Taiwan, April 28-30, 2014}, pages = {1--4}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/VLSI-DAT.2014.6834918}, doi = {10.1109/VLSI-DAT.2014.6834918}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/vlsi-dat/GoelWAML14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:books/crc/14/GoelD14, author = {Sandeep Kumar Goel and Narendra Devta{-}Prasanna}, editor = {Sandeep Kumar Goel and Krishnendu Chakrabarty}, title = {Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects}, booktitle = {Testing for Small-Delay Defects in Nanoscale {CMOS} Integrated Circuits}, pages = {147--160}, publisher = {{CRC} Press}, year = {2014}, timestamp = {Fri, 05 Jun 2020 14:24:01 +0200}, biburl = {https://dblp.org/rec/books/crc/14/GoelD14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:books/crc/14/GoelC14, author = {Sandeep Kumar Goel and Krishnendu Chakrabarty}, editor = {Sandeep Kumar Goel and Krishnendu Chakrabarty}, title = {Circuit Topology-Based Test Pattern Generation for Small-Delay Defects}, booktitle = {Testing for Small-Delay Defects in Nanoscale {CMOS} Integrated Circuits}, pages = {161--184}, publisher = {{CRC} Press}, year = {2014}, timestamp = {Fri, 05 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/books/crc/14/GoelC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:books/crc/14/Devta-PrasannaG14, author = {Narendra Devta{-}Prasanna and Sandeep Kumar Goel}, editor = {Sandeep Kumar Goel and Krishnendu Chakrabarty}, title = {Small-Delay Defect Coverage Metrics}, booktitle = {Testing for Small-Delay Defects in Nanoscale {CMOS} Integrated Circuits}, pages = {185--210}, publisher = {{CRC} Press}, year = {2014}, timestamp = {Fri, 05 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/books/crc/14/Devta-PrasannaG14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@book{DBLP:books/crc/14/GC2014, editor = {Sandeep Kumar Goel and Krishnendu Chakrabarty}, title = {Testing for Small-Delay Defects in Nanoscale {CMOS} Integrated Circuits}, publisher = {{CRC} Press}, year = {2014}, url = {http://www.crcpress.com/product/isbn/9781439829417}, isbn = {978-1-439-82941-7}, timestamp = {Fri, 05 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/books/crc/14/GC2014.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/GoelAWCHMLCKVMSCLCK13, author = {Sandeep Kumar Goel and Saman Adham and Min{-}Jer Wang and Ji{-}Jan Chen and Tze{-}Chiang Huang and Ashok Mehta and Frank Lee and Vivek Chickermane and Brion L. Keller and Thomas Valind and Subhasish Mukherjee and Navdeep Sood and Jeongho Cho and Hayden Hyungdong Lee and Jungi Choi and Sangdoo Kim}, title = {Test and debug strategy for {TSMC} CoWoS{\texttrademark} stacking process based heterogeneous 3D {IC:} {A} silicon case study}, booktitle = {2013 {IEEE} International Test Conference, {ITC} 2013, Anaheim, CA, USA, September 6-13, 2013}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2013}, url = {https://doi.org/10.1109/TEST.2013.6651893}, doi = {10.1109/TEST.2013.6651893}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/GoelAWCHMLCKVMSCLCK13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/MarinissenVGHRMB12, author = {Erik Jan Marinissen and Gilbert Vandling and Sandeep Kumar Goel and Friedrich Hapke and Jason Rivers and Nikolaus Mittermaier and Swapnil Bahl}, editor = {Wolfgang Rosenstiel and Lothar Thiele}, title = {{EDA} solutions to new-defect detection in advanced process technologies}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, pages = {123--128}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/DATE.2012.6176444}, doi = {10.1109/DATE.2012.6176444}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/MarinissenVGHRMB12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/Goel12, author = {Sandeep Kumar Goel}, editor = {Alan J. Hu}, title = {Test challenges in designing complex 3D chips: What in on the horizon for {EDA} industry?: Designer track}, booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012}, pages = {273}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2429384.2429438}, doi = {10.1145/2429384.2429438}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/Goel12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/DeutschKCMSGCMLM12, author = {Sergej Deutsch and Brion L. Keller and Vivek Chickermane and Subhasish Mukherjee and Navdeep Sood and Sandeep Kumar Goel and Ji{-}Jan Chen and Ashok Mehta and Frank Lee and Erik Jan Marinissen}, title = {DfT architecture and {ATPG} for Interconnect tests of {JEDEC} Wide-I/O memory-on-logic die stacks}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/TEST.2012.6401569}, doi = {10.1109/TEST.2012.6401569}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/DeutschKCMSGCMLM12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/NoiaCGMV11, author = {Brandon Noia and Krishnendu Chakrabarty and Sandeep Kumar Goel and Erik Jan Marinissen and Jouke Verbree}, title = {Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {11}, pages = {1705--1718}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2011.2160177}, doi = {10.1109/TCAD.2011.2160177}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/NoiaCGMV11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/DeutschCKMKMG11, author = {Sergej Deutsch and Vivek Chickermane and Brion L. Keller and Subhasish Mukherjee and Mario Konijnenburg and Erik Jan Marinissen and Sandeep Kumar Goel}, title = {Automation of 3D-DfT Insertion}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, pages = {395--400}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ATS.2011.58}, doi = {10.1109/ATS.2011.58}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/DeutschCKMKMG11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/ChiMGW11, author = {Chun{-}Chuan Chi and Erik Jan Marinissen and Sandeep Kumar Goel and Cheng{-}Wen Wu}, title = {Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, pages = {451--456}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ATS.2011.36}, doi = {10.1109/ATS.2011.36}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/ChiMGW11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/ChiMGW11, author = {Chun{-}Chuan Chi and Erik Jan Marinissen and Sandeep Kumar Goel and Cheng{-}Wen Wu}, title = {DfT Architecture for 3D-SICs with Multiple Towers}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, pages = {51--56}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ETS.2011.52}, doi = {10.1109/ETS.2011.52}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/ChiMGW11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/ChiMGW11, author = {Chun{-}Chuan Chi and Erik Jan Marinissen and Sandeep Kumar Goel and Cheng{-}Wen Wu}, editor = {Bill Eklow and R. D. (Shawn) Blanton}, title = {Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base}, booktitle = {2011 {IEEE} International Test Conference, {ITC} 2011, Anaheim, CA, USA, September 20-22, 2011}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/TEST.2011.6139181}, doi = {10.1109/TEST.2011.6139181}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/ChiMGW11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/GoelCYPT10, author = {Sandeep Kumar Goel and Krishnendu Chakrabarty and Mahmut Yilmaz and Ke Peng and Mohammad Tehranipoor}, title = {Circuit Topology-Based Test Pattern Generation for Small-Delay Defects}, booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4 December 2010, Shanghai, China}, pages = {307--312}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/ATS.2010.59}, doi = {10.1109/ATS.2010.59}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/GoelCYPT10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/NoiaGCMV10, author = {Brandon Noia and Sandeep Kumar Goel and Krishnendu Chakrabarty and Erik Jan Marinissen and Jouke Verbree}, title = {Test-architecture optimization for TSV-based 3D stacked ICs}, booktitle = {15th European Test Symposium, {ETS} 2010, Prague, Czech Republic, May 24-28, 2010}, pages = {24--29}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/ETSYM.2010.5512787}, doi = {10.1109/ETSYM.2010.5512787}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/NoiaGCMV10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/GoelMSC09, author = {Sandeep Kumar Goel and Erik Jan Marinissen and Anuja Sehgal and Krishnendu Chakrabarty}, title = {Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling}, journal = {{IEEE} Trans. Computers}, volume = {58}, number = {3}, pages = {409--423}, year = {2009}, url = {https://doi.org/10.1109/TC.2008.169}, doi = {10.1109/TC.2008.169}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tc/GoelMSC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/Devta-PrasannaGGWK09, author = {Narendra Devta{-}Prasanna and Sandeep Kumar Goel and Arun Gunda and Mark Ward and P. Krishnamurthy}, editor = {Gordon W. Roberts and Bill Eklow}, title = {Accurate measurement of small delay defect coverage of test patterns}, booktitle = {2009 {IEEE} International Test Conference, {ITC} 2009, Austin, TX, USA, November 1-6, 2009}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/TEST.2009.5355644}, doi = {10.1109/TEST.2009.5355644}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/Devta-PrasannaGGWK09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/GoelDW09, author = {Sandeep Kumar Goel and Narendra Devta{-}Prasanna and Mark Ward}, editor = {Gordon W. Roberts and Bill Eklow}, title = {Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: {A} simulation and silicon study}, booktitle = {2009 {IEEE} International Test Conference, {ITC} 2009, Austin, TX, USA, November 1-6, 2009}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/TEST.2009.5355762}, doi = {10.1109/TEST.2009.5355762}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/GoelDW09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/GoelDT09, author = {Sandeep Kumar Goel and Narendra Devta{-}Prasanna and Ritesh P. Turakhia}, title = {Effective and Efficient Test Pattern Generation for Small Delay Defect}, booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa Cruz, California, {USA}}, pages = {111--116}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/VTS.2009.28}, doi = {10.1109/VTS.2009.28}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vts/GoelDT09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/TurakhiaWGB09, author = {Ritesh P. Turakhia and Mark Ward and Sandeep Kumar Goel and Brady Benware}, title = {Bridging {DFM} Analysis and Volume Diagnostics for Yield Learning - {A} Case Study}, booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa Cruz, California, {USA}}, pages = {167--172}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/VTS.2009.37}, doi = {10.1109/VTS.2009.37}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vts/TurakhiaWGB09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/iet-cdt/GoelMG07, author = {Sandeep Kumar Goel and Maurice Meijer and Jos{\'{e}} Pineda de Gyvez}, title = {Efficient testing and diagnosis of faulty power switches in SOCs}, journal = {{IET} Comput. Digit. Tech.}, volume = {1}, number = {3}, pages = {230--236}, year = {2007}, url = {https://doi.org/10.1049/iet-cdt:20060147}, doi = {10.1049/IET-CDT:20060147}, timestamp = {Tue, 14 Jul 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/iet-cdt/GoelMG07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-0710-4687, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips}, journal = {CoRR}, volume = {abs/0710.4687}, year = {2007}, url = {http://arxiv.org/abs/0710.4687}, eprinttype = {arXiv}, eprint = {0710.4687}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-0710-4687.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/VrankenGGSH06, author = {Harald P. E. Vranken and Sandeep Kumar Goel and Andreas Glowatz and J{\"{u}}rgen Schl{\"{o}}ffel and Friedrich Hapke}, editor = {Ellen Sentovich}, title = {Fault detection and diagnosis with parity trees for space compaction of test responses}, booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006, San Francisco, CA, USA, July 24-28, 2006}, pages = {1095--1098}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1146909.1147185}, doi = {10.1145/1146909.1147185}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/VrankenGGSH06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/SehgalGMC06, author = {Anuja Sehgal and Sandeep Kumar Goel and Erik Jan Marinissen and Krishnendu Chakrabarty}, editor = {Georges G. E. Gielen}, title = {Hierarchy-aware and area-efficient test infrastructure design for core-based system chips}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2006, Munich, Germany, March 6-10, 2006}, pages = {285--290}, publisher = {European Design and Automation Association, Leuven, Belgium}, year = {2006}, url = {https://doi.org/10.1109/DATE.2006.244140}, doi = {10.1109/DATE.2006.244140}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/SehgalGMC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/GoelMG06, author = {Sandeep Kumar Goel and Maurice Meijer and Jos{\'{e}} Pineda de Gyvez}, title = {Testing and Diagnosis of Power Switches in SOCs}, booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24, 2006}, pages = {145--150}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ETS.2006.47}, doi = {10.1109/ETS.2006.47}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/GoelMG06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/GoelM05, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips}, booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2005), 7-11 March 2005, Munich, Germany}, pages = {44--49}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/DATE.2005.231}, doi = {10.1109/DATE.2005.231}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/GoelM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/IngelssonGLM05, author = {Urban Ingelsson and Sandeep Kumar Goel and Erik Larsson and Erik Jan Marinissen}, title = {Test scheduling for modular SOCs in an abort-on-fail environment}, booktitle = {10th European Test Symposium, {ETS} 2005, Tallinn, Estonia, May 22-25, 2005}, pages = {8--13}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ETS.2005.38}, doi = {10.1109/ETS.2005.38}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/IngelssonGLM05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/VermeulenUG04, author = {Bart Vermeulen and Mohammad Zalfany Urfianto and Sandeep Kumar Goel}, editor = {Sharad Malik and Limor Fix and Andrew B. Kahng}, title = {Automatic generation of breakpoint hardware for silicon debug}, booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004, San Diego, CA, USA, June 7-11, 2004}, pages = {514--517}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/996566.996708}, doi = {10.1145/996566.996708}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/VermeulenUG04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/GoelCMNO04, author = {Sandeep Kumar Goel and Kuoshu Chiu and Erik Jan Marinissen and Toan Nguyen and Steven Oostdijk}, title = {Test Infrastructure Design for the Nexperia? Home Platform {PNX8550} System Chip}, booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2004), 16-20 February 2004, Paris, France}, pages = {108--113}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/DATE.2004.1269215}, doi = {10.1109/DATE.2004.1269215}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/GoelCMNO04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/KrundelGMFR04, author = {Ludovic A. Krundel and Sandeep Kumar Goel and Erik Jan Marinissen and Marie{-}Lise Flottes and Bruno Rouzeyre}, title = {User-constrained test architecture design for modular {SOC} testing}, booktitle = {9th European Test Symposium, {ETS} 2004, Ajaccio, France, May 23-26, 2004}, pages = {80--85}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ETSYM.2004.1347611}, doi = {10.1109/ETSYM.2004.1347611}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/KrundelGMFR04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/SehgalGMC04, author = {Anuja Sehgal and Sandeep Kumar Goel and Erik Jan Marinissen and Krishnendu Chakrabarty}, title = {{IEEE} P1500-Compliant Test Wrapper Design for Hierarchical Cores}, booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October 26-28, 2004, Charlotte, NC, {USA}}, pages = {1203--1212}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/TEST.2004.1387393}, doi = {10.1109/TEST.2004.1387393}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/SehgalGMC04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/et/GoelV03, author = {Sandeep Kumar Goel and Bart Vermeulen}, title = {Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips}, journal = {J. Electron. Test.}, volume = {19}, number = {4}, pages = {407--416}, year = {2003}, url = {https://doi.org/10.1023/A:1024639925852}, doi = {10.1023/A:1024639925852}, timestamp = {Fri, 11 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/et/GoelV03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/et/GoelM03, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips}, journal = {J. Electron. Test.}, volume = {19}, number = {4}, pages = {425--435}, year = {2003}, url = {https://doi.org/10.1023/A:1024644026761}, doi = {10.1023/A:1024644026761}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/et/GoelM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/GoelM03, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {{SOC} test architecture design for efficient utilization of test bandwidth}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {8}, number = {4}, pages = {399--429}, year = {2003}, url = {https://doi.org/10.1145/944027.944029}, doi = {10.1145/944027.944029}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/GoelM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/GoelM03, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {Layout-Driven {SOC} Test Architecture Design for Test Time and Wire Length Minimization}, booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2003), 3-7 March 2003, Munich, Germany}, pages = {10738--10741}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10171}, doi = {10.1109/DATE.2003.10171}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/GoelM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/GoelM03, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {Control-aware test architecture design for modular {SOC} testing}, booktitle = {8th European Test Workshop, {ETW} 2003, Maastricht, The Netherlands, May 25-28, 2003}, pages = {57--62}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/ETW.2003.1231669}, doi = {10.1109/ETW.2003.1231669}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/GoelM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/dt/VermeulenG02, author = {Bart Vermeulen and Sandeep Kumar Goel}, title = {Design for Debug: Catching Design Errors in Digital Chips}, journal = {{IEEE} Des. Test Comput.}, volume = {19}, number = {3}, pages = {37--45}, year = {2002}, url = {https://doi.org/10.1109/MDT.2002.1003792}, doi = {10.1109/MDT.2002.1003792}, timestamp = {Sun, 17 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/dt/VermeulenG02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/GoelM02, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {A novel test time reduction algorithm for test architecture design for core-based system chips}, booktitle = {7th European Test Workshop, {ETW} 2002, Corfu, Greece, May 26-29, 2002}, pages = {7--12}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/ETW.2002.1029633}, doi = {10.1109/ETW.2002.1029633}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ets/GoelM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/GoelV02, author = {Sandeep Kumar Goel and Bart Vermeulen}, title = {Data invalidation analysis for scan-based debug on multiple-clock system chips}, booktitle = {7th European Test Workshop, {ETW} 2002, Corfu, Greece, May 26-29, 2002}, pages = {61--66}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/ETW.2002.1029640}, doi = {10.1109/ETW.2002.1029640}, timestamp = {Tue, 28 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ets/GoelV02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/GoelM02, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {Effective and Efficient Test Architecture Design for SOCs}, booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002}, pages = {529--538}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/TEST.2002.1041803}, doi = {10.1109/TEST.2002.1041803}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/GoelM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/VermeulenWG02, author = {Bart Vermeulen and Tom Waayers and Sandeep Kumar Goel}, title = {Core-Based Scan Architecture for Silicon Debug}, booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002}, pages = {638--647}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/TEST.2002.1041815}, doi = {10.1109/TEST.2002.1041815}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/VermeulenWG02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/GoelV02, author = {Sandeep Kumar Goel and Bart Vermeulen}, title = {Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips}, booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002}, pages = {1103--1110}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/TEST.2002.1041867}, doi = {10.1109/TEST.2002.1041867}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/GoelV02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/IyengarGMC02, author = {Vikram Iyengar and Sandeep Kumar Goel and Erik Jan Marinissen and Krishnendu Chakrabarty}, title = {Test Resource Optimization for Multi-Site Testing of SOCs Under {ATE} Memory Depth Constraints}, booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002}, pages = {1159--1168}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/TEST.2002.1041874}, doi = {10.1109/TEST.2002.1041874}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/IyengarGMC02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vts/GoelM02, author = {Sandeep Kumar Goel and Erik Jan Marinissen}, title = {Cluster-Based Test Architecture Design for System-on-Chip}, booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}}, pages = {259--264}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/VTS.2002.1011147}, doi = {10.1109/VTS.2002.1011147}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vts/GoelM02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/ZorianMLG00, author = {Yervant Zorian and Erik Jan Marinissen and Maurice Lousberg and Sandeep Kumar Goel}, title = {Wrapper design for embedded core test}, booktitle = {Proceedings {IEEE} International Test Conference 2000, Atlantic City, NJ, USA, October 2000}, pages = {911--920}, publisher = {{IEEE} Computer Society}, year = {2000}, url = {https://doi.org/10.1109/TEST.2000.894302}, doi = {10.1109/TEST.2000.894302}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/ZorianMLG00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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