BibTeX records: Kazushige Kanda

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@article{DBLP:journals/jssc/YuhLLOHAJADBTAR23,
  author       = {Jonghak Yuh and
                  Yen{-}Lung Jason Li and
                  Heguang Li and
                  Yoshihiro Oyama and
                  Cynthia Hsu and
                  Pradeep Anantula and
                  Gwang Yeong Stanley Jeong and
                  Anirudh Amarnath and
                  Siddhesh Darne and
                  Sneha Bhatia and
                  Tianyu Tang and
                  Aditya Arya and
                  Naman Rastogi and
                  Naoki Ookuma and
                  Hiroyuki Mizukoshi and
                  Alex Yap and
                  Demin Wang and
                  Steve Kim and
                  Yonggang Wu and
                  Min Peng and
                  Jason Lu and
                  Tommy Ip and
                  Seema Malhotra and
                  Taekeun Han and
                  Masatoshi Okumura and
                  Jiwen Liu and
                  Jeongduk John Sohn and
                  Hardwell Chibvongodze and
                  Muralikrishna Balaga and
                  Akihiro Matsuda and
                  Chen Chen and
                  Indra K. V and
                  V. S. N. K. Chaitanya G. and
                  Venky Ramachandra and
                  Yosuke Kato and
                  Ravi Kumar and
                  Huijuan Wang and
                  Farookh Moogat and
                  In{-}Soo Yoon and
                  Kazushige Kanda and
                  Takahiro Shimizu and
                  Noboru Shibata and
                  Kosuke Yanagidaira and
                  Takuyo Kodama and
                  Ryo Fukuda and
                  Yasuhiro Hirashima and
                  Mitsuhiro Abe},
  title        = {A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s {IO}
                  Interface},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {58},
  number       = {1},
  pages        = {316--328},
  year         = {2023},
  url          = {https://doi.org/10.1109/JSSC.2022.3193326},
  doi          = {10.1109/JSSC.2022.3193326},
  timestamp    = {Fri, 15 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/YuhLLOHAJADBTAR23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Yuh0LOHAJADBTAR22,
  author       = {Jong Yuh and
                  Jason Li and
                  Heguang Li and
                  Yoshihiro Oyama and
                  Cynthia Hsu and
                  Pradeep Anantula and
                  Stanley Jeong and
                  Anirudh Amarnath and
                  Siddhesh Darne and
                  Sneha Bhatia and
                  Tianyu Tang and
                  Aditya Arya and
                  Naman Rastogi and
                  Naoki Ookuma and
                  Hiroyuki Mizukoshi and
                  Alex Yap and
                  Demin Wang and
                  Steve Kim and
                  Yonggang Wu and
                  Min Peng and
                  Jason Lu and
                  Tommy Ip and
                  Seema Malhotra and
                  David Han and
                  Masatoshi Okumura and
                  Jiwen Liu and
                  John Sohn and
                  Hardwell Chibvongodze and
                  Muralikrishna Balaga and
                  Aki Matsuda and
                  Chakshu Puri and
                  Chen Chen and
                  Indra K. V and
                  Chaitanya G and
                  Venky Ramachandra and
                  Yosuke Kato and
                  Ravi Kumar and
                  Huijuan Wang and
                  Farookh Moogat and
                  In{-}Soo Yoon and
                  Kazushige Kanda and
                  Takahiro Shimizu and
                  Noboru Shibata and
                  Takashi Shigeoka and
                  Kosuke Yanagidaira and
                  Takuyo Kodama and
                  Ryo Fukuda and
                  Yasuhiro Hirashima and
                  Mitsuhiro Abe},
  title        = {A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s {I/O}
                  Speed Interface},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
                  San Francisco, CA, USA, February 20-26, 2022},
  pages        = {130--132},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ISSCC42614.2022.9731110},
  doi          = {10.1109/ISSCC42614.2022.9731110},
  timestamp    = {Fri, 15 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/Yuh0LOHAJADBTAR22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ShibataKSSYHDSN20,
  author       = {Noboru Shibata and
                  Takahisa Kawabe and
                  Taira Shibuya and
                  Mario Sako and
                  Kosuke Yanagidaira and
                  Toshifumi Hashimoto and
                  Hiroki Date and
                  Manabu Sato and
                  Tomoki Nakagawa and
                  Junji Musha and
                  Takatoshi Minamoto and
                  Kazushige Kanda and
                  Mizuki Uda and
                  Dai Nakamura and
                  Katsuaki Sakurai and
                  Takahiro Yamashita and
                  Jieyun Zhou and
                  Ryoichi Tachibana and
                  Teruo Takagiwa and
                  Takahiro Sugimoto and
                  Masatsugu Ogawa and
                  Yusuke Ochi and
                  Takahiro Shimizu and
                  Kazuaki Kawaguchi and
                  Masatsugu Kojima and
                  Takeshi Ogawa and
                  Tomoharu Hashiguchi and
                  Ryo Fukuda and
                  Masami Masuda and
                  Koichi Kawakami and
                  Tadashi Someya and
                  Yasuyuki Kajitani and
                  Yuuki Matsumoto and
                  Jun Nakai and
                  Jumpei Sato and
                  Namasivayam Raghunathan and
                  Yee Lih Koh and
                  Shuo Chen and
                  Juan Lee and
                  Hiroaki Nasu and
                  Hiroshi Sugawara and
                  Koji Hosono and
                  Toshiki Hisada and
                  Hiroshi Nakamura and
                  Osamu Nagao and
                  Naoki Kobayashi and
                  Makoto Miakashi and
                  Yasushi Nagadomi and
                  Tomoaki Nakano},
  title        = {A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {55},
  number       = {1},
  pages        = {178--188},
  year         = {2020},
  url          = {https://doi.org/10.1109/JSSC.2019.2941758},
  doi          = {10.1109/JSSC.2019.2941758},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShibataKSSYHDSN20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShibataKSNNKMNN19,
  author       = {Noboru Shibata and
                  Kazushige Kanda and
                  Takahiro Shimizu and
                  Jun Nakai and
                  Osamu Nagao and
                  Naoki Kobayashi and
                  Makoto Miakashi and
                  Yasushi Nagadomi and
                  Takeshi Nakano and
                  Takahisa Kawabe and
                  Taira Shibuya and
                  Mario Sako and
                  Kosuke Yanagidaira and
                  Toshifumi Hashimoto and
                  Hiroki Date and
                  Manabu Sato and
                  Tomoki Nakagawa and
                  H. Takamoto and
                  Junji Musha and
                  Takatoshi Minamoto and
                  Mizuki Uda and
                  Dai Nakamura and
                  Katsuaki Sakurai and
                  Takahiro Yamashita and
                  Jieyun Zhou and
                  Ryoichi Tachibana and
                  Teruo Takagiwa and
                  Takahiro Sugimoto and
                  Mikio Ogawa and
                  Yusuke Ochi and
                  Kazuaki Kawaguchi and
                  Masatsugu Kojima and
                  Takeshi Ogawa and
                  Tomoharu Hashiguchi and
                  Ryo Fukuda and
                  Masami Masuda and
                  Koichi Kawakami and
                  Tadashi Someya and
                  Yasuyuki Kajitani and
                  Yuuki Matsumoto and
                  Naohito Morozumi and
                  Jumpei Sato and
                  Namas Raghunathan and
                  Yee Lih Koh and
                  Shuo Chen and
                  Juan Lee and
                  Hiroaki Nasu and
                  Hiroshi Sugawara and
                  Koji Hosono and
                  Toshiki Hisada and
                  T. Kaneko and
                  Hiroshi Nakamura},
  title        = {A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
                  San Francisco, CA, USA, February 17-21, 2019},
  pages        = {210--212},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISSCC.2019.8662443},
  doi          = {10.1109/ISSCC.2019.8662443},
  timestamp    = {Thu, 25 Feb 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ShibataKSNNKMNN19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MaejimaKFTOSSSK18,
  author       = {Hiroshi Maejima and
                  Kazushige Kanda and
                  Susumu Fujimura and
                  Teruo Takagiwa and
                  Susumu Ozawa and
                  Jumpei Sato and
                  Yoshihiko Shindo and
                  Manabu Sato and
                  Naoaki Kanagawa and
                  Junji Musha and
                  Satoshi Inoue and
                  Katsuaki Sakurai and
                  Naohito Morozumi and
                  Ryo Fukuda and
                  Yuui Shimizu and
                  Toshifumi Hashimoto and
                  Xu Li and
                  Yuki Shimizu and
                  Kenichi Abe and
                  Tadashi Yasufuku and
                  Takatoshi Minamoto and
                  Hiroshi Yoshihara and
                  Takahiro Yamashita and
                  Kazuhiko Satou and
                  Takahiro Sugimoto and
                  Fumihiro Kono and
                  Mitsuhiro Abe and
                  Tomoharu Hashiguchi and
                  Masatsugu Kojima and
                  Yasuhiro Suematsu and
                  Takahiro Shimizu and
                  Akihiro Imamoto and
                  Naoki Kobayashi and
                  Makoto Miakashi and
                  Kouichirou Yamaguchi and
                  Sanad Bushnaq and
                  Hicham Haibi and
                  Masatsugu Ogawa and
                  Yusuke Ochi and
                  Kenro Kubota and
                  Taichi Wakui and
                  Dong He and
                  Weihan Wang and
                  Hiroe Minagawa and
                  Tomoko Nishiuchi and
                  Hao Nguyen and
                  Kwang{-}Ho Kim and
                  Ken Cheah and
                  Yee Lih Koh and
                  Feng Lu and
                  Venky Ramachandra and
                  Srinivas Rajendra and
                  Steve Choi and
                  Keyur Payak and
                  Namas Raghunathan and
                  Spiros Georgakis and
                  Hiroshi Sugawara and
                  Seungpil Lee and
                  Takuya Futatsuyama and
                  Koji Hosono and
                  Noboru Shibata and
                  Toshiki Hisada and
                  Tetsuya Kaneko and
                  Hiroshi Nakamura},
  title        = {A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology},
  booktitle    = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2018, San Francisco, CA, USA, February 11-15, 2018},
  pages        = {336--338},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISSCC.2018.8310321},
  doi          = {10.1109/ISSCC.2018.8310321},
  timestamp    = {Tue, 14 Jan 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/MaejimaKFTOSSSK18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KandaSHISSSSKKKOIKSSSFUHKMISHKZCWDOY13,
  author       = {Kazushige Kanda and
                  Noboru Shibata and
                  Toshiki Hisada and
                  Katsuaki Isobe and
                  Manabu Sato and
                  Yui Shimizu and
                  Takahiro Shimizu and
                  Takahiro Sugimoto and
                  Tomohiro Kobayashi and
                  Naoaki Kanagawa and
                  Yasuyuki Kajitani and
                  Takeshi Ogawa and
                  Kiyoaki Iwasa and
                  Masatsugu Kojima and
                  Toshihiro Suzuki and
                  Yuya Suzuki and
                  Shintaro Sakai and
                  Tomofumi Fujimura and
                  Yuko Utsunomiya and
                  Toshifumi Hashimoto and
                  Naoki Kobayashi and
                  Yuuki Matsumoto and
                  Satoshi Inoue and
                  Yoshinao Suzuki and
                  Yasuhiko Honda and
                  Yosuke Kato and
                  Shingo Zaitsu and
                  Hardwell Chibvongodze and
                  Mitsuyuki Watanabe and
                  Hong Ding and
                  Naoki Ookuma and
                  Ryuji Yamashita},
  title        = {A 19 nm 112.8 mm\({}^{\mbox{2}}\) 64 Gb Multi-Level Flash Memory With
                  400 Mbit/sec/pin 1.8 {V} Toggle Mode Interface},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {48},
  number       = {1},
  pages        = {159--167},
  year         = {2013},
  url          = {https://doi.org/10.1109/JSSC.2012.2215094},
  doi          = {10.1109/JSSC.2012.2215094},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KandaSHISSSSKKKOIKSSSFUHKMISHKZCWDOY13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TakashimaNSKSF12,
  author       = {Daisaburo Takashima and
                  Mitsuhiro Noguchi and
                  Noboru Shibata and
                  Kazushige Kanda and
                  Hiroshi Sukegawa and
                  Shuso Fujii},
  title        = {An Embedded {DRAM} Technology for High-Performance {NAND} Flash Memories},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {2},
  pages        = {536--546},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2011.2170779},
  doi          = {10.1109/JSSC.2011.2170779},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/TakashimaNSKSF12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShibataKH12,
  author       = {Noboru Shibata and
                  Kazushige Kanda and
                  Toshiki Hisada and
                  Katsuaki Isobe and
                  Manabu Sato and
                  Yui Shimizu and
                  Takahiro Shimizu and
                  Takahiro Sugimoto and
                  Tomohiro Kobayashi and
                  Kazuko Inuzuka and
                  Naoaki Kanagawa and
                  Yasuyuki Kajitani and
                  Takeshi Ogawa and
                  J. Nakai and
                  Kiyoaki Iwasa and
                  Masatsugu Kojima and
                  Toshihiro Suzuki and
                  Yuya Suzuki and
                  Shintaro Sakai and
                  Tomofumi Fujimura and
                  Yuko Utsunomiya and
                  Toshifumi Hashimoto and
                  Makoto Miakashi and
                  Naoki Kobayashi and
                  M. Inagaki and
                  Yuuki Matsumoto and
                  Satoshi Inoue and
                  Yoshinao Suzuki and
                  D. He and
                  Yasuhiko Honda and
                  Junji Musha and
                  Masaki Nakagawa and
                  Mitsuaki Honma and
                  Naofumi Abiko and
                  Mitsumasa Koyanagi and
                  Masahiro Yoshihara and
                  Kazumi Ino and
                  Mitsuhiro Noguchi and
                  Teruhiko Kamei and
                  Yosuke Kato and
                  Shingo Zaitsu and
                  Hiroaki Nasu and
                  Takuya Ariki and
                  Hardwell Chibvongodze and
                  Mitsuyuki Watanabe and
                  Hong Ding and
                  Naoki Ookuma and
                  Ryuji Yamashita and
                  G. Liang and
                  Gertjan Hemink and
                  Farookh Moogat and
                  Cuong Trinh and
                  Masaaki Higashitani and
                  Tuan Pham and
                  Kousuke Kanazawa},
  title        = {A 19nm 112.8mm\({}^{\mbox{2}}\) 64Gb multi-level flash memory with
                  400Mb/s/pin 1.8V Toggle Mode interface},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {422--424},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6177073},
  doi          = {10.1109/ISSCC.2012.6177073},
  timestamp    = {Wed, 10 Mar 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ShibataKH12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TakashimaNSKSF11,
  author       = {Daisaburo Takashima and
                  Mitsuhiro Noguchi and
                  Noboru Shibata and
                  Kazushige Kanda and
                  Hiroshi Sukegawa and
                  Shuso Fujii},
  title        = {An embedded {DRAM} technology for high-performance {NAND} flash memories},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
                  Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
                  2011},
  pages        = {504--505},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISSCC.2011.5746417},
  doi          = {10.1109/ISSCC.2011.5746417},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TakashimaNSKSF11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KandaKYHYMKMCTCLMTOKFTISNSOKYAHMNYHIKHMIO08,
  author       = {Kazushige Kanda and
                  Masaru Koyanagi and
                  Toshio Yamamura and
                  Koji Hosono and
                  Masahiro Yoshihara and
                  Toru Miwa and
                  Yosuke Kato and
                  Alex Mak and
                  Siu Lung Chan and
                  Frank Tsai and
                  Raul Cernea and
                  Binh Le and
                  Eiichi Makino and
                  Takashi Taira and
                  Hiroyuki Otake and
                  Norifumi Kajimura and
                  Susumu Fujimura and
                  Yoshiaki Takeuchi and
                  Mikihiko Itoh and
                  Masanobu Shirakawa and
                  Dai Nakamura and
                  Yuya Suzuki and
                  Yuki Okukawa and
                  Masatsugu Kojima and
                  Kazuhide Yoneya and
                  Takamichi Arizono and
                  Toshiki Hisada and
                  Shinji Miyamoto and
                  Mitsuhiro Noguchi and
                  Toshitake Yaegashi and
                  Masaaki Higashitani and
                  Fumitoshi Ito and
                  Teruhiko Kamei and
                  Gertjan Hemink and
                  Tooru Maruyama and
                  Kazumi Ino and
                  Shigeo Ohshima},
  title        = {A 120mm\({}^{\mbox{2}}\) 16Gb 4-MLC {NAND} Flash Memory with 43nm
                  {CMOS} Technology},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {430--431},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523241},
  doi          = {10.1109/ISSCC.2008.4523241},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KandaKYHYMKMCTCLMTOKFTISNSOKYAHMNYHIKHMIO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ImamiyaNHYITKHF02,
  author       = {Kenichi Imamiya and
                  Hiroshi Nakamura and
                  Toshihiko Himeno and
                  Toshio Yamamura and
                  Tamio Ikehashi and
                  Ken Takeuchi and
                  Kazushige Kanda and
                  Koji Hosono and
                  Takuya Futatsuyama and
                  Koichi Kawai and
                  Riichiro Shirota and
                  Norihisa Arai and
                  Fumitaka Arai and
                  Kazuo Hatakeyama and
                  Hiroaki Hazama and
                  Masanobu Saito and
                  Hisataka Meguro and
                  Kevin Conley and
                  Khandker Quader and
                  Jian J. Che},
  title        = {A 125-mm\({}^{\mbox{2}}\) 1-Gb {NAND} flash memory with 10-MByte/s
                  program speed},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {37},
  number       = {11},
  pages        = {1493--1501},
  year         = {2002},
  url          = {https://doi.org/10.1109/JSSC.2002.802355},
  doi          = {10.1109/JSSC.2002.802355},
  timestamp    = {Wed, 06 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ImamiyaNHYITKHF02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ImamiyaSNHTIKHS99,
  author       = {Kenichi Imamiya and
                  Yoshihisa Sugiura and
                  Hiroshi Nakamura and
                  Toshihiko Himeno and
                  Ken Takeuchi and
                  Tamio Ikehashi and
                  Kazushige Kanda and
                  Koji Hosono and
                  Riichiro Shirota and
                  Seiichi Aritome and
                  Kazuhiro Shimizu and
                  Kazuo Hatakeyama and
                  Koji Sakui},
  title        = {A 130-mm/\({}^{\mbox{2}}\), 256-Mbit {NAND} flash with shallow trench
                  isolation technology},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {34},
  number       = {11},
  pages        = {1536--1543},
  year         = {1999},
  url          = {https://doi.org/10.1109/4.799860},
  doi          = {10.1109/4.799860},
  timestamp    = {Wed, 06 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ImamiyaSNHTIKHS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimSLIKKLNKHKKJ97,
  author       = {Jin{-}Ki Kim and
                  Koji Sakui and
                  Sung{-}Soo Lee and
                  Yasuo Itoh and
                  Suk{-}Chon Kwon and
                  Kazuhisa Kanazawa and
                  Ki{-}Jun Lee and
                  Hiroshi Nakamura and
                  Kang{-}Young Kim and
                  Toshihiko Himeno and
                  Jang{-}Rae Kim and
                  Kazushige Kanda and
                  Tae{-}Sung Jung and
                  Yoichi Oshima and
                  Kang{-}Deog Suh and
                  Kazuhiko Hashimoto and
                  Sung{-}Tae Ahn and
                  Junichi Miyamoto},
  title        = {A 120-mm\({}^{\mbox{2}}\) 64-Mb {NAND} flash memory achieving 180
                  ns/Byte effective program speed},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {32},
  number       = {5},
  pages        = {670--680},
  year         = {1997},
  url          = {https://doi.org/10.1109/4.568831},
  doi          = {10.1109/4.568831},
  timestamp    = {Tue, 26 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KimSLIKKLNKHKKJ97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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