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ORCIDBibTeX records: Yun Liang 0001
@article{DBLP:journals/tcad/LuLZYCLY24,
author = {Liqiang Lu and
Zizhang Luo and
Size Zheng and
Jieming Yin and
Jason Cong and
Yun Liang and
Jianwei Yin},
title = {Rubick: {A} Unified Infrastructure for Analyzing, Exploring, and Implementing
Spatial Architectures via Dataflow Decomposition},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {4},
pages = {1177--1190},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3337208},
doi = {10.1109/TCAD.2023.3337208},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuLZYCLY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aaai/ChenZW024,
author = {Yingjie Chen and
Jiarui Zhang and
Tao Wang and
Yun Liang},
editor = {Michael J. Wooldridge and
Jennifer G. Dy and
Sriraam Natarajan},
title = {Trend-Aware Supervision: On Learning Invariance for Semi-supervised
Facial Action Unit Intensity Estimation},
booktitle = {Thirty-Eighth {AAAI} Conference on Artificial Intelligence, {AAAI}
2024, Thirty-Sixth Conference on Innovative Applications of Artificial
Intelligence, {IAAI} 2024, Fourteenth Symposium on Educational Advances
in Artificial Intelligence, {EAAI} 2014, February 20-27, 2024, Vancouver,
Canada},
pages = {483--491},
publisher = {{AAAI} Press},
year = {2024},
url = {https://doi.org/10.1609/aaai.v38i1.27803},
doi = {10.1609/AAAI.V38I1.27803},
timestamp = {Tue, 02 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aaai/ChenZW024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/GuanQL0YLF0Z00L24,
author = {Yue Guan and
Yuxian Qiu and
Jingwen Leng and
Fan Yang and
Shuo Yu and
Yunxin Liu and
Yu Feng and
Yuhao Zhu and
Lidong Zhou and
Yun Liang and
Chen Zhang and
Chao Li and
Minyi Guo},
editor = {Rajiv Gupta and
Nael B. Abu{-}Ghazaleh and
Madan Musuvathi and
Dan Tsafrir},
title = {Amanda: Unified Instrumentation Framework for Deep Neural Networks},
booktitle = {Proceedings of the 29th {ACM} International Conference on Architectural
Support for Programming Languages and Operating Systems, Volume 1,
{ASPLOS} 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024},
pages = {1--18},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3617232.3624864},
doi = {10.1145/3617232.3624864},
timestamp = {Fri, 19 Apr 2024 11:32:06 +0200},
biburl = {https://dblp.org/rec/conf/asplos/GuanQL0YLF0Z00L24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XuL024,
author = {Ruifan Xu and
Jin Luo and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level
IRs},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {186},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637606},
doi = {10.1145/3626202.3637606},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XuL024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HaoRZSJ024,
author = {Xiaochen Hao and
Hongbo Rong and
Mingzhe Zhang and
Ce Sun and
Hong H. Jiang and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {{POPA:} Expressing High and Portable Performance across Spatial and
Vector Architectures for Tensor Computations},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {199--210},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637566},
doi = {10.1145/3626202.3637566},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/HaoRZSJ024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XiaoLZ024,
author = {Youwei Xiao and
Zizhang Luo and
Kexing Zhou and
Yun Liang},
editor = {Zhiru Zhang and
Andrew Putnam},
title = {Cement: Streamlining {FPGA} Hardware Design with Cycle-Deterministic
eHDL and Synthesis},
booktitle = {Proceedings of the 2024 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2024, Monterey, CA, USA, March 3-5,
2024},
pages = {211--222},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626202.3637561},
doi = {10.1145/3626202.3637561},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/XiaoLZ024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2403-07257,
author = {Lei Chen and
Yiqi Chen and
Zhufei Chu and
Wenji Fang and
Tsung{-}Yi Ho and
Yu Huang and
Sadaf Khan and
Min Li and
Xingquan Li and
Yun Liang and
Yibo Lin and
Jinwei Liu and
Yi Liu and
Guojie Luo and
Zhengyuan Shi and
Guangyu Sun and
Dimitrios Tsaras and
Runsheng Wang and
Ziyi Wang and
Xinming Wei and
Zhiyao Xie and
Qiang Xu and
Chenhao Xue and
Evangeline F. Y. Young and
Bei Yu and
Mingxuan Yuan and
Haoyi Zhang and
Zuodong Zhang and
Yuxiang Zhao and
Hui{-}Ling Zhen and
Ziyang Zheng and
Binwu Zhu and
Keren Zhu and
Sunan Zou},
title = {The Dawn of AI-Native {EDA:} Promises and Challenges of Large Circuit
Models},
journal = {CoRR},
volume = {abs/2403.07257},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2403.07257},
doi = {10.48550/ARXIV.2403.07257},
eprinttype = {arXiv},
eprint = {2403.07257},
timestamp = {Fri, 05 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2403-07257.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiaLLL23,
author = {Liancheng Jia and
Zizhang Luo and
Liqiang Lu and
Yun Liang},
title = {Automatic Generation of Spatial Accelerator for Tensor Algebra},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {6},
pages = {1898--1911},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3209949},
doi = {10.1109/TCAD.2022.3209949},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiaLLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/LiangZNL23,
author = {Yun Liang and
Wei Zhang and
Stephen Neuendorffer and
Wayne Luk},
title = {Special Issue: "AI Acceleration on FPGAs"},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {22},
number = {6},
pages = {89:1--89:3},
year = {2023},
url = {https://doi.org/10.1145/3626323},
doi = {10.1145/3626323},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/LiangZNL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/MaiWDLLL23,
author = {Jing Mai and
Jiarui Wang and
Zhixiong Di and
Guojie Luo and
Yun Liang and
Yibo Lin},
title = {OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale
Heterogeneous FPGAs with Deep Learning Toolkit},
booktitle = {15th {IEEE} International Conference on ASIC, {ASICON} 2023, Nanjing,
China, October 24-27, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ASICON58565.2023.10396248},
doi = {10.1109/ASICON58565.2023.10396248},
timestamp = {Fri, 16 Feb 2024 14:02:58 +0100},
biburl = {https://dblp.org/rec/conf/asicon/MaiWDLLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bmvc/ChenZ0023,
author = {Yingjie Chen and
Jiarui Zhang and
Tao Wang and
Yun Liang},
title = {EventFormer: {AU} Event Transformer for Facial Action Unit Event Detection},
booktitle = {34th British Machine Vision Conference 2023, {BMVC} 2023, Aberdeen,
UK, November 20-24, 2023},
pages = {287--289},
publisher = {{BMVA} Press},
year = {2023},
url = {http://proceedings.bmvc2023.org/287/},
timestamp = {Mon, 11 Mar 2024 15:42:29 +0100},
biburl = {https://dblp.org/rec/conf/bmvc/ChenZ0023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DongJDJWZZYMLYH23,
author = {Yanchi Dong and
Tianyu Jia and
Kaixuan Du and
Yiqi Jing and
Qijun Wang and
Pixian Zhan and
Yadong Zhang and
Fengyun Yan and
Yufei Ma and
Yun Liang and
Le Ye and
Ru Huang},
title = {A Model-Specific End-to-End Design Methodology for Resource-Constrained
TinyML Hardware},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247791},
doi = {10.1109/DAC56929.2023.10247791},
timestamp = {Sun, 24 Sep 2023 13:31:06 +0200},
biburl = {https://dblp.org/rec/conf/dac/DongJDJWZZYMLYH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LuoLZYCYL23,
author = {Zizhang Luo and
Liqiang Lu and
Size Zheng and
Jieming Yin and
Jason Cong and
Jianwei Yin and
Yun Liang},
title = {Rubick: {A} Synthesis Framework for Spatial Architectures via Dataflow
Decomposition},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247743},
doi = {10.1109/DAC56929.2023.10247743},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LuoLZYCYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhengCL23,
author = {Size Zheng and
Siyuan Chen and
Yun Liang},
title = {Memory and Computation Coordinated Mapping of DNNs onto Complex Heterogeneous
SoC},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247951},
doi = {10.1109/DAC56929.2023.10247951},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/ZhengCL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/HaoZSTRZHPC023,
author = {Xiaochen Hao and
Mingzhe Zhang and
Ce Sun and
Zhuofu Tao and
Hongbo Rong and
Yu Zhang and
Lei He and
Eric Petit and
Wenguang Chen and
Yun Liang},
title = {Lasa: Abstraction and Specialization for Productive and Performant
Linear Algebra on FPGAs},
booktitle = {31st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2023, Marina Del Rey, CA, USA, May 8-11,
2023},
pages = {34--40},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FCCM57271.2023.00013},
doi = {10.1109/FCCM57271.2023.00013},
timestamp = {Sun, 30 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fccm/HaoZSTRZHPC023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LuoLJJL23,
author = {Zizhang Luo and
Liqiang Lu and
Yicheng Jin and
Liancheng Jia and
Yun Liang},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Nikela Papadopoulou and
Ioannis Sourdis},
title = {Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs},
booktitle = {33rd International Conference on Field-Programmable Logic and Applications,
{FPL} 2023, Gothenburg, Sweden, September 4-8, 2023},
pages = {242--247},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FPL60245.2023.00041},
doi = {10.1109/FPL60245.2023.00041},
timestamp = {Fri, 17 Nov 2023 08:57:25 +0100},
biburl = {https://dblp.org/rec/conf/fpl/LuoLJJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/ZhengCSCLYLLL23,
author = {Size Zheng and
Siyuan Chen and
Peidi Song and
Renze Chen and
Xiuhong Li and
Shengen Yan and
Dahua Lin and
Jingwen Leng and
Yun Liang},
title = {Chimera: An Analytical Optimizing Framework for Effective Compute-intensive
Operators Fusion},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2023, Montreal, QC, Canada, February 25 - March 1, 2023},
pages = {1113--1126},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/HPCA56546.2023.10071018},
doi = {10.1109/HPCA56546.2023.10071018},
timestamp = {Wed, 29 Mar 2023 11:07:46 +0200},
biburl = {https://dblp.org/rec/conf/hpca/ZhengCSCLYLLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenWLL23,
author = {Yifan Chen and
Zaiwen Wen and
Yun Liang and
Yibo Lin},
title = {Stronger Mixed-Size Placement Backbone Considering Second-Order Information},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323700},
doi = {10.1109/ICCAD57390.2023.10323700},
timestamp = {Wed, 03 Jan 2024 08:34:26 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChenWLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/CuiZJYL23,
author = {Xiuping Cui and
Size Zheng and
Tianyu Jia and
Le Ye and
Yun Liang},
title = {{ARES:} {A} Mapping Framework of DNNs Towards Diverse PIMs with General
Abstractions},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323777},
doi = {10.1109/ICCAD57390.2023.10323777},
timestamp = {Wed, 03 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/CuiZJYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HaoDYWL23,
author = {Xiaochen Hao and
Zijian Ding and
Jieming Yin and
Yuan Wang and
Yun Liang},
title = {Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial
Accelerators},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323880},
doi = {10.1109/ICCAD57390.2023.10323880},
timestamp = {Wed, 03 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HaoDYWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhongLLWH23,
author = {Shuzhang Zhong and
Meng Li and
Yun Liang and
Runsheng Wang and
Ru Huang},
title = {Memory-aware Scheduling for Complex Wired Networks with Iterative
Graph Optimization},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323998},
doi = {10.1109/ICCAD57390.2023.10323998},
timestamp = {Wed, 03 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhongLLWH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/Zhou0LWH23,
author = {Kexing Zhou and
Yun Liang and
Yibo Lin and
Runsheng Wang and
Ru Huang},
title = {Khronos: Fusing Memory Access for Improved Hardware {RTL} Simulation},
booktitle = {Proceedings of the 56th Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 2023, Toronto, ON, Canada, 28 October
2023 - 1 November 2023},
pages = {180--193},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3613424.3614301},
doi = {10.1145/3613424.3614301},
timestamp = {Sun, 31 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/Zhou0LWH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/0001CGJ0W023,
author = {Size Zheng and
Siyuan Chen and
Siyuan Gao and
Liancheng Jia and
Guangyu Sun and
Runsheng Wang and
Yun Liang},
title = {TileFlow: {A} Framework for Modeling Fusion Dataflow via Tree-based
Analysis},
booktitle = {Proceedings of the 56th Annual {IEEE/ACM} International Symposium
on Microarchitecture, {MICRO} 2023, Toronto, ON, Canada, 28 October
2023 - 1 November 2023},
pages = {1271--1288},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3613424.3623792},
doi = {10.1145/3613424.3623792},
timestamp = {Sun, 31 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/0001CGJ0W023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2302-11256,
author = {Xiaochen Hao and
Zijian Ding and
Jieming Yin and
Yuan Wang and
Yun Liang},
title = {{ALEGO:} Towards Cost-Aware Architecture and Integration Co-Design
for Chiplet-based Spatial Accelerators},
journal = {CoRR},
volume = {abs/2302.11256},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2302.11256},
doi = {10.48550/ARXIV.2302.11256},
eprinttype = {arXiv},
eprint = {2302.11256},
timestamp = {Mon, 06 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2302-11256.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-02267,
author = {Jiangfei Duan and
Xiuhong Li and
Ping Xu and
Xingcheng Zhang and
Shengen Yan and
Yun Liang and
Dahua Lin},
title = {Proteus: Simulating the Performance of Distributed {DNN} Training},
journal = {CoRR},
volume = {abs/2306.02267},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.02267},
doi = {10.48550/ARXIV.2306.02267},
eprinttype = {arXiv},
eprint = {2306.02267},
timestamp = {Mon, 12 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-02267.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-16665,
author = {Jing Mai and
Jiarui Wang and
Zhixiong Di and
Guojie Luo and
Yun Liang and
Yibo Lin},
title = {OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale
Heterogeneous FPGAs with Deep Learning Toolkit},
journal = {CoRR},
volume = {abs/2306.16665},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.16665},
doi = {10.48550/ARXIV.2306.16665},
eprinttype = {arXiv},
eprint = {2306.16665},
timestamp = {Mon, 03 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-16665.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2308-13898,
author = {Shuzhang Zhong and
Meng Li and
Yun Liang and
Runsheng Wang and
Ru Huang},
title = {Memory-aware Scheduling for Complex Wired Networks with Iterative
Graph Optimization},
journal = {CoRR},
volume = {abs/2308.13898},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2308.13898},
doi = {10.48550/ARXIV.2308.13898},
eprinttype = {arXiv},
eprint = {2308.13898},
timestamp = {Mon, 20 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2308-13898.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/aiopen/WeiTWLC22,
author = {Tao Wei and
Yonghong Tian and
Yaowei Wang and
Yun Liang and
Chang Wen Chen},
title = {Optimized separable convolution: Yet another efficient convolution
operator},
journal = {{AI} Open},
volume = {3},
pages = {162--171},
year = {2022},
url = {https://doi.org/10.1016/j.aiopen.2022.10.002},
doi = {10.1016/J.AIOPEN.2022.10.002},
timestamp = {Tue, 31 Oct 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/aiopen/WeiTWLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangLJXHZL22,
author = {Yun Liang and
Liqiang Lu and
Yicheng Jin and
Jiaming Xie and
Ruirui Huang and
Jiansong Zhang and
Wei Lin},
title = {An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based
Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {3},
pages = {597--613},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3066563},
doi = {10.1109/TCAD.2021.3066563},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangLJXHZL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangXLX22,
author = {Yun Liang and
Qingcheng Xiao and
Liqiang Lu and
Jiaming Xie},
title = {FCNNLib: {A} Flexible Convolution Algorithm Library for Deep Learning
on FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {8},
pages = {2546--2559},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3108065},
doi = {10.1109/TCAD.2021.3108065},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangXLX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuL22,
author = {Liqiang Lu and
Yun Liang},
title = {Morphling: {A} Reconfigurable Architecture for Tensor Computation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {4733--4746},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3135322},
doi = {10.1109/TCAD.2021.3135322},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/FanGHPXYYFL22,
author = {Zejia Fan and
Yuchen Gu and
Zhewen Hao and
Yueyang Pan and
Pengcheng Xu and
Yuxuan Yan and
Fangyuan Yang and
Zhenxin Fu and
Yun Liang},
title = {Critique of "MemXCT: Memory-Centric X-Ray {CT} Reconstruction
With Massive Parallelization" by {SCC} Team From Peking University},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {33},
number = {9},
pages = {2032--2034},
year = {2022},
url = {https://doi.org/10.1109/TPDS.2021.3092273},
doi = {10.1109/TPDS.2021.3092273},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/FanGHPXYYFL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/ZhengCJWWLYL22,
author = {Size Zheng and
Renze Chen and
Yicheng Jin and
Anjiang Wei and
Bingyang Wu and
Xiuhong Li and
Shengen Yan and
Yun Liang},
title = {NeoFlow: {A} Flexible Framework for Enabling Efficient Compilation
for High Performance {DNN} Training},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {33},
number = {11},
pages = {3220--3232},
year = {2022},
url = {https://doi.org/10.1109/TPDS.2021.3138862},
doi = {10.1109/TPDS.2021.3138862},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/ZhengCJWWLYL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aaai/ChenCWW022,
author = {Yingjie Chen and
Diqi Chen and
Tao Wang and
Yizhou Wang and
Yun Liang},
title = {Causal Intervention for Subject-Deconfounded Facial Action Unit Recognition},
booktitle = {Thirty-Sixth {AAAI} Conference on Artificial Intelligence, {AAAI}
2022, Thirty-Fourth Conference on Innovative Applications of Artificial
Intelligence, {IAAI} 2022, The Twelveth Symposium on Educational Advances
in Artificial Intelligence, {EAAI} 2022 Virtual Event, February 22
- March 1, 2022},
pages = {374--382},
publisher = {{AAAI} Press},
year = {2022},
url = {https://doi.org/10.1609/aaai.v36i1.19914},
doi = {10.1609/AAAI.V36I1.19914},
timestamp = {Mon, 04 Sep 2023 12:29:24 +0200},
biburl = {https://dblp.org/rec/conf/aaai/ChenCWW022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/CuiHLSCWH22,
author = {Xiuping Cui and
Xiaochen Hao and
Yun Liang and
Guangyu Sun and
Xiaoxin Cui and
Yuan Wang and
Ru Huang},
title = {A Mapping Model of SNNs to Neuromorphic Hardware},
booktitle = {4th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2022, Incheon, Republic of Korea, June 13-15,
2022},
pages = {206--209},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/AICAS54282.2022.9869998},
doi = {10.1109/AICAS54282.2022.9869998},
timestamp = {Mon, 06 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aicas/CuiHLSCWH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JiaWL022,
author = {Liancheng Jia and
Yuyue Wang and
Jingwen Leng and
Yun Liang},
editor = {Rob Oshana},
title = {{EMS:} efficient memory subsystem synthesis for spatial accelerators},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {67--72},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530411},
doi = {10.1145/3489517.3530411},
timestamp = {Thu, 18 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/JiaWL022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eccv/ChenZCSHWLS22,
author = {Yingjie Chen and
Huasong Zhong and
Chong Chen and
Chen Shen and
Jianqiang Huang and
Tao Wang and
Yun Liang and
Qianru Sun},
editor = {Shai Avidan and
Gabriel J. Brostow and
Moustapha Ciss{\'{e}} and
Giovanni Maria Farinella and
Tal Hassner},
title = {On Mitigating Hard Clusters for Face Clustering},
booktitle = {Computer Vision - {ECCV} 2022 - 17th European Conference, Tel Aviv,
Israel, October 23-27, 2022, Proceedings, Part {XII}},
series = {Lecture Notes in Computer Science},
volume = {13672},
pages = {529--544},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-19775-8\_31},
doi = {10.1007/978-3-031-19775-8\_31},
timestamp = {Mon, 19 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eccv/ChenZCSHWLS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Xiao022,
author = {Qingcheng Xiao and
Yun Liang},
editor = {Michael Adler and
Paolo Ienne},
title = {Towards Agile {DNN} Accelerator Design Using Incremental Synthesis
on FPGAs},
booktitle = {{FPGA} '22: The 2022 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022},
pages = {42--48},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3490422.3502351},
doi = {10.1145/3490422.3502351},
timestamp = {Mon, 14 Feb 2022 10:33:28 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Xiao022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZhangCLN22,
author = {Wei Zhang and
Ray C. C. Cheung and
Yun Liang and
Hiroki Nakahara},
title = {Message from the General Chair and Program Co-Chairs},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2022, Hong Kong, December 5-9, 2022},
pages = {1},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICFPT56656.2022.9974448},
doi = {10.1109/ICFPT56656.2022.9974448},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ZhangCLN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/LiangNZMC22,
author = {Yun Liang and
Hiroki Nakahara and
Wei Zhang and
Fubing Mao and
Ray C. C. Cheung},
title = {Preface},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2022, Hong Kong, December 5-9, 2022},
pages = {i},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICFPT56656.2022.9974431},
doi = {10.1109/ICFPT56656.2022.9974431},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/LiangNZMC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XuXLL22,
author = {Ruifan Xu and
Youwei Xiao and
Jin Luo and
Yun Liang},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {{HECTOR:} {A} Multi-Level Intermediate Representation for Hardware
Synthesis Methodologies},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {54:1--54:9},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3549370},
doi = {10.1145/3508352.3549370},
timestamp = {Tue, 06 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/XuXLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdcs/LiLJLWT22,
author = {Haokun Li and
Jing Liu and
Liancheng Jia and
Yun Liang and
Yaowei Wang and
Mingkui Tan},
title = {Downscaling and Overflow-aware Model Compression for Efficient Vision
Processors},
booktitle = {42nd {IEEE} International Conference on Distributed Computing Systems,
{ICDCS} Workshops, Bologna, Italy, July 10, 2022},
pages = {145--150},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICDCSW56584.2022.00036},
doi = {10.1109/ICDCSW56584.2022.00036},
timestamp = {Tue, 31 Oct 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icdcs/LiLJLWT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/0001CWJHLWLY022,
author = {Size Zheng and
Renze Chen and
Anjiang Wei and
Yicheng Jin and
Qin Han and
Liqiang Lu and
Bingyang Wu and
Xiuhong Li and
Shengen Yan and
Yun Liang},
editor = {Valentina Salapura and
Mohamed Zahran and
Fred Chong and
Lingjia Tang},
title = {{AMOS:} enabling automatic mapping for tensor computations on spatial
accelerators with hardware abstraction},
booktitle = {{ISCA} '22: The 49th Annual International Symposium on Computer Architecture,
New York, New York, USA, June 18 - 22, 2022},
pages = {874--887},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3470496.3527440},
doi = {10.1145/3470496.3527440},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isca/0001CWJHLWLY022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mm/Chen00H0W022,
author = {Yingjie Chen and
Chong Chen and
Xiao Luo and
Jianqiang Huang and
Xian{-}Sheng Hua and
Tao Wang and
Yun Liang},
editor = {Jo{\~{a}}o Magalh{\~{a}}es and
Alberto Del Bimbo and
Shin'ichi Satoh and
Nicu Sebe and
Xavier Alameda{-}Pineda and
Qin Jin and
Vincent Oria and
Laura Toni},
title = {Pursuing Knowledge Consistency: Supervised Hierarchical Contrastive
Learning for Facial Action Unit Recognition},
booktitle = {{MM} '22: The 30th {ACM} International Conference on Multimedia, Lisboa,
Portugal, October 10 - 14, 2022},
pages = {111--119},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3503161.3548116},
doi = {10.1145/3503161.3548116},
timestamp = {Mon, 30 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mm/Chen00H0W022.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2203-06355,
author = {Yingjie Chen and
Jiarui Zhang and
Diqi Chen and
Tao Wang and
Yizhou Wang and
Yun Liang},
title = {EventFormer: {AU} Event Transformer for Facial Action Unit Event Detection},
journal = {CoRR},
volume = {abs/2203.06355},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2203.06355},
doi = {10.48550/ARXIV.2203.06355},
eprinttype = {arXiv},
eprint = {2203.06355},
timestamp = {Wed, 28 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2203-06355.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2204-07935,
author = {Yingjie Chen and
Diqi Chen and
Tao Wang and
Yizhou Wang and
Yun Liang},
title = {Causal Intervention for Subject-Deconfounded Facial Action Unit Recognition},
journal = {CoRR},
volume = {abs/2204.07935},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2204.07935},
doi = {10.48550/ARXIV.2204.07935},
eprinttype = {arXiv},
eprint = {2204.07935},
timestamp = {Wed, 28 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2204-07935.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2207-11895,
author = {Yingjie Chen and
Huasong Zhong and
Chong Chen and
Chen Shen and
Jianqiang Huang and
Tao Wang and
Yun Liang and
Qianru Sun},
title = {On Mitigating Hard Clusters for Face Clustering},
journal = {CoRR},
volume = {abs/2207.11895},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2207.11895},
doi = {10.48550/ARXIV.2207.11895},
eprinttype = {arXiv},
eprint = {2207.11895},
timestamp = {Thu, 02 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2207-11895.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/LiL21,
author = {Chao Li and
Yun Liang},
title = {Preface},
journal = {J. Comput. Sci. Technol.},
volume = {36},
number = {5},
pages = {961--962},
year = {2021},
url = {https://doi.org/10.1007/s11390-021-0006-z},
doi = {10.1007/S11390-021-0006-Z},
timestamp = {Wed, 10 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jcst/LiL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ral/ChenWWWL21,
author = {Yingjie Chen and
Han Wu and
Tao Wang and
Yizhou Wang and
Yun Liang},
title = {Cross-Modal Representation Learning for Lightweight and Accurate Facial
Action Unit Detection},
journal = {{IEEE} Robotics Autom. Lett.},
volume = {6},
number = {4},
pages = {7619--7626},
year = {2021},
url = {https://doi.org/10.1109/LRA.2021.3098944},
doi = {10.1109/LRA.2021.3098944},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ral/ChenWWWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangLX21,
author = {Yun Liang and
Liqiang Lu and
Jiaming Xie},
title = {{OMNI:} {A} Framework for Integrating Hardware and Software Optimizations
for Sparse CNNs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {8},
pages = {1648--1661},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3023903},
doi = {10.1109/TCAD.2020.3023903},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangLX21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/ChengFMWXYFL21,
author = {Yihua Cheng and
Zejia Fan and
Jing Mai and
Yifan Wu and
Pengcheng Xu and
Yuxuan Yan and
Zhenxin Fu and
Yun Liang},
title = {Critique of "Planetary Normal Mode Computation: Parallel Algorithms,
Performance, and Reproducibility" by {SCC} Team From Peking University},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {32},
number = {11},
pages = {2643--2645},
year = {2021},
url = {https://doi.org/10.1109/TPDS.2020.3049050},
doi = {10.1109/TPDS.2020.3049050},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/ChengFMWXYFL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YangHKLHYLLJ21,
author = {Tao Yang and
Zhezhi He and
Tengchuan Kou and
Qingzheng Li and
Qi Han and
Haibao Yu and
Fangxin Liu and
Yun Liang and
Li Jiang},
title = {{BISWSRBS:} {A} Winograd-based {CNN} Accelerator with a Fine-grained
Regular Sparsity Pattern and Mixed Precision Quantization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {18:1--18:28},
year = {2021},
url = {https://doi.org/10.1145/3467476},
doi = {10.1145/3467476},
timestamp = {Thu, 07 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YangHKLHYLLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JiaLL021,
author = {Liancheng Jia and
Zizhang Luo and
Liqiang Lu and
Yun Liang},
title = {TensorLib: {A} Spatial Accelerator Generation Framework for Tensor
Algebra},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {865--870},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586329},
doi = {10.1109/DAC18074.2021.9586329},
timestamp = {Fri, 12 Nov 2021 12:31:50 +0100},
biburl = {https://dblp.org/rec/conf/dac/JiaLL021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iconip/ChenZCWWL21,
author = {Yingjie Chen and
Jiarui Zhang and
Diqi Chen and
Tao Wang and
Yizhou Wang and
Yun Liang},
editor = {Teddy Mantoro and
Minho Lee and
Media Anugerah Ayu and
Kok Wai Wong and
Achmad Nizar Hidayanto},
title = {AUPro: Multi-label Facial Action Unit Proposal Generation for Sequence-Level
Analysis},
booktitle = {Neural Information Processing - 28th International Conference, {ICONIP}
2021, Sanur, Bali, Indonesia, December 8-12, 2021, Proceedings, Part
{III}},
series = {Lecture Notes in Computer Science},
volume = {13110},
pages = {88--99},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-92238-2\_8},
doi = {10.1007/978-3-030-92238-2\_8},
timestamp = {Wed, 28 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iconip/ChenZCWWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iiswc/ZhouYGLLCGZ21,
author = {Yangjie Zhou and
Mengtian Yang and
Cong Guo and
Jingwen Leng and
Yun Liang and
Quan Chen and
Minyi Guo and
Yuhao Zhu},
title = {Characterizing and Demystifying the Implicit Convolution Algorithm
on Commercial Matrix-Multiplication Accelerators},
booktitle = {{IEEE} International Symposium on Workload Characterization, {IISWC}
2021, Storrs, CT, USA, November 7-9, 2021},
pages = {214--225},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/IISWC53511.2021.00029},
doi = {10.1109/IISWC53511.2021.00029},
timestamp = {Wed, 19 Jan 2022 17:40:18 +0100},
biburl = {https://dblp.org/rec/conf/iiswc/ZhouYGLLCGZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/LuGWJLYC021,
author = {Liqiang Lu and
Naiqing Guan and
Yuyue Wang and
Liancheng Jia and
Zizhang Luo and
Jieming Yin and
Jason Cong and
Yun Liang},
title = {{TENET:} {A} Framework for Modeling Tensor Dataflow Based on Relation-centric
Notation},
booktitle = {48th {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2021, Virtual Event / Valencia, Spain, June 14-18, 2021},
pages = {720--733},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCA52012.2021.00062},
doi = {10.1109/ISCA52012.2021.00062},
timestamp = {Mon, 19 Feb 2024 07:32:07 +0100},
biburl = {https://dblp.org/rec/conf/isca/LuGWJLYC021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/Xiao0WXQ021,
author = {Qingcheng Xiao and
Size Zheng and
Bingzhe Wu and
Pengcheng Xu and
Xuehai Qian and
Yun Liang},
title = {{HASCO:} Towards Agile HArdware and Software CO-design for Tensor
Computation},
booktitle = {48th {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2021, Virtual Event / Valencia, Spain, June 14-18, 2021},
pages = {1055--1068},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCA52012.2021.00086},
doi = {10.1109/ISCA52012.2021.00086},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/Xiao0WXQ021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/JiaLL021,
author = {Liancheng Jia and
Zizhang Luo and
Liqiang Lu and
Yun Liang},
title = {Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2021, Tampa,
FL, USA, July 7-9, 2021},
pages = {230--235},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISVLSI51109.2021.00050},
doi = {10.1109/ISVLSI51109.2021.00050},
timestamp = {Mon, 30 Aug 2021 15:00:20 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/JiaLL021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/LuJBLLW021,
author = {Liqiang Lu and
Yicheng Jin and
Hangrui Bi and
Zizhang Luo and
Peng Li and
Tao Wang and
Yun Liang},
title = {Sanger: {A} Co-Design Framework for Enabling Sparse Attention using
Reconfigurable Architecture},
booktitle = {{MICRO} '21: 54th Annual {IEEE/ACM} International Symposium on Microarchitecture,
Virtual Event, Greece, October 18-22, 2021},
pages = {977--991},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3466752.3480125},
doi = {10.1145/3466752.3480125},
timestamp = {Mon, 31 Oct 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/LuJBLLW021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/mm/ChenCWW021,
author = {Yingjie Chen and
Diqi Chen and
Yizhou Wang and
Tao Wang and
Yun Liang},
editor = {Heng Tao Shen and
Yueting Zhuang and
John R. Smith and
Yang Yang and
Pablo C{\'{e}}sar and
Florian Metze and
Balakrishnan Prabhakaran},
title = {CaFGraph: Context-aware Facial Multi-graph Representation for Facial
Action Unit Recognition},
booktitle = {{MM} '21: {ACM} Multimedia Conference, Virtual Event, China, October
20 - 24, 2021},
pages = {1029--1037},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3474085.3475295},
doi = {10.1145/3474085.3475295},
timestamp = {Mon, 22 Apr 2024 21:24:20 +0200},
biburl = {https://dblp.org/rec/conf/mm/ChenCWW021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Liancheng Jia and
Zizhang Luo and
Liqiang Lu and
Yun Liang},
title = {TensorLib: {A} Spatial Accelerator Generation Framework for Tensor
Algebra},
journal = {CoRR},
volume = {abs/2104.12339},
year = {2021},
url = {https://arxiv.org/abs/2104.12339},
eprinttype = {arXiv},
eprint = {2104.12339},
timestamp = {Mon, 03 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2104-12339.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Qingcheng Xiao and
Size Zheng and
Bingzhe Wu and
Pengcheng Xu and
Xuehai Qian and
Yun Liang},
title = {{HASCO:} Towards Agile HArdware and Software CO-design for Tensor
Computation},
journal = {CoRR},
volume = {abs/2105.01585},
year = {2021},
url = {https://arxiv.org/abs/2105.01585},
eprinttype = {arXiv},
eprint = {2105.01585},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2105-01585.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2105-01892,
author = {Liqiang Lu and
Naiqing Guan and
Yuyue Wang and
Liancheng Jia and
Zizhang Luo and
Jieming Yin and
Jason Cong and
Yun Liang},
title = {{TENET:} {A} Framework for Modeling Tensor Dataflow Based on Relation-centric
Notation},
journal = {CoRR},
volume = {abs/2105.01892},
year = {2021},
url = {https://arxiv.org/abs/2105.01892},
eprinttype = {arXiv},
eprint = {2105.01892},
timestamp = {Thu, 18 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2105-01892.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2110-03901,
author = {Yangjie Zhou and
Mengtian Yang and
Cong Guo and
Jingwen Leng and
Yun Liang and
Quan Chen and
Minyi Guo and
Yuhao Zhu},
title = {Characterizing and Demystifying the Implicit Convolution Algorithm
on Commercial Matrix-Multiplication Accelerators},
journal = {CoRR},
volume = {abs/2110.03901},
year = {2021},
url = {https://arxiv.org/abs/2110.03901},
eprinttype = {arXiv},
eprint = {2110.03901},
timestamp = {Wed, 19 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2110-03901.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/XiaoL20,
author = {Qingcheng Xiao and
Yun Liang},
title = {Fune: An {FPGA} Tuning Framework for {CNN} Acceleration},
journal = {{IEEE} Des. Test},
volume = {37},
number = {1},
pages = {46--55},
year = {2020},
url = {https://doi.org/10.1109/MDAT.2019.2908549},
doi = {10.1109/MDAT.2019.2908549},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/XiaoL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/JiaLWL20,
author = {Liancheng Jia and
Liqiang Lu and
Xuechao Wei and
Yun Liang},
title = {Generating Systolic Array Accelerators With Reusable Blocks},
journal = {{IEEE} Micro},
volume = {40},
number = {4},
pages = {85--92},
year = {2020},
url = {https://doi.org/10.1109/MM.2020.2997611},
doi = {10.1109/MM.2020.2997611},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/JiaLWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/JiaLLLY20,
author = {Liancheng Jia and
Yun Liang and
Xiuhong Li and
Liqiang Lu and
Shengen Yan},
title = {Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels},
journal = {{IEEE} Trans. Computers},
volume = {69},
number = {7},
pages = {986--997},
year = {2020},
url = {https://doi.org/10.1109/TC.2020.2973144},
doi = {10.1109/TC.2020.2973144},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/JiaLLLY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Yun Liang and
Liqiang Lu and
Qingcheng Xiao and
Shengen Yan},
title = {Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {4},
pages = {857--870},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2897701},
doi = {10.1109/TCAD.2019.2897701},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangLXY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoFSZLH20,
author = {Jieru Zhao and
Liang Feng and
Sharad Sinha and
Wei Zhang and
Yun Liang and
Bingsheng He},
title = {Performance Modeling and Directives Optimization for High-Level Synthesis
on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {7},
pages = {1428--1441},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2912916},
doi = {10.1109/TCAD.2019.2912916},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoFSZLH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuSZZZLWCD20,
author = {Jingchen Zhu and
Guangyu Sun and
Xian Zhang and
Chao Zhang and
Weiqi Zhang and
Yun Liang and
Tao Wang and
Yiran Chen and
Jia Di},
title = {Fork Path: Batching {ORAM} Requests to Remove Redundant Memory Accesses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {10},
pages = {2279--2292},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2948914},
doi = {10.1109/TCAD.2019.2948914},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuSZZZLWCD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/Zheng0WCS20,
author = {Size Zheng and
Yun Liang and
Shuo Wang and
Renze Chen and
Kaiwen Sheng},
editor = {James R. Larus and
Luis Ceze and
Karin Strauss},
title = {FlexTensor: An Automatic Schedule Exploration and Optimization Framework
for Tensor Computation on Heterogeneous System},
booktitle = {{ASPLOS} '20: Architectural Support for Programming Languages and
Operating Systems, Lausanne, Switzerland, March 16-20, 2020},
pages = {859--873},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373376.3378508},
doi = {10.1145/3373376.3378508},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asplos/Zheng0WCS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XiaoLX020,
author = {Qingcheng Xiao and
Liqiang Lu and
Jiaming Xie and
Yun Liang},
title = {FCNNLib: An Efficient and Flexible Convolution Algorithm Library on
FPGAs},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218748},
doi = {10.1109/DAC18072.2020.9218748},
timestamp = {Wed, 14 Oct 2020 10:56:17 +0200},
biburl = {https://dblp.org/rec/conf/dac/XiaoLX020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YangLSLJJ20,
author = {Tao Yang and
Yunkun Liao and
Jianping Shi and
Yun Liang and
Naifeng Jing and
Li Jiang},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Miquel Peric{\`{a}}s and
Ioannis Sourdis},
title = {A Winograd-Based {CNN} Accelerator with a Fine-Grained Regular Sparsity
Pattern},
booktitle = {30th International Conference on Field-Programmable Logic and Applications,
{FPL} 2020, Gothenburg, Sweden, August 31 - September 4, 2020},
pages = {254--261},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FPL50879.2020.00050},
doi = {10.1109/FPL50879.2020.00050},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YangLSLJJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LaiRZZCJ0SZ0ZCG20,
author = {Yi{-}Hsiang Lai and
Hongbo Rong and
Size Zheng and
Weihao Zhang and
Xiuping Cui and
Yunshan Jia and
Jie Wang and
Brendan Sullivan and
Zhiru Zhang and
Yun Liang and
Youhui Zhang and
Jason Cong and
Nithin George and
Jose Alvarez and
Christopher J. Hughes and
Pradeep Dubey},
title = {SuSy: {A} Programming Model for Productive Construction of High-Performance
Systolic Arrays on FPGAs},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {73:1--73:9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415644},
doi = {10.1145/3400302.3415644},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LaiRZZCJ0SZ0ZCG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Hongbo Rong and
Xiaochen Hao and
Yun Liang and
Lidong Xu and
Hong H. Jiang and
Pradeep Dubey},
title = {Systolic Computing on GPUs for Productive Performance},
journal = {CoRR},
volume = {abs/2010.15884},
year = {2020},
url = {https://arxiv.org/abs/2010.15884},
eprinttype = {arXiv},
eprint = {2010.15884},
timestamp = {Thu, 05 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2010-15884.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/appt/Xie019,
author = {Jiaming Xie and
Yun Liang},
editor = {Pen{-}Chung Yew and
Per Stenstr{\"{o}}m and
Junjie Wu and
Xiaoli Gong and
Tao Li},
title = {{SPART:} Optimizing CNNs by Utilizing Both Sparsity of Weights and
Feature Maps},
booktitle = {Advanced Parallel Processing Technologies - 13th International Symposium,
{APPT} 2019, Tianjin, China, August 15-16, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11719},
pages = {71--85},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-29611-7\_6},
doi = {10.1007/978-3-030-29611-7\_6},
timestamp = {Wed, 14 Aug 2019 16:04:08 +0200},
biburl = {https://dblp.org/rec/conf/appt/Xie019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/dac/Wei0C19,
author = {Xuechao Wei and
Yun Liang and
Jason Cong},
title = {Overcoming Data Transfer Bottlenecks in FPGA-based {DNN} Accelerators
via Layer Conscious Memory Management},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {125},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317875},
doi = {10.1145/3316781.3317875},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/Wei0C19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/dac/ShiLSWL19,
author = {Runbin Shi and
Junjie Liu and
Hayden Kwok{-}Hay So and
Shuo Wang and
Yun Liang},
title = {{E-LSTM:} Efficient Inference of Sparse {LSTM} on Embedded Heterogeneous
System},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {182},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317813},
doi = {10.1145/3316781.3317813},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/ShiLSWL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/emnlp/XuZYZLS19,
author = {Jingjing Xu and
Liang Zhao and
Hanqi Yan and
Qi Zeng and
Yun Liang and
Xu Sun},
editor = {Kentaro Inui and
Jing Jiang and
Vincent Ng and
Xiaojun Wan},
title = {LexicalAT: Lexical-Based Adversarial Reinforcement Training for Robust
Sentiment Classification},
booktitle = {Proceedings of the 2019 Conference on Empirical Methods in Natural
Language Processing and the 9th International Joint Conference on
Natural Language Processing, {EMNLP-IJCNLP} 2019, Hong Kong, China,
November 3-7, 2019},
pages = {5517--5526},
publisher = {Association for Computational Linguistics},
year = {2019},
url = {https://doi.org/10.18653/v1/D19-1554},
doi = {10.18653/V1/D19-1554},
timestamp = {Tue, 02 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/emnlp/XuZYZLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/fccm/LuXHZL019,
author = {Liqiang Lu and
Jiaming Xie and
Ruirui Huang and
Jiansong Zhang and
Wei Lin and
Yun Liang},
title = {An Efficient Hardware Accelerator for Sparse Convolutional Neural
Networks on FPGAs},
booktitle = {27th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May
1, 2019},
pages = {17--25},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FCCM.2019.00013},
doi = {10.1109/FCCM.2019.00013},
timestamp = {Mon, 12 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fccm/LuXHZL019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/fpga/DingWLXW019,
author = {Caiwen Ding and
Shuo Wang and
Ning Liu and
Kaidi Xu and
Yanzhi Wang and
Yun Liang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{REQ-YOLO:} {A} Resource-Aware, Efficient Quantization Framework for
Object Detection on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {33--42},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293904},
doi = {10.1145/3289602.3293904},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DingWLXW019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Wei0ZYC19,
author = {Xuechao Wei and
Yun Liang and
Peng Zhang and
Cody Hao Yu and
Jason Cong},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Overcoming Data Transfer Bottlenecks in {DNN} Accelerators via Layer-Conscious
Memory Managment},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {120},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293947},
doi = {10.1145/3289602.3293947},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Wei0ZYC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Lu0HLCZ19,
author = {Liqiang Lu and
Yun Liang and
Ruirui Huang and
Wei Lin and
Xiaoyuan Cui and
Jiansong Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Speedy: An Accelerator for Sparse Convolutional Neural Networks on
FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {187},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293970},
doi = {10.1145/3289602.3293970},
timestamp = {Mon, 12 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Lu0HLCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/hpca/Wang0Z19,
author = {Shuo Wang and
Yun Liang and
Wei Zhang},
title = {Poly: Efficient Heterogeneous System and Application Management for
Interactive Applications},
booktitle = {25th {IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2019, Washington, DC, USA, February 16-20, 2019},
pages = {199--210},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/HPCA.2019.00038},
doi = {10.1109/HPCA.2019.00038},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/Wang0Z19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/hpdc/Xie0LT19,
author = {Xiaolong Xie and
Yun Liang and
Xiuhong Li and
Wei Tan},
editor = {Jon B. Weissman and
Ali Raza Butt and
Evgenia Smirni},
title = {CuLDA: Solving Large-scale {LDA} Problems on GPUs},
booktitle = {Proceedings of the 28th International Symposium on High-Performance
Parallel and Distributed Computing, {HPDC} 2019, Phoenix, AZ, USA,
June 22-29, 2019},
pages = {195--205},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3307681.3325407},
doi = {10.1145/3307681.3325407},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpdc/Xie0LT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/iccad/XiaoL19,
author = {Qingcheng Xiao and
Yun Liang},
editor = {David Z. Pan},
title = {Zac: Towards Automatic Optimization and Deployment of Quantized Deep
Neural Networks on Embedded Devices},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942058},
doi = {10.1109/ICCAD45719.2019.8942058},
timestamp = {Wed, 19 Feb 2020 16:38:01 +0100},
biburl = {https://dblp.org/rec/conf/iccad/XiaoL19.bib},
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@inproceedings{DBLP:conf/icpads/XiaZMLZ0S19,
author = {Xu Xia and
Lei Zhang and
Chengli Mei and
Jinyan Li and
Xuetian Zhu and
Yun Liang and
Jeffrey Song},
title = {A Survey on 5G Network Slicing Enabling the Smart Grid},
booktitle = {25th {IEEE} International Conference on Parallel and Distributed Systems,
{ICPADS} 2019, Tianjin, China, December 4-6, 2019},
pages = {911--916},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICPADS47876.2019.00134},
doi = {10.1109/ICPADS47876.2019.00134},
timestamp = {Tue, 04 Feb 2020 13:36:54 +0100},
biburl = {https://dblp.org/rec/conf/icpads/XiaZMLZ0S19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/iscas/ZhangZLW0C19,
author = {Jiaxi Zhang and
Wentai Zhang and
Guojie Luo and
Xuechao Wei and
Yun Liang and
Jason Cong},
title = {Frequency Improvement of Systolic Array-Based CNNs on FPGAs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702071},
doi = {10.1109/ISCAS.2019.8702071},
timestamp = {Mon, 19 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ZhangZLW0C19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ppopp/Li0YJL19,
author = {Xiuhong Li and
Yun Liang and
Shengen Yan and
Liancheng Jia and
Yinghan Li},
editor = {Jeffrey K. Hollingsworth and
Idit Keidar},
title = {A coordinated tiling and batching framework for efficient {GEMM} on
GPUs},
booktitle = {Proceedings of the 24th {ACM} {SIGPLAN} Symposium on Principles and
Practice of Parallel Programming, PPoPP 2019, Washington, DC, USA,
February 16-20, 2019},
pages = {229--241},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3293883.3295734},
doi = {10.1145/3293883.3295734},
timestamp = {Sun, 12 Jun 2022 19:46:08 +0200},
biburl = {https://dblp.org/rec/conf/ppopp/Li0YJL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/ppopp/Xie0LT19,
author = {Xiaolong Xie and
Yun Liang and
Xiuhong Li and
Wei Tan},
editor = {Jeffrey K. Hollingsworth and
Idit Keidar},
title = {CuLDA{\_}CGS: solving large-scale {LDA} problems on GPUs},
booktitle = {Proceedings of the 24th {ACM} {SIGPLAN} Symposium on Principles and
Practice of Parallel Programming, PPoPP 2019, Washington, DC, USA,
February 16-20, 2019},
pages = {435--436},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3293883.3301496},
doi = {10.1145/3293883.3301496},
timestamp = {Sun, 12 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ppopp/Xie0LT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Caiwen Ding and
Shuo Wang and
Ning Liu and
Kaidi Xu and
Yanzhi Wang and
Yun Liang},
title = {{REQ-YOLO:} {A} Resource-Aware, Efficient Quantization Framework for
Object Detection on FPGAs},
journal = {CoRR},
volume = {abs/1909.13396},
year = {2019},
url = {http://arxiv.org/abs/1909.13396},
eprinttype = {arXiv},
eprint = {1909.13396},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1909-13396.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Zhenxin Fu and
Lei Yang and
Wenbin Hou and
Zhuohan Li and
Yifan Wu and
Yihua Cheng and
Xiaolin Wang and
Yun Liang},
title = {Student Cluster Competition 2017, Team Peking University: Reproducing
vectorization of the Tersoff multi-body potential on the Intel Broadwell
architecture},
journal = {Parallel Comput.},
volume = {78},
pages = {28--32},
year = {2018},
url = {https://doi.org/10.1016/j.parco.2018.06.010},
doi = {10.1016/J.PARCO.2018.06.010},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/FuYHLWCWL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Xiaolong Xie and
Yun Liang and
Xiuhong Li and
Yudong Wu and
Guangyu Sun and
Tao Wang and
Dongrui Fan},
title = {{CRAT:} Enabling Coordinated Register Allocation and Thread-Level
Parallelism Optimization for GPUs},
journal = {{IEEE} Trans. Computers},
volume = {67},
number = {6},
pages = {890--897},
year = {2018},
url = {https://doi.org/10.1109/TC.2017.2776272},
doi = {10.1109/TC.2017.2776272},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/XieLLWSWF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/LiangWZ18,
author = {Yun Liang and
Shuo Wang and
Wei Zhang},
title = {FlexCL: {A} Model of Performance and Power for OpenCL Workloads on
FPGAs},
journal = {{IEEE} Trans. Computers},
volume = {67},
number = {12},
pages = {1750--1764},
year = {2018},
url = {https://doi.org/10.1109/TC.2018.2840686},
doi = {10.1109/TC.2018.2840686},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/LiangWZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangXWSW18,
author = {Yun Liang and
Xiaolong Xie and
Yu Wang and
Guangyu Sun and
Tao Wang},
title = {Optimizing Cache Bypassing and Warp Scheduling for GPUs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1560--1573},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2764886},
doi = {10.1109/TCAD.2017.2764886},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangXWSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/XieDLLTOLHG18,
author = {Xinfeng Xie and
Dayou Du and
Qian Li and
Yun Liang and
Wai Teng Tang and
Zhongliang Ong and
Mian Lu and
Huynh Phung Huynh and
Rick Siow Mong Goh},
title = {Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based
Applications on Mobile SoCs},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {17},
number = {2},
pages = {37:1--37:25},
year = {2018},
url = {https://doi.org/10.1145/3122788},
doi = {10.1145/3122788},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/XieDLLTOLHG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aca/LiangWMH18,
author = {Yun Liang and
Shuo Wang and
Tulika Mitra and
Yajun Ha},
editor = {Chao Li and
Junjie Wu},
title = {Analytical Two-Level Near Threshold Cache Exploration for Low Power
Biomedical Applications},
booktitle = {Advanced Computer Architecture - 12th Conference, {ACA} 2018, Yingkou,
China, August 10-11, 2018, Proceedings},
series = {Communications in Computer and Information Science},
volume = {908},
pages = {95--108},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-981-13-2423-9\_8},
doi = {10.1007/978-981-13-2423-9\_8},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aca/LiangWMH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Lu018,
author = {Liqiang Lu and
Yun Liang},
title = {SpWA: an efficient sparse winograd convolutional neural networks accelerator
on FPGAs},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {135:1--135:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196120},
doi = {10.1145/3195970.3196120},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/dac/Lu018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/FengSZ018,
author = {Liang Feng and
Sharad Sinha and
Wei Zhang and
Yun Liang},
title = {{CAMAS:} Static and Dynamic Hybrid Cache Management for {CPU-FPGA}
Platforms},
booktitle = {26th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May
1, 2018},
pages = {165--172},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FCCM.2018.00034},
doi = {10.1109/FCCM.2018.00034},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/FengSZ018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Wang0DYQW018,
author = {Shuo Wang and
Zhe Li and
Caiwen Ding and
Bo Yuan and
Qinru Qiu and
Yanzhi Wang and
Yun Liang},
editor = {Jason Helge Anderson and
Kia Bazargan},
title = {{C-LSTM:} Enabling Efficient {LSTM} using Structured Compression Techniques
on FPGAs},
booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
pages = {11--20},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3174243.3174253},
doi = {10.1145/3174243.3174253},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Wang0DYQW018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/Wei0LYZC18,
author = {Xuechao Wei and
Yun Liang and
Xiuhong Li and
Cody Hao Yu and
Peng Zhang and
Jason Cong},
editor = {Iris Bahar},
title = {{TGPA:} tile-grained pipeline architecture for low latency {CNN} inference},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {58},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240856},
doi = {10.1145/3240765.3240856},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/iccad/Wei0LYZC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iclr/0001WDQW018,
author = {Zhe Li and
Shuo Wang and
Caiwen Ding and
Qinru Qiu and
Yanzhi Wang and
Yun Liang},
title = {Efficient Recurrent Neural Networks using Structured Matrices in FPGAs},
booktitle = {6th International Conference on Learning Representations, {ICLR} 2018,
Vancouver, BC, Canada, April 30 - May 3, 2018, Workshop Track Proceedings},
publisher = {OpenReview.net},
year = {2018},
url = {https://openreview.net/forum?id=SJgAA3AUG},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iclr/0001WDQW018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/Li0ZLLLJ18,
author = {Xiuhong Li and
Yun Liang and
Wentai Zhang and
Taide Liu and
Haochen Li and
Guojie Luo and
Ming Jiang},
title = {cuMBIR: An Efficient Framework for Low-dose X-ray {CT} Image Reconstruction
on GPUs},
booktitle = {Proceedings of the 32nd International Conference on Supercomputing,
{ICS} 2018, Beijing, China, June 12-15, 2018},
pages = {184--194},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3205289.3205309},
doi = {10.1145/3205289.3205309},
timestamp = {Thu, 02 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ics/Li0ZLLLJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1803-04631,
author = {Xiaolong Xie and
Yun Liang and
Xiuhong Li and
Wei Tan},
title = {CuLDA{\_}CGS: Solving Large-scale {LDA} Problems on GPUs},
journal = {CoRR},
volume = {abs/1803.04631},
year = {2018},
url = {http://arxiv.org/abs/1803.04631},
eprinttype = {arXiv},
eprint = {1803.04631},
timestamp = {Mon, 30 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1803-04631.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1803-06305,
author = {Shuo Wang and
Zhe Li and
Caiwen Ding and
Bo Yuan and
Yanzhi Wang and
Qinru Qiu and
Yun Liang},
title = {{C-LSTM:} Enabling Efficient {LSTM} using Structured Compression Techniques
on FPGAs},
journal = {CoRR},
volume = {abs/1803.06305},
year = {2018},
url = {http://arxiv.org/abs/1803.06305},
eprinttype = {arXiv},
eprint = {1803.06305},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1803-06305.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1803-07661,
author = {Zhe Li and
Shuo Wang and
Caiwen Ding and
Qinru Qiu and
Yanzhi Wang and
Yun Liang},
title = {Efficient Recurrent Neural Networks using Structured Matrices in FPGAs},
journal = {CoRR},
volume = {abs/1803.07661},
year = {2018},
url = {http://arxiv.org/abs/1803.07661},
eprinttype = {arXiv},
eprint = {1803.07661},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1803-07661.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1811-01907,
author = {Shaokai Ye and
Tianyun Zhang and
Kaiqi Zhang and
Jiayu Li and
Jiaming Xie and
Yun Liang and
Sijia Liu and
Xue Lin and
Yanzhi Wang},
title = {A Unified Framework of {DNN} Weight Pruning and Weight Clustering/Quantization
Using {ADMM}},
journal = {CoRR},
volume = {abs/1811.01907},
year = {2018},
url = {http://arxiv.org/abs/1811.01907},
eprinttype = {arXiv},
eprint = {1811.01907},
timestamp = {Thu, 03 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1811-01907.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pc/YangLFLHWWL17,
author = {Lei Yang and
Yilong Li and
Zhenxin Fu and
Zhuohan Li and
Wenbin Hou and
Haoze Wu and
Xiaolin Wang and
Yun Liang},
title = {ParConnect reproducibility report},
journal = {Parallel Comput.},
volume = {70},
pages = {22--26},
year = {2017},
url = {https://doi.org/10.1016/j.parco.2017.07.006},
doi = {10.1016/J.PARCO.2017.07.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pc/YangLFLHWWL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/tcad/LiangTZLHG17,
author = {Yun Liang and
Wai Teng Tang and
Ruizhe Zhao and
Mian Lu and
Huynh Phung Huynh and
Rick Siow Mong Goh},
title = {Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {12},
pages = {2106--2119},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2017.2681072},
doi = {10.1109/TCAD.2017.2681072},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangTZLHG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/LiangL17,
author = {Yun Liang and
Xiuhong Li},
title = {Efficient Kernel Management on GPUs},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {16},
number = {4},
pages = {115:1--115:24},
year = {2017},
url = {https://doi.org/10.1145/3070710},
doi = {10.1145/3070710},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/LiangL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WeiLWLC17,
author = {Xuechao Wei and
Yun Liang and
Tao Wang and
Songwu Lu and
Jason Cong},
title = {Throughput optimization for streaming applications on {CPU-FPGA} heterogeneous
systems},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {488--493},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858370},
doi = {10.1109/ASPDAC.2017.7858370},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WeiLWLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/Liang17,
author = {Yun Liang},
title = {Programming FPGAs Using OpenCL from Performance Model to Application
Study},
booktitle = {Proceedings of the first Workshop on Emerging Technologies for software-defined
and reconfigurable hardware-accelerated Cloud Datacenters, ETCD@ASPLOS
2017, Xi'an, China, April 8, 2017},
pages = {11:1},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3129457.3129502},
doi = {10.1145/3129457.3129502},
timestamp = {Tue, 06 Nov 2018 11:07:42 +0100},
biburl = {https://dblp.org/rec/conf/asplos/Liang17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/dac/WangLZ17,
author = {Shuo Wang and
Yun Liang and
Wei Zhang},
title = {FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible
FPGAs},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {27:1--27:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062251},
doi = {10.1145/3061639.3062251},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WangLZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangL17,
author = {Shuo Wang and
Yun Liang},
title = {A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs
using OpenCL Model},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {28:1--28:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062185},
doi = {10.1145/3061639.3062185},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WangL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WeiYZCWHLC17,
author = {Xuechao Wei and
Cody Hao Yu and
Peng Zhang and
Youxiang Chen and
Yuxin Wang and
Han Hu and
Yun Liang and
Jason Cong},
title = {Automated Systolic Array Architecture Synthesis for High Throughput
{CNN} Inference on FPGAs},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {29:1--29:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062207},
doi = {10.1145/3061639.3062207},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WeiYZCWHLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XiaoLLYT17,
author = {Qingcheng Xiao and
Yun Liang and
Liqiang Lu and
Shengen Yan and
Yu{-}Wing Tai},
title = {Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional
Neural Networks on FPGAs},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {62:1--62:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062244},
doi = {10.1145/3061639.3062244},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/XiaoLLYT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZhongPWLMN17,
author = {Guanwen Zhong and
Alok Prakash and
Siqi Wang and
Yun Liang and
Tulika Mitra and
Sma{\"{\i}}l Niar},
editor = {David Atienza and
Giorgio Di Natale},
title = {Design Space exploration of FPGA-based accelerators with multi-level
parallelism},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1141--1146},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927161},
doi = {10.23919/DATE.2017.7927161},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ZhongPWLMN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/LuLXY17,
author = {Liqiang Lu and
Yun Liang and
Qingcheng Xiao and
Shengen Yan},
title = {Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs},
booktitle = {25th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2017, Napa, CA, USA, April 30 - May 2,
2017},
pages = {101--108},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/FCCM.2017.64},
doi = {10.1109/FCCM.2017.64},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/LuLXY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WangL17,
author = {Shuo Wang and
Yun Liang},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from
OpenCL Programming Model (Abstract Only)},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {285--286},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021761},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WangL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpdc/XieTFL17,
author = {Xiaolong Xie and
Wei Tan and
Liana L. Fong and
Yun Liang},
editor = {H. Howie Huang and
Jon B. Weissman and
Adriana Iamnitchi and
Alexandru Iosup},
title = {CuMF{\_}SGD: Parallelized Stochastic Gradient Descent for Matrix Factorization
on GPUs},
booktitle = {Proceedings of the 26th International Symposium on High-Performance
Parallel and Distributed Computing, {HPDC} 2017, Washington, DC, USA,
June 26-30, 2017},
pages = {79--92},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3078597.3078602},
doi = {10.1145/3078597.3078602},
timestamp = {Tue, 06 Nov 2018 11:07:20 +0100},
biburl = {https://dblp.org/rec/conf/hpdc/XieTFL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/0001LX17,
author = {Yun Liang and
Xiuhong Li and
Xiaolong Xie},
editor = {Sri Parameswaran},
title = {Exploring cache bypassing and partitioning for multi-tasking on GPUs},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {9--16},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203754},
doi = {10.1109/ICCAD.2017.8203754},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/0001LX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhaoFSZLH17,
author = {Jieru Zhao and
Liang Feng and
Sharad Sinha and
Wei Zhang and
Yun Liang and
Bingsheng He},
editor = {Sri Parameswaran},
title = {{COMBA:} {A} comprehensive model-based analysis framework for high
level synthesis of real applications},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {430--437},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203809},
doi = {10.1109/ICCAD.2017.8203809},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhaoFSZLH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/FengSZL17,
author = {Liang Feng and
Sharad Sinha and
Wei Zhang and
Yun Liang},
editor = {Sri Parameswaran},
title = {A hybrid approach to cache management in heterogeneous {CPU-FPGA}
platforms},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {937--944},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203881},
doi = {10.1109/ICCAD.2017.8203881},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/FengSZL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/LiX017,
author = {Qian Li and
Qingcheng Xiao and
Yun Liang},
title = {Enabling high performance deep learning networks on embedded systems},
booktitle = {{IECON} 2017 - 43rd Annual Conference of the {IEEE} Industrial Electronics
Society, Beijing, China, October 29 - November 1, 2017},
pages = {8405--8410},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/IECON.2017.8217476},
doi = {10.1109/IECON.2017.8217476},
timestamp = {Tue, 26 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iecon/LiX017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/LiangW16,
author = {Yun Liang and
Shuo Wang},
title = {Performance-Centric Optimization for Racetrack Memory Based Register
File on GPUs},
journal = {J. Comput. Sci. Technol.},
volume = {31},
number = {1},
pages = {36--49},
year = {2016},
url = {https://doi.org/10.1007/s11390-016-1610-1},
doi = {10.1007/S11390-016-1610-1},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcst/LiangW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangSRC16,
author = {Yun Liang and
Muhammad Teguh Satria and
Kyle Rupnow and
Deming Chen},
title = {An Accurate {GPU} Performance Model for Effective Control Flow Divergence
Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {7},
pages = {1165--1178},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2501303},
doi = {10.1109/TCAD.2015.2501303},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangSRC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenNCGLRCHC16,
author = {Ying Chen and
Tan Nguyen and
Yao Chen and
Swathi T. Gurumani and
Yun Liang and
Kyle Rupnow and
Jason Cong and
Wen{-}mei W. Hwu and
Deming Chen},
title = {{FCUDA-HB:} Hierarchical and Scalable Bus Architecture Generation
on FPGAs With the {FCUDA} Flow},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {12},
pages = {2032--2045},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2016.2552821},
doi = {10.1109/TCAD.2016.2552821},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenNCGLRCHC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenGLLGRC16,
author = {Yao Chen and
Swathi T. Gurumani and
Yun Liang and
Guofeng Li and
Donghui Guo and
Kyle Rupnow and
Deming Chen},
title = {FCUDA-NoC: {A} Scalable and Efficient Network-on-Chip Implementation
for the CUDA-to-FPGA Flow},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {6},
pages = {2220--2233},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2497259},
doi = {10.1109/TVLSI.2015.2497259},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenGLLGRC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangLZXSLWL16,
author = {Shuo Wang and
Yun Liang and
Chao Zhang and
Xiaolong Xie and
Guangyu Sun and
Yongpan Liu and
Yu Wang and
Xiuhong Li},
title = {Performance-centric register file design for GPUs using racetrack
memory},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {25--30},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7427984},
doi = {10.1109/ASPDAC.2016.7427984},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WangLZXSLWL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhongPLMN16,
author = {Guanwen Zhong and
Alok Prakash and
Yun Liang and
Tulika Mitra and
Sma{\"{\i}}l Niar},
title = {Lin-analyzer: a high-level performance analysis tool for FPGA-based
accelerators},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {136:1--136:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898040},
doi = {10.1145/2897937.2898040},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhongPLMN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LiL16,
author = {Xiuhong Li and
Yun Liang},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Efficient kernel management on GPUs},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {85--90},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459285/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LiL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/XieTFL16,
author = {Xiaolong Xie and
Wei Tan and
Liana L. Fong and
Yun Liang},
title = {CuMF{\_}SGD: Fast and Scalable Matrix Factorization},
journal = {CoRR},
volume = {abs/1610.05838},
year = {2016},
url = {http://arxiv.org/abs/1610.05838},
eprinttype = {arXiv},
eprint = {1610.05838},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/XieTFL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangMJ15,
author = {Yun Liang and
Tulika Mitra and
Lei Ju},
title = {Instruction Cache Locking Using Temporal Reuse Profile},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {9},
pages = {1387--1400},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2418320},
doi = {10.1109/TCAD.2015.2418320},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiangMJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangXSC15,
author = {Yun Liang and
Xiaolong Xie and
Guangyu Sun and
Deming Chen},
title = {An Efficient Compiler Framework for Cache Bypassing on GPUs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {10},
pages = {1677--1690},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2424962},
doi = {10.1109/TCAD.2015.2424962},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangXSC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/LiangHRGC15,
author = {Yun Liang and
Huynh Phung Huynh and
Kyle Rupnow and
Rick Siow Mong Goh and
Deming Chen},
title = {Efficient {GPU} Spatial-Temporal Multitasking},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {26},
number = {3},
pages = {748--760},
year = {2015},
url = {https://doi.org/10.1109/TPDS.2014.2313342},
doi = {10.1109/TPDS.2014.2313342},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/LiangHRGC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/LuLHOHG15,
author = {Mian Lu and
Yun Liang and
Huynh Phung Huynh and
Zhongliang Ong and
Bingsheng He and
Rick Siow Mong Goh},
title = {MrPhi: An Optimized MapReduce Framework on Intel Xeon Phi Coprocessors},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {26},
number = {11},
pages = {3066--3078},
year = {2015},
url = {https://doi.org/10.1109/TPDS.2014.2365784},
doi = {10.1109/TPDS.2014.2365784},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/LuLHOHG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/0001W15,
author = {Yun Liang and
Shuo Wang},
title = {Quantitative performance and power analysis of {LTE} using high level
synthesis},
booktitle = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015,
Chengdu, China, November 3-6, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASICON.2015.7517024},
doi = {10.1109/ASICON.2015.7517024},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asicon/0001W15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cgo/TangZLLHLG15,
author = {Wai Teng Tang and
Ruizhe Zhao and
Mian Lu and
Yun Liang and
Huynh Phung Huyng and
Xibai Li and
Rick Siow Mong Goh},
editor = {Kunle Olukotun and
Aaron Smith and
Robert Hundt and
Jason Mars},
title = {Optimizing and auto-tuning scale-free sparse matrix-vector multiplication
on Intel Xeon Phi},
booktitle = {Proceedings of the 13th Annual {IEEE/ACM} International Symposium
on Code Generation and Optimization, {CGO} 2015, San Francisco, CA,
USA, February 07 - 11, 2015},
pages = {136--145},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/CGO.2015.7054194},
doi = {10.1109/CGO.2015.7054194},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cgo/TangZLLHLG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/XieLWSW15,
author = {Xiaolong Xie and
Yun Liang and
Yu Wang and
Guangyu Sun and
Tao Wang},
title = {Coordinated static and dynamic cache bypassing for GPUs},
booktitle = {21st {IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2015, Burlingame, CA, USA, February 7-11, 2015},
pages = {76--88},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/HPCA.2015.7056023},
doi = {10.1109/HPCA.2015.7056023},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/XieLWSW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ZhangSZZZWLLWS15,
author = {Chao Zhang and
Guangyu Sun and
Xian Zhang and
Weiqi Zhang and
Weisheng Zhao and
Tao Wang and
Yun Liang and
Yongpan Liu and
Yu Wang and
Jiwu Shu},
editor = {Deborah T. Marr and
David H. Albonesi},
title = {Hi-fi playback: tolerating position errors in shift operations of
racetrack memory},
booktitle = {Proceedings of the 42nd Annual International Symposium on Computer
Architecture, Portland, OR, USA, June 13-17, 2015},
pages = {694--706},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2749469.2750388},
doi = {10.1145/2749469.2750388},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/ZhangSZZZWLLWS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ZhangSZZLWCD15,
author = {Xian Zhang and
Guangyu Sun and
Chao Zhang and
Weiqi Zhang and
Yun Liang and
Tao Wang and
Yiran Chen and
Jia Di},
editor = {Milos Prvulovic},
title = {Fork path: improving efficiency of {ORAM} by removing redundant memory
accesses},
booktitle = {Proceedings of the 48th International Symposium on Microarchitecture,
{MICRO} 2015, Waikiki, HI, USA, December 5-9, 2015},
pages = {102--114},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2830772.2830787},
doi = {10.1145/2830772.2830787},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/ZhangSZZLWCD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/XieLLWSWF15,
author = {Xiaolong Xie and
Yun Liang and
Xiuhong Li and
Yudong Wu and
Guangyu Sun and
Tao Wang and
Dongrui Fan},
editor = {Milos Prvulovic},
title = {Enabling coordinated register allocation and thread-level parallelism
optimization for GPUs},
booktitle = {Proceedings of the 48th International Symposium on Microarchitecture,
{MICRO} 2015, Waikiki, HI, USA, December 5-9, 2015},
pages = {395--406},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2830772.2830813},
doi = {10.1145/2830772.2830813},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/micro/XieLLWSWF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenWLXY14,
author = {Xiaoming Chen and
Yu Wang and
Yun Liang and
Yuan Xie and
Huazhong Yang},
title = {Run-Time Technique for Simultaneous Aging and Power Optimization in
GPGPUs},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {168:1--168:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593208},
doi = {10.1145/2593069.2593208},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChenWLXY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DingLM14,
author = {Huping Ding and
Yun Liang and
Tulika Mitra},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {WCET-Centric dynamic instruction cache locking},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.040},
doi = {10.7873/DATE.2014.040},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/DingLM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/GurumaniTCLRC14,
author = {Swathi T. Gurumani and
Jacob Tolar and
Yao Chen and
Yun Liang and
Kyle Rupnow and
Deming Chen},
title = {Integrated CUDA-to-FPGA Synthesis with Network-on-Chip},
booktitle = {22nd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2014, Boston, MA, USA, May 11-13, 2014},
pages = {21--24},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/FCCM.2014.14},
doi = {10.1109/FCCM.2014.14},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fccm/GurumaniTCLRC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ZhongVLMN14,
author = {Guanwen Zhong and
Vanchinathan Venkataramani and
Yun Liang and
Tulika Mitra and
Sma{\"{\i}}l Niar},
title = {Design space exploration of multiple loops on FPGAs using high level
synthesis},
booktitle = {32nd {IEEE} International Conference on Computer Design, {ICCD} 2014,
Seoul, South Korea, October 19-22, 2014},
pages = {456--463},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ICCD.2014.6974719},
doi = {10.1109/ICCD.2014.6974719},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ZhongVLMN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfem/WuLL014,
author = {Zhimin Wu and
Yang Liu and
Yun Liang and
Jun Sun},
editor = {Stephan Merz and
Jun Pang},
title = {{GPU} Accelerated Counterexample Generation in {LTL} Model Checking},
booktitle = {Formal Methods and Software Engineering - 16th International Conference
on Formal Engineering Methods, {ICFEM} 2014, Luxembourg, Luxembourg,
November 3-5, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8829},
pages = {413--429},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-11737-9\_27},
doi = {10.1007/978-3-319-11737-9\_27},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icfem/WuLL014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DengLLS14,
author = {Jingyu Deng and
Yun Liang and
Guojie Luo and
Guangyu Sun},
title = {Rapid design space exploration of two-level unified caches},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {1937--1940},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865540},
doi = {10.1109/ISCAS.2014.6865540},
timestamp = {Mon, 16 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/DengLLS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/LiangM13,
author = {Yun Liang and
Tulika Mitra},
title = {An analytical approach for fast and accurate design space exploration
of instruction caches},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {13},
number = {3},
pages = {43:1--43:29},
year = {2013},
url = {https://doi.org/10.1145/2539036.2539039},
doi = {10.1145/2539036.2539039},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/LiangM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GurumaniCLRC13,
author = {Swathi T. Gurumani and
Hisham Cholakkal and
Yun Liang and
Kyle Rupnow and
Deming Chen},
title = {High-level synthesis of multiple dependent {CUDA} kernels on {FPGA}},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {305--312},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509613},
doi = {10.1109/ASPDAC.2013.6509613},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GurumaniCLRC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiangCRC13,
author = {Yun Liang and
Zheng Cui and
Kyle Rupnow and
Deming Chen},
title = {Register and thread structure optimization for GPUs},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {461--466},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509639},
doi = {10.1109/ASPDAC.2013.6509639},
timestamp = {Tue, 19 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiangCRC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DingLM13,
author = {Huping Ding and
Yun Liang and
Tulika Mitra},
title = {Shared cache aware task mapping for {WCRT} minimization},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {735--740},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509688},
doi = {10.1109/ASPDAC.2013.6509688},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/DingLM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bigdataconf/LuZHOLHGH13,
author = {Mian Lu and
Lei Zhang and
Huynh Phung Huynh and
Zhongliang Ong and
Yun Liang and
Bingsheng He and
Rick Siow Mong Goh and
Richard Huynh},
editor = {Xiaohua Hu and
Tsau Young Lin and
Vijay V. Raghavan and
Benjamin W. Wah and
Ricardo Baeza{-}Yates and
Geoffrey C. Fox and
Cyrus Shahabi and
Matthew Smith and
Qiang Yang and
Rayid Ghani and
Wei Fan and
Ronny Lempel and
Raghunath Nambiar},
title = {Optimizing the MapReduce framework on Intel Xeon Phi coprocessor},
booktitle = {2013 {IEEE} International Conference on Big Data {(IEEE} BigData 2013),
6-9 October 2013, Santa Clara, CA, {USA}},
pages = {125--130},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/BigData.2013.6691563},
doi = {10.1109/BIGDATA.2013.6691563},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/bigdataconf/LuZHOLHGH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PapakonstantinouCHCL13,
author = {Alexandros Papakonstantinou and
Deming Chen and
Wen{-}mei W. Hwu and
Jason Cong and
Yun Liang},
title = {Throughput-oriented kernel porting onto FPGAs},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {11:1--11:10},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488747},
doi = {10.1145/2463209.2488747},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PapakonstantinouCHCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DingLM13,
author = {Huping Ding and
Yun Liang and
Tulika Mitra},
title = {Integrated instruction cache analysis and locking in multitasking
real-time systems},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {147:1--147:10},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488916},
doi = {10.1145/2463209.2488916},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DingLM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZuoLLRCC13,
author = {Wei Zuo and
Yun Liang and
Peng Li and
Kyle Rupnow and
Deming Chen and
Jason Cong},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {Improving high level synthesis optimization opportunity through polyhedral
transformations},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {9--18},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435271},
doi = {10.1145/2435264.2435271},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ZuoLLRCC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XieLSC13,
author = {Xiaolong Xie and
Yun Liang and
Guangyu Sun and
Deming Chen},
editor = {J{\"{o}}rg Henkel},
title = {An efficient compiler framework for cache bypassing on GPUs},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
pages = {516--523},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICCAD.2013.6691165},
doi = {10.1109/ICCAD.2013.6691165},
timestamp = {Mon, 16 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/XieLSC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/LuZHOLHGH13,
author = {Mian Lu and
Lei Zhang and
Huynh Phung Huynh and
Zhongliang Ong and
Yun Liang and
Bingsheng He and
Rick Siow Mong Goh and
Richard Huynh},
title = {Optimizing the MapReduce Framework on Intel Xeon Phi Coprocessor},
journal = {CoRR},
volume = {abs/1309.0215},
year = {2013},
url = {http://arxiv.org/abs/1309.0215},
eprinttype = {arXiv},
eprint = {1309.0215},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/LuZHOLHGH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jece/LiangRLMDC12,
author = {Yun Liang and
Kyle Rupnow and
Yinan Li and
Dongbo Min and
Minh N. Do and
Deming Chen},
title = {High-Level Synthesis: Productivity, Performance, and Software Constraints},
journal = {J. Electr. Comput. Eng.},
volume = {2012},
pages = {649057:1--649057:14},
year = {2012},
url = {https://doi.org/10.1155/2012/649057},
doi = {10.1155/2012/649057},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jece/LiangRLMDC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/rts/LiangDMRLS12,
author = {Yun Liang and
Huping Ding and
Tulika Mitra and
Abhik Roychoudhury and
Yan Li and
Vivy Suhendra},
title = {Timing analysis of concurrent programs running on shared cache multi-cores},
journal = {Real Time Syst.},
volume = {48},
number = {6},
pages = {638--680},
year = {2012},
url = {https://doi.org/10.1007/s11241-012-9160-2},
doi = {10.1007/S11241-012-9160-2},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/rts/LiangDMRLS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DingLM12,
author = {Huping Ding and
Yun Liang and
Tulika Mitra},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {WCET-centric partial instruction cache locking},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {412--420},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228434},
doi = {10.1145/2228360.2228434},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DingLM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LiangCZRZJC12,
author = {Yun Liang and
Zheng Cui and
Shengkui Zhao and
Kyle Rupnow and
Yihao Zhang and
Douglas L. Jones and
Deming Chen},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Real-time implementation and performance optimization of 3D sound
localization on GPUs},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {832--835},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176610},
doi = {10.1109/DATE.2012.6176610},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/LiangCZRZJC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/CuiLRC12,
author = {Zheng Cui and
Yun Liang and
Kyle Rupnow and
Deming Chen},
title = {An Accurate {GPU} Performance Model for Effective Control Flow Divergence
Optimization},
booktitle = {26th {IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} 2012, Shanghai, China, May 21-25, 2012},
pages = {83--94},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/IPDPS.2012.18},
doi = {10.1109/IPDPS.2012.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/CuiLRC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/RupnowLLC11,
author = {Kyle Rupnow and
Yun Liang and
Yinan Li and
Deming Chen},
title = {A study of high-level synthesis: Promises and challenges},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {1102--1105},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157401},
doi = {10.1109/ASICON.2011.6157401},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/RupnowLLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/PapakonstantinouLSGCHC11,
author = {Alexandros Papakonstantinou and
Yun Liang and
John A. Stratton and
Karthik Gururaj and
Deming Chen and
Wen{-}mei W. Hwu and
Jason Cong},
editor = {Paul Chow and
Michael J. Wirthlin},
title = {Multilevel Granularity Parallelism Synthesis on FPGAs},
booktitle = {{IEEE} 19th Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2011, Salt Lake City, Utah, USA, 1-3 May
2011},
pages = {178--185},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FCCM.2011.29},
doi = {10.1109/FCCM.2011.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/PapakonstantinouLSGCHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/RupnowLLMDC11,
author = {Kyle Rupnow and
Yun Liang and
Yinan Li and
Dongbo Min and
Minh N. Do and
Deming Chen},
editor = {Russell Tessier},
title = {High level synthesis of stereo matching: Productivity, performance,
and software constraints},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--8},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6132716},
doi = {10.1109/FPT.2011.6132716},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/RupnowLLMDC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/LiangM10,
author = {Yun Liang and
Tulika Mitra},
editor = {Vinod Kathail and
Reid Tatge and
Rajeev Barua},
title = {Improved procedure placement for set associative caches},
booktitle = {Proceedings of the 2010 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2010, Scottsdale, AZ,
USA, October 24-29, 2010},
pages = {147--156},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1878921.1878944},
doi = {10.1145/1878921.1878944},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/LiangM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiangM10,
author = {Yun Liang and
Tulika Mitra},
editor = {Sachin S. Sapatnekar},
title = {Instruction cache locking using temporal reuse profile},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {344--349},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837362},
doi = {10.1145/1837274.1837362},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiangM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HuynhLM10,
author = {Huynh Phung Huynh and
Yun Liang and
Tulika Mitra},
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {Efficient custom instructions generation for system-level design},
booktitle = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
pages = {445--448},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/FPT.2010.5681456},
doi = {10.1109/FPT.2010.5681456},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/HuynhLM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icaart/DuLMLZ10,
author = {Bowen Du and
Yun Liang and
Dianfu Ma and
Weifeng Lv and
Tongyu Zhu},
editor = {Joaquim Filipe and
Ana L. N. Fred and
Bernadette Sharp},
title = {An Efficient Algorithm to Estimate Real-time Traffic Information based
on Multiple Data Sources},
booktitle = {{ICAART} 2010 - Proceedings of the International Conference on Agents
and Artificial Intelligence, Volume 1 - Artificial Intelligence, Valencia,
Spain, January 22-24, 2010},
pages = {507--510},
publisher = {{INSTICC} Press},
year = {2010},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icaart/DuLMLZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/JuLCMR09,
author = {Lei Ju and
Yun Liang and
Samarjit Chakraborty and
Tulika Mitra and
Abhik Roychoudhury},
title = {Cache-aware optimization of {BAN} applications},
journal = {Des. Autom. Embed. Syst.},
volume = {13},
number = {3},
pages = {159--178},
year = {2009},
url = {https://doi.org/10.1007/s10617-009-9045-3},
doi = {10.1007/S10617-009-9045-3},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dafes/JuLCMR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtss/LiSLMR09,
author = {Yan Li and
Vivy Suhendra and
Yun Liang and
Tulika Mitra and
Abhik Roychoudhury},
editor = {Theodore P. Baker},
title = {Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores},
booktitle = {Proceedings of the 30th {IEEE} Real-Time Systems Symposium, {RTSS}
2009, Washington, DC, USA, 1-4 December 2009},
pages = {57--67},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/RTSS.2009.32},
doi = {10.1109/RTSS.2009.32},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtss/LiSLMR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LiangM08,
author = {Yun Liang and
Tulika Mitra},
editor = {Catherine H. Gebotys and
Grant Martin},
title = {Static analysis for fast and accurate design space exploration of
caches},
booktitle = {Proceedings of the 6th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2008, Atlanta, GA, USA,
October 19-24, 2008},
pages = {103--108},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1450135.1450159},
doi = {10.1145/1450135.1450159},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/LiangM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LiangJCMR08,
author = {Yun Liang and
Lei Ju and
Samarjit Chakraborty and
Tulika Mitra and
Abhik Roychoudhury},
editor = {Catherine H. Gebotys and
Grant Martin},
title = {Cache-aware optimization of {BAN} applications},
booktitle = {Proceedings of the 6th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2008, Atlanta, GA, USA,
October 19-24, 2008},
pages = {149--154},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1450135.1450170},
doi = {10.1145/1450135.1450170},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/LiangJCMR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiangM08,
author = {Yun Liang and
Tulika Mitra},
editor = {Limor Fix},
title = {Cache modeling in probabilistic execution time analysis},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {319--324},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391551},
doi = {10.1145/1391469.1391551},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiangM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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