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BibTeX records: Gabriel H. Loh
@inproceedings{DBLP:conf/date/LohS23, author = {Gabriel H. Loh and Raja Swaminathan}, title = {The Next Era for Chiplet Innovation}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2023, Antwerp, Belgium, April 17-19, 2023}, pages = {1--6}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.23919/DATE56975.2023.10137172}, doi = {10.23919/DATE56975.2023.10137172}, timestamp = {Wed, 07 Jun 2023 22:08:03 +0200}, biburl = {https://dblp.org/rec/conf/date/LohS23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/LohSIAAAAAABBBB23, author = {Gabriel H. Loh and Michael J. Schulte and Mike Ignatowski and Vignesh Adhinarayanan and Shaizeen Aga and Derrick Aguren and Varun Agrawal and Ashwin M. Aji and Johnathan Alsop and Paul T. Bauman and Bradford M. Beckmann and Majed Valad Beigi and Sergey Blagodurov and Travis Boraten and Michael Boyer and William C. Brantley and Noel Chalmers and Shaoming Chen and Kevin Cheng and Michael L. Chu and David Cownie and Nicholas Curtis and Joris Del Pino and Nam Duong and Alexandru Dutu and Yasuko Eckert and Christopher Erb and Chip Freitag and Joseph L. Greathouse and Sudhanva Gurumurthi and Anthony Gutierrez and Khaled Hamidouche and Sachin Hossamani and Wei Huang and Mahzabeen Islam and Nuwan Jayasena and John Kalamatianos and Onur Kayiran and Jagadish Kotra and Alan Lee and Daniel Lowell and Niti Madan and Abhinandan Majumdar and Nicholas Malaya and Srilatha Manne and Susumu Mashimo and Damon McDougall and Elliot Mednick and Michael Mishkin and Mark Nutter and Indrani Paul and Matthew Poremba and Brandon Potter and Kishore Punniyamurthy and Sooraj Puthoor and Steven E. Raasch and Karthik Rao and Gregory Rodgers and Marko Scrbak and Mohammad Seyedzadeh and John Slice and Vilas Sridharan and Ren{\'{e}} van Oostrum and Eric Van Tassell and Abhinav Vishnu and Samuel Wasmundt and Mark Wilkening and Noah Wolfe and Mark Wyse and Adithya Yalavarti and Dmitri Yudanov}, editor = {Yan Solihin and Mark A. Heinrich}, title = {A Research Retrospective on AMD's Exascale Computing Journey}, booktitle = {Proceedings of the 50th Annual International Symposium on Computer Architecture, {ISCA} 2023, Orlando, FL, USA, June 17-21, 2023}, pages = {81:1--81:14}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3579371.3589349}, doi = {10.1145/3579371.3589349}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/LohSIAAAAAABBBB23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsit/SwaminathanSWLS23, author = {Raja Swaminathan and Michael J. Schulte and Brett Wilkerson and Gabriel H. Loh and Alan Smith and Norman James}, title = {{AMD} Instinct\({}^{\mbox{TM}}\) {MI250X} Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture}, booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology and Circuits), Kyoto, Japan, June 11-16, 2023}, pages = {1--2}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185224}, doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185224}, timestamp = {Fri, 28 Jul 2023 10:40:41 +0200}, biburl = {https://dblp.org/rec/conf/vlsit/SwaminathanSWLS23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LohNL21, author = {Gabriel H. Loh and Samuel Naffziger and Kevin Lepak}, title = {Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2021, Grenoble, France, February 1-5, 2021}, pages = {142--145}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.23919/DATE51398.2021.9474021}, doi = {10.23919/DATE51398.2021.9474021}, timestamp = {Wed, 21 Jul 2021 10:04:34 +0200}, biburl = {https://dblp.org/rec/conf/date/LohNL21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/IbrahimKELJ21, author = {Mohamed Assem Ibrahim and Onur Kayiran and Yasuko Eckert and Gabriel H. Loh and Adwait Jog}, title = {Analyzing and Leveraging Decoupled {L1} Caches in GPUs}, booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture, {HPCA} 2021, Seoul, South Korea, February 27 - March 3, 2021}, pages = {467--478}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/HPCA51647.2021.00047}, doi = {10.1109/HPCA51647.2021.00047}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/hpca/IbrahimKELJ21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/NaffzigerBBLLSW21, author = {Samuel Naffziger and Noah Beck and Thomas Burd and Kevin Lepak and Gabriel H. Loh and Mahesh Subramony and Sean White}, title = {Pioneering Chiplet Technology and Design for the {AMD} EPYC{\texttrademark} and Ryzen{\texttrademark} Processor Families : Industrial Product}, booktitle = {48th {ACM/IEEE} Annual International Symposium on Computer Architecture, {ISCA} 2021, Virtual Event / Valencia, Spain, June 14-18, 2021}, pages = {57--70}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/ISCA52012.2021.00014}, doi = {10.1109/ISCA52012.2021.00014}, timestamp = {Mon, 19 Feb 2024 07:32:07 +0100}, biburl = {https://dblp.org/rec/conf/isca/NaffzigerBBLLSW21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/KotraLKL21, author = {Jagadish B. Kotra and Michael LeBeane and Mahmut T. Kandemir and Gabriel H. Loh}, title = {Increasing {GPU} Translation Reach by Leveraging Under-Utilized On-Chip Resources}, booktitle = {{MICRO} '21: 54th Annual {IEEE/ACM} International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021}, pages = {1169--1181}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3466752.3480105}, doi = {10.1145/3466752.3480105}, timestamp = {Tue, 19 Oct 2021 15:51:04 +0200}, biburl = {https://dblp.org/rec/conf/micro/KotraLKL21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsic/PapermasterKLN21, author = {Mark Papermaster and Stephen Kosonocky and Gabriel H. Loh and Samuel Naffziger}, title = {A New Era of Tailored Computing}, booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021}, pages = {1--2}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492400}, doi = {10.23919/VLSICIRCUITS52068.2021.9492400}, timestamp = {Mon, 02 Aug 2021 16:52:31 +0200}, biburl = {https://dblp.org/rec/conf/vlsic/PapermasterKLN21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2109-01714, author = {Salonik Resch and Anthony Gutierrez and Joon Suk Huh and Srikant Bharadwaj and Yasuko Eckert and Gabriel H. Loh and Mark Oskin and Swamit S. Tannu}, title = {Accelerating Variational Quantum Algorithms Using Circuit Concurrency}, journal = {CoRR}, volume = {abs/2109.01714}, year = {2021}, url = {https://arxiv.org/abs/2109.01714}, eprinttype = {arXiv}, eprint = {2109.01714}, timestamp = {Mon, 20 Sep 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2109-01714.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/IbrahimKELJ20, author = {Mohamed Assem Ibrahim and Onur Kayiran and Yasuko Eckert and Gabriel H. Loh and Adwait Jog}, editor = {Vivek Sarkar and Hyesoon Kim}, title = {Analyzing and Leveraging Shared {L1} Caches in GPUs}, booktitle = {{PACT} '20: International Conference on Parallel Architectures and Compilation Techniques, Virtual Event, GA, USA, October 3-7, 2020}, pages = {161--173}, publisher = {{ACM}}, year = {2020}, url = {https://doi.org/10.1145/3410463.3414623}, doi = {10.1145/3410463.3414623}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/IEEEpact/IbrahimKELJ20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/YinSEPSMOJL20, author = {Jieming Yin and Subhash Sethumurugan and Yasuko Eckert and Chintan Patel and Alan Smith and Eric Morton and Mark Oskin and Natalie D. Enright Jerger and Gabriel H. Loh}, title = {Experiences with ML-Driven Design: {A} NoC Case Study}, booktitle = {{IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2020, San Diego, CA, USA, February 22-26, 2020}, pages = {637--648}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/HPCA47549.2020.00058}, doi = {10.1109/HPCA47549.2020.00058}, timestamp = {Wed, 29 Apr 2020 10:45:35 +0200}, biburl = {https://dblp.org/rec/conf/hpca/YinSEPSMOJL20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/StowAH0LL19, author = {Dylan C. Stow and Itir Akgun and Wenqin Huangfu and Yuan Xie and Xueqi Li and Gabriel H. Loh}, title = {Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory}, booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019, {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019}, pages = {100}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3316781.3323475}, doi = {10.1145/3316781.3323475}, timestamp = {Fri, 15 Dec 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/StowAH0LL19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/taco/KimHNKJEKL18, author = {Hyojong Kim and Ramyad Hadidi and Lifeng Nai and Hyesoon Kim and Nuwan Jayasena and Yasuko Eckert and Onur Kayiran and Gabriel H. Loh}, title = {{CODA:} Enabling Co-location of Computation and Data for Multiple {GPU} Systems}, journal = {{ACM} Trans. Archit. Code Optim.}, volume = {15}, number = {3}, pages = {32:1--32:23}, year = {2018}, url = {https://doi.org/10.1145/3232521}, doi = {10.1145/3232521}, timestamp = {Mon, 28 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/taco/KimHNKJEKL18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/GreathouseL18, author = {Joseph L. Greathouse and Gabriel H. Loh}, editor = {Iris Bahar}, title = {Machine learning for performance and power modeling of heterogeneous systems}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018}, pages = {47}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3240765.3243484}, doi = {10.1145/3240765.3243484}, timestamp = {Mon, 09 Aug 2021 14:54:01 +0200}, biburl = {https://dblp.org/rec/conf/iccad/GreathouseL18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/ShinCOLSBB18, author = {Seunghee Shin and Guilherme Cox and Mark Oskin and Gabriel H. Loh and Yan Solihin and Abhishek Bhattacharjee and Arkaprava Basu}, editor = {Murali Annavaram and Timothy Mark Pinkston and Babak Falsafi}, title = {Scheduling Page Table Walks for Irregular {GPU} Applications}, booktitle = {45th {ACM/IEEE} Annual International Symposium on Computer Architecture, {ISCA} 2018, Los Angeles, CA, USA, June 1-6, 2018}, pages = {180--192}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/ISCA.2018.00025}, doi = {10.1109/ISCA.2018.00025}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/ShinCOLSBB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/YinLKPAJL18, author = {Jieming Yin and Zhifeng Lin and Onur Kayiran and Matthew Poremba and Muhammad Shoaib Bin Altaf and Natalie D. Enright Jerger and Gabriel H. Loh}, editor = {Murali Annavaram and Timothy Mark Pinkston and Babak Falsafi}, title = {Modular Routing Design for Chiplet-Based Systems}, booktitle = {45th {ACM/IEEE} Annual International Symposium on Computer Architecture, {ISCA} 2018, Los Angeles, CA, USA, June 1-6, 2018}, pages = {726--738}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/ISCA.2018.00066}, doi = {10.1109/ISCA.2018.00066}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/YinLKPAJL18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/VeselyBBLOR18, author = {J{\'{a}}n Vesel{\'{y}} and Arkaprava Basu and Abhishek Bhattacharjee and Gabriel H. Loh and Mark Oskin and Steven K. Reinhardt}, editor = {Murali Annavaram and Timothy Mark Pinkston and Babak Falsafi}, title = {Generic System Calls for GPUs}, booktitle = {45th {ACM/IEEE} Annual International Symposium on Computer Architecture, {ISCA} 2018, Los Angeles, CA, USA, June 1-6, 2018}, pages = {843--856}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/ISCA.2018.00075}, doi = {10.1109/ISCA.2018.00075}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/VeselyBBLOR18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sc/FarahaniGLI18, author = {Amin Farmahini Farahani and Sudhanva Gurumurthi and Gabriel H. Loh and Michael Ignatowski}, title = {Challenges of High-Capacity {DRAM} Stacks and Potential Directions}, booktitle = {Proceedings of the Workshop on Memory Centric High Performance Computing, MCHPC@SC 2018, Dallas, TX, USA, November 11, 2018}, pages = {4--13}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3286475.3286484}, doi = {10.1145/3286475.3286484}, timestamp = {Sat, 22 Dec 2018 17:30:19 +0100}, biburl = {https://dblp.org/rec/conf/sc/FarahaniGLI18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-1804-11038, author = {Rachata Ausavarungnirun and Saugata Ghose and Onur Kayiran and Gabriel H. Loh and Chita R. Das and Mahmut T. Kandemir and Onur Mutlu}, title = {Holistic Management of the {GPGPU} Memory Hierarchy to Manage Warp-level Latency Tolerance}, journal = {CoRR}, volume = {abs/1804.11038}, year = {2018}, url = {http://arxiv.org/abs/1804.11038}, eprinttype = {arXiv}, eprint = {1804.11038}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-1804-11038.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-1804-11043, author = {Rachata Ausavarungnirun and Gabriel H. Loh and Lavanya Subramanian and Kevin K. Chang and Onur Mutlu}, title = {High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems}, journal = {CoRR}, volume = {abs/1804.11043}, year = {2018}, url = {http://arxiv.org/abs/1804.11043}, eprinttype = {arXiv}, eprint = {1804.11043}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-1804-11043.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/AwadBBSL17, author = {Amro Awad and Arkaprava Basu and Sergey Blagodurov and Yan Solihin and Gabriel H. Loh}, title = {Avoiding {TLB} Shootdowns Through Self-Invalidating {TLB} Entries}, booktitle = {26th International Conference on Parallel Architectures and Compilation Techniques, {PACT} 2017, Portland, OR, USA, September 9-13, 2017}, pages = {273--287}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/PACT.2017.38}, doi = {10.1109/PACT.2017.38}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/IEEEpact/AwadBBSL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/VijayaraghavanE17, author = {Thiruvengadam Vijayaraghavan and Yasuko Eckert and Gabriel H. Loh and Michael J. Schulte and Mike Ignatowski and Bradford M. Beckmann and William C. Brantley and Joseph L. Greathouse and Wei Huang and Arun Karunanithi and Onur Kayiran and Mitesh R. Meswani and Indrani Paul and Matthew Poremba and Steven Raasch and Steven K. Reinhardt and Greg Sadowski and Vilas Sridharan}, title = {Design and Analysis of an {APU} for Exascale Computing}, booktitle = {2017 {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2017, Austin, TX, USA, February 4-8, 2017}, pages = {85--96}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/HPCA.2017.42}, doi = {10.1109/HPCA.2017.42}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/VijayaraghavanE17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/ProdromouMJLT17, author = {Andreas Prodromou and Mitesh R. Meswani and Nuwan Jayasena and Gabriel H. Loh and Dean M. Tullsen}, title = {MemPod: {A} Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories}, booktitle = {2017 {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2017, Austin, TX, USA, February 4-8, 2017}, pages = {433--444}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/HPCA.2017.39}, doi = {10.1109/HPCA.2017.39}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/hpca/ProdromouMJLT17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/Stow0SL17, author = {Dylan C. Stow and Yuan Xie and Taniya Siddiqua and Gabriel H. Loh}, editor = {Sri Parameswaran}, title = {Cost-effective design of scalable high-performance systems using active and passive interposers}, booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017}, pages = {728--735}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/ICCAD.2017.8203849}, doi = {10.1109/ICCAD.2017.8203849}, timestamp = {Fri, 15 Nov 2019 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/Stow0SL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/PorembaAYKXL17, author = {Matthew Poremba and Itir Akgun and Jieming Yin and Onur Kayiran and Yuan Xie and Gabriel H. Loh}, title = {There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes}, booktitle = {Proceedings of the 44th Annual International Symposium on Computer Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017}, pages = {678--690}, publisher = {{ACM}}, year = {2017}, url = {https://dl.acm.org/citation.cfm?id=3080251}, timestamp = {Mon, 26 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/PorembaAYKXL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sc/AgrawalLT17, author = {Abhinav Agrawal and Gabriel H. Loh and James Tuck}, editor = {Bernd Mohr and Padma Raghavan}, title = {Leveraging near data processing for high-performance checkpoint/restart}, booktitle = {Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, {SC} 2017, Denver, CO, USA, November 12 - 17, 2017}, pages = {60}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3126908.3126918}, doi = {10.1145/3126908.3126918}, timestamp = {Tue, 23 Jan 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sc/AgrawalLT17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/VeselyBBLOR17, author = {J{\'{a}}n Vesel{\'{y}} and Arkaprava Basu and Abhishek Bhattacharjee and Gabriel H. Loh and Mark Oskin and Steven K. Reinhardt}, title = {{GPU} System Calls}, journal = {CoRR}, volume = {abs/1705.06965}, year = {2017}, url = {http://arxiv.org/abs/1705.06965}, eprinttype = {arXiv}, eprint = {1705.06965}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/VeselyBBLOR17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-1710-09517, author = {Hyojong Kim and Ramyad Hadidi and Lifeng Nai and Hyesoon Kim and Nuwan Jayasena and Yasuko Eckert and Onur Kayiran and Gabriel H. Loh}, title = {{CODA:} Enabling Co-location of Computation and Data for Near-Data Processing}, journal = {CoRR}, volume = {abs/1710.09517}, year = {2017}, url = {http://arxiv.org/abs/1710.09517}, eprinttype = {arXiv}, eprint = {1710.09517}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-1710-09517.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/KannanJL16, author = {Ajaykumar Kannan and Natalie D. Enright Jerger and Gabriel H. Loh}, title = {Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors}, journal = {{IEEE} Micro}, volume = {36}, number = {3}, pages = {84--93}, year = {2016}, url = {https://doi.org/10.1109/MM.2016.53}, doi = {10.1109/MM.2016.53}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/KannanJL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/pc/Ausavarungnirun16, author = {Rachata Ausavarungnirun and Chris Fallin and Xiangyao Yu and Kevin Kai{-}Wei Chang and Greg Nazario and Reetuparna Das and Gabriel H. Loh and Onur Mutlu}, title = {A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate}, journal = {Parallel Comput.}, volume = {54}, pages = {29--45}, year = {2016}, url = {https://doi.org/10.1016/j.parco.2016.01.009}, doi = {10.1016/J.PARCO.2016.01.009}, timestamp = {Sat, 22 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/pc/Ausavarungnirun16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/KayiranJPATKLMD16, author = {Onur Kayiran and Adwait Jog and Ashutosh Pattnaik and Rachata Ausavarungnirun and Xulong Tang and Mahmut T. Kandemir and Gabriel H. Loh and Onur Mutlu and Chita R. Das}, editor = {Ayal Zaks and Bilha Mendelson and Lawrence Rauchwerger and Wen{-}mei W. Hwu}, title = {{\(\mu\)}C-States: Fine-grained {GPU} Datapath Power Management}, booktitle = {Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, {PACT} 2016, Haifa, Israel, September 11-15, 2016}, pages = {17--30}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2967938.2967941}, doi = {10.1145/2967938.2967941}, timestamp = {Wed, 11 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/IEEEpact/KayiranJPATKLMD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/YinKPJL16, author = {Jieming Yin and Onur Kayiran and Matthew Poremba and Natalie D. Enright Jerger and Gabriel H. Loh}, title = {Efficient synthetic traffic models for large, complex SoCs}, booktitle = {2016 {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2016, Barcelona, Spain, March 12-16, 2016}, pages = {297--308}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/HPCA.2016.7446073}, doi = {10.1109/HPCA.2016.7446073}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/YinKPJL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispass/VeselyBOLB16, author = {J{\'{a}}n Vesel{\'{y}} and Arkaprava Basu and Mark Oskin and Gabriel H. Loh and Abhishek Bhattacharjee}, title = {Observations and opportunities in architecting shared virtual memory for heterogeneous systems}, booktitle = {2016 {IEEE} International Symposium on Performance Analysis of Systems and Software, {ISPASS} 2016, Uppsala, Sweden, April 17-19, 2016}, pages = {161--171}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/ISPASS.2016.7482091}, doi = {10.1109/ISPASS.2016.7482091}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispass/VeselyBOLB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/ZhanKLDX16, author = {Jia Zhan and Onur Kayiran and Gabriel H. Loh and Chita R. Das and Yuan Xie}, title = {{OSCAR:} Orchestrating {STT-RAM} cache traffic for heterogeneous {CPU-GPU} architectures}, booktitle = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2016, Taipei, Taiwan, October 15-19, 2016}, pages = {28:1--28:13}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/MICRO.2016.7783731}, doi = {10.1109/MICRO.2016.7783731}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/ZhanKLDX16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sbac-pad/WangJZLX16, author = {Zhe Wang and Daniel A. Jim{\'{e}}nez and Tao Zhang and Gabriel H. Loh and Yuan Xie}, title = {Building a Low Latency, Highly Associative {DRAM} Cache with the Buffered Way Predictor}, booktitle = {28th International Symposium on Computer Architecture and High Performance Computing, {SBAC-PAD} 2016, Los Angeles, CA, USA, October 26-28, 2016}, pages = {109--117}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/SBAC-PAD.2016.22}, doi = {10.1109/SBAC-PAD.2016.22}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sbac-pad/WangJZLX16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/ChangLTEOMHSM16, author = {Kevin Kai{-}Wei Chang and Gabriel H. Loh and Mithuna Thottethodi and Yasuko Eckert and Mike O'Connor and Srilatha Manne and Lisa Hsu and Lavanya Subramanian and Onur Mutlu}, title = {Enabling Efficient Dynamic Resizing of Large {DRAM} Caches via {A} Hardware Consistent Hashing Mechanism}, journal = {CoRR}, volume = {abs/1602.00722}, year = {2016}, url = {http://arxiv.org/abs/1602.00722}, eprinttype = {arXiv}, eprint = {1602.00722}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/ChangLTEOMHSM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/Ausavarungnirun16, author = {Rachata Ausavarungnirun and Chris Fallin and Xiangyao Yu and Kevin Kai{-}Wei Chang and Greg Nazario and Reetuparna Das and Gabriel H. Loh and Onur Mutlu}, title = {Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing}, journal = {CoRR}, volume = {abs/1602.06005}, year = {2016}, url = {http://arxiv.org/abs/1602.06005}, eprinttype = {arXiv}, eprint = {1602.06005}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/Ausavarungnirun16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/SchulteILBBGJPR15, author = {Michael J. Schulte and Mike Ignatowski and Gabriel H. Loh and Bradford M. Beckmann and William C. Brantley and Sudhanva Gurumurthi and Nuwan Jayasena and Indrani Paul and Steven K. Reinhardt and Gregory Rodgers}, title = {Achieving Exascale Capabilities through Heterogeneous Computing}, journal = {{IEEE} Micro}, volume = {35}, number = {4}, pages = {26--36}, year = {2015}, url = {https://doi.org/10.1109/MM.2015.71}, doi = {10.1109/MM.2015.71}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/SchulteILBBGJPR15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/KimAHHJKKLLLLPPRSSWZKCLLL15, author = {Daehyun Kim and Krit Athikulwongse and Michael B. Healy and Mohammad M. Hossain and Moongon Jung and Ilya Khorosh and Gokul Kumar and Young{-}Joon Lee and Dean L. Lewis and Tzu{-}Wei Lin and Chang Liu and Shreepad Panth and Mohit Pathak and Minzhen Ren and Guanhao Shen and Taigon Song and Dong Hyuk Woo and Xin Zhao and Joungho Kim and Ho Choi and Gabriel H. Loh and Hsien{-}Hsin S. Lee and Sung Kyu Lim}, title = {Design and Analysis of 3D-MAPS {(3D} Massively Parallel Processor with Stacked Memory)}, journal = {{IEEE} Trans. Computers}, volume = {64}, number = {1}, pages = {112--125}, year = {2015}, url = {https://doi.org/10.1109/TC.2013.192}, doi = {10.1109/TC.2013.192}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/KimAHHJKKLLLLPPRSSWZKCLLL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/Ausavarungnirun15, author = {Rachata Ausavarungnirun and Saugata Ghose and Onur Kayiran and Gabriel H. Loh and Chita R. Das and Mahmut T. Kandemir and Onur Mutlu}, title = {Exploiting Inter-Warp Heterogeneity to Improve {GPGPU} Performance}, booktitle = {2015 International Conference on Parallel Architectures and Compilation, {PACT} 2015, San Francisco, CA, USA, October 18-21, 2015}, pages = {25--38}, publisher = {{IEEE} Computer Society}, year = {2015}, url = {https://doi.org/10.1109/PACT.2015.38}, doi = {10.1109/PACT.2015.38}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/IEEEpact/Ausavarungnirun15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/OskinL15, author = {Mark Oskin and Gabriel H. Loh}, title = {A Software-Managed Approach to Die-Stacked {DRAM}}, booktitle = {2015 International Conference on Parallel Architectures and Compilation, {PACT} 2015, San Francisco, CA, USA, October 18-21, 2015}, pages = {188--200}, publisher = {{IEEE} Computer Society}, year = {2015}, url = {https://doi.org/10.1109/PACT.2015.30}, doi = {10.1109/PACT.2015.30}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/IEEEpact/OskinL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/MeswaniBRSIL15, author = {Mitesh R. Meswani and Sergey Blagodurov and David Roberts and John Slice and Mike Ignatowski and Gabriel H. Loh}, title = {Heterogeneous memory architectures: {A} {HW/SW} approach for mixing die-stacked and off-package memories}, booktitle = {21st {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2015, Burlingame, CA, USA, February 7-11, 2015}, pages = {126--136}, publisher = {{IEEE} Computer Society}, year = {2015}, url = {https://doi.org/10.1109/HPCA.2015.7056027}, doi = {10.1109/HPCA.2015.7056027}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/MeswaniBRSIL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/memsys/LohJKE15, author = {Gabriel H. Loh and Natalie D. Enright Jerger and Ajaykumar Kannan and Yasuko Eckert}, editor = {Bruce L. Jacob}, title = {Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems}, booktitle = {Proceedings of the 2015 International Symposium on Memory Systems, {MEMSYS} 2015, Washington DC, DC, USA, October 5-8, 2015}, pages = {3--10}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2818950.2818951}, doi = {10.1145/2818950.2818951}, timestamp = {Fri, 13 Nov 2020 09:24:44 +0100}, biburl = {https://dblp.org/rec/conf/memsys/LohJKE15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/memsys/SuRLCSLN15, author = {Chun{-}Yi Su and David Roberts and Edgar A. Le{\'{o}}n and Kirk W. Cameron and Bronis R. de Supinski and Gabriel H. Loh and Dimitrios S. Nikolopoulos}, editor = {Bruce L. Jacob}, title = {HpMC: An Energy-aware Management System of Multi-level Memory Architectures}, booktitle = {Proceedings of the 2015 International Symposium on Memory Systems, {MEMSYS} 2015, Washington DC, DC, USA, October 5-8, 2015}, pages = {167--178}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2818950.2818974}, doi = {10.1145/2818950.2818974}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/memsys/SuRLCSLN15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/PhamVLB15, author = {Binh Pham and J{\'{a}}n Vesel{\'{y}} and Gabriel H. Loh and Abhishek Bhattacharjee}, editor = {Milos Prvulovic}, title = {Large pages and lightweight memory management in virtualized environments: can you have it both ways?}, booktitle = {Proceedings of the 48th International Symposium on Microarchitecture, {MICRO} 2015, Waikiki, HI, USA, December 5-9, 2015}, pages = {1--12}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2830772.2830773}, doi = {10.1145/2830772.2830773}, timestamp = {Wed, 11 Aug 2021 11:51:26 +0200}, biburl = {https://dblp.org/rec/conf/micro/PhamVLB15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/KannanJL15, author = {Ajaykumar Kannan and Natalie D. Enright Jerger and Gabriel H. Loh}, editor = {Milos Prvulovic}, title = {Enabling interposer-based disintegration of multi-core processors}, booktitle = {Proceedings of the 48th International Symposium on Microarchitecture, {MICRO} 2015, Waikiki, HI, USA, December 5-9, 2015}, pages = {546--558}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2830772.2830808}, doi = {10.1145/2830772.2830808}, timestamp = {Wed, 11 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/KannanJL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/SimLSO14, author = {Jaewoong Sim and Gabriel H. Loh and Vilas Sridharan and Mike O'Connor}, title = {A Configurable and Strong {RAS} Solution for Die-Stacked {DRAM} Caches}, journal = {{IEEE} Micro}, volume = {34}, number = {3}, pages = {80--90}, year = {2014}, url = {https://doi.org/10.1109/MM.2014.13}, doi = {10.1109/MM.2014.13}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/SimLSO14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/PhamBEL14, author = {Binh Pham and Abhishek Bhattacharjee and Yasuko Eckert and Gabriel H. Loh}, title = {Increasing {TLB} reach by exploiting clustering in page translations}, booktitle = {20th {IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2014, Orlando, FL, USA, February 15-19, 2014}, pages = {558--567}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/HPCA.2014.6835964}, doi = {10.1109/HPCA.2014.6835964}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/PhamBEL14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ics/TianKJL14, author = {Yingying Tian and Samira Manabi Khan and Daniel A. Jim{\'{e}}nez and Gabriel H. Loh}, editor = {Arndt Bode and Michael Gerndt and Per Stenstr{\"{o}}m and Lawrence Rauchwerger and Barton P. Miller and Martin Schulz}, title = {Last-level cache deduplication}, booktitle = {2014 International Conference on Supercomputing, ICS'14, Muenchen, Germany, June 10-13, 2014}, pages = {53--62}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2597652.2597655}, doi = {10.1145/2597652.2597655}, timestamp = {Sun, 25 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ics/TianKJL14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/JeonLA14, author = {Hyeran Jeon and Gabriel H. Loh and Murali Annavaram}, title = {Efficient {RAS} support for die-stacked {DRAM}}, booktitle = {2014 International Test Conference, {ITC} 2014, Seattle, WA, USA, October 20-23, 2014}, pages = {1--10}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/TEST.2014.7035318}, doi = {10.1109/TEST.2014.7035318}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/JeonLA14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/JevdjicLKF14, author = {Djordje Jevdjic and Gabriel H. Loh and Cansu Kaynak and Babak Falsafi}, title = {Unison Cache: {A} Scalable and Effective Die-Stacked {DRAM} Cache}, booktitle = {47th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2014, Cambridge, United Kingdom, December 13-17, 2014}, pages = {25--37}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/MICRO.2014.51}, doi = {10.1109/MICRO.2014.51}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/JevdjicLKF14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/KayiranNJAKLMD14, author = {Onur Kayiran and Nachiappan Chidambaram Nachiappan and Adwait Jog and Rachata Ausavarungnirun and Mahmut T. Kandemir and Gabriel H. Loh and Onur Mutlu and Chita R. Das}, title = {Managing {GPU} Concurrency in Heterogeneous Architectures}, booktitle = {47th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2014, Cambridge, United Kingdom, December 13-17, 2014}, pages = {114--126}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/MICRO.2014.62}, doi = {10.1109/MICRO.2014.62}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/KayiranNJAKLMD14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/JergerKLL14, author = {Natalie D. Enright Jerger and Ajaykumar Kannan and Zimo Li and Gabriel H. Loh}, title = {NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?}, booktitle = {47th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2014, Cambridge, United Kingdom, December 13-17, 2014}, pages = {458--470}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/MICRO.2014.61}, doi = {10.1109/MICRO.2014.61}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/JergerKLL14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sbac-pad/AusavarungnirunFYCNDLM14, author = {Rachata Ausavarungnirun and Chris Fallin and Xiangyao Yu and Kevin Kai{-}Wei Chang and Greg Nazario and Reetuparna Das and Gabriel H. Loh and Onur Mutlu}, title = {Design and Evaluation of Hierarchical Rings with Deflection Routing}, booktitle = {26th {IEEE} International Symposium on Computer Architecture and High Performance Computing, {SBAC-PAD} 2014, Paris, France, October 22-24, 2014}, pages = {230--237}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/SBAC-PAD.2014.31}, doi = {10.1109/SBAC-PAD.2014.31}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sbac-pad/AusavarungnirunFYCNDLM14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sc/MeswaniLBRSI14, author = {Mitesh R. Meswani and Gabriel H. Loh and Sergey Blagodurov and David Roberts and John Slice and Mike Ignatowski}, title = {Toward efficient programmer-managed two-level memory hierarchies in exascale computers}, booktitle = {Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, Co-HPC '14, New Orleans, Louisiana, USA, November 16-21, 2014}, pages = {9--16}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/Co-HPC.2014.8}, doi = {10.1109/CO-HPC.2014.8}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sc/MeswaniLBRSI14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sc/ChatterjeeOLJB14, author = {Niladrish Chatterjee and Mike O'Connor and Gabriel H. Loh and Nuwan Jayasena and Rajeev Balasubramonian}, editor = {Trish Damkroger and Jack J. Dongarra}, title = {Managing {DRAM} Latency Divergence in Irregular {GPGPU} Applications}, booktitle = {International Conference for High Performance Computing, Networking, Storage and Analysis, {SC} 2014, New Orleans, LA, USA, November 16-21, 2014}, pages = {128--139}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/SC.2014.16}, doi = {10.1109/SC.2014.16}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sc/ChatterjeeOLJB14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/FalsafiL13, author = {Babak Falsafi and Gabriel H. Loh}, title = {Top Picks from the 2012 Computer Architecture Conferences}, journal = {{IEEE} Micro}, volume = {33}, number = {3}, pages = {4--7}, year = {2013}, url = {https://doi.org/10.1109/MM.2013.65}, doi = {10.1109/MM.2013.65}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/FalsafiL13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/taco/ZhaoSLX13, author = {Jishen Zhao and Guangyu Sun and Gabriel H. Loh and Yuan Xie}, title = {Optimizing {GPU} energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface}, journal = {{ACM} Trans. Archit. Code Optim.}, volume = {10}, number = {4}, pages = {24:1--24:25}, year = {2013}, url = {https://doi.org/10.1145/2541228.2541231}, doi = {10.1145/2541228.2541231}, timestamp = {Wed, 17 Feb 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/taco/ZhaoSLX13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/XieL13, author = {Yuan Xie and Gabriel H. Loh}, title = {Guest Editorial}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {32}, number = {4}, pages = {485--486}, year = {2013}, url = {https://doi.org/10.1109/TCAD.2013.2250716}, doi = {10.1109/TCAD.2013.2250716}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/XieL13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/SimLSO13, author = {Jaewoong Sim and Gabriel H. Loh and Vilas Sridharan and Mike O'Connor}, editor = {Avi Mendelson}, title = {Resilient die-stacked {DRAM} caches}, booktitle = {The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013}, pages = {416--427}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2485922.2485958}, doi = {10.1145/2485922.2485958}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isca/SimLSO13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/esticas/ChoiKL12, author = {Kiyoung Choi and John Kim and Gabriel H. Loh}, title = {Guest Editorial New Interconnect Technologies in On-Chip Communication}, journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.}, volume = {2}, number = {2}, pages = {121--123}, year = {2012}, url = {https://doi.org/10.1109/JETCAS.2012.2196890}, doi = {10.1109/JETCAS.2012.2196890}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/esticas/ChoiKL12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/esticas/KimCL12, author = {John Kim and Kiyoung Choi and Gabriel H. Loh}, title = {Exploiting New Interconnect Technologies in On-Chip Communication}, journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.}, volume = {2}, number = {2}, pages = {124--136}, year = {2012}, url = {https://doi.org/10.1109/JETCAS.2012.2201031}, doi = {10.1109/JETCAS.2012.2201031}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/esticas/KimCL12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/LohH12, author = {Gabriel H. Loh and Mark D. Hill}, title = {Supporting Very Large {DRAM} Caches with Compound-Access Scheduling and MissMap}, journal = {{IEEE} Micro}, volume = {32}, number = {3}, pages = {70--78}, year = {2012}, url = {https://doi.org/10.1109/MM.2012.25}, doi = {10.1109/MM.2012.25}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/LohH12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/AusavarungnirunCSLM12, author = {Rachata Ausavarungnirun and Kevin Kai{-}Wei Chang and Lavanya Subramanian and Gabriel H. Loh and Onur Mutlu}, title = {Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems}, booktitle = {39th International Symposium on Computer Architecture {(ISCA} 2012), June 9-13, 2012, Portland, OR, {USA}}, pages = {416--427}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/ISCA.2012.6237036}, doi = {10.1109/ISCA.2012.6237036}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/AusavarungnirunCSLM12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/islped/ZhaoSLX12, author = {Jishen Zhao and Guangyu Sun and Gabriel H. Loh and Yuan Xie}, editor = {Naresh R. Shanbhag and Massimo Poncino and Pai H. Chou and Ajith Amerasekera}, title = {Energy-efficient {GPU} design with reconfigurable in-package graphics memory}, booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, {USA} - July 30 - August 01, 2012}, pages = {403--408}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2333660.2333752}, doi = {10.1145/2333660.2333752}, timestamp = {Sun, 19 May 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/islped/ZhaoSLX12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/KimAHHJKKLLLLPPRSSWZKCLLL12, author = {Dae Hyun Kim and Krit Athikulwongse and Michael B. Healy and Mohammad M. Hossain and Moongon Jung and Ilya Khorosh and Gokul Kumar and Young{-}Joon Lee and Dean L. Lewis and Tzu{-}Wei Lin and Chang Liu and Shreepad Panth and Mohit Pathak and Minzhen Ren and Guanhao Shen and Taigon Song and Dong Hyuk Woo and Xin Zhao and Joungho Kim and Ho Choi and Gabriel H. Loh and Hsien{-}Hsin S. Lee and Sung Kyu Lim}, title = {3D-MAPS: 3D Massively parallel processor with stacked memory}, booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC} 2012, San Francisco, CA, USA, February 19-23, 2012}, pages = {188--190}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/ISSCC.2012.6176969}, doi = {10.1109/ISSCC.2012.6176969}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isscc/KimAHHJKKLLLLPPRSSWZKCLLL12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/QureshiL12, author = {Moinuddin K. Qureshi and Gabriel H. Loh}, title = {Fundamental Latency Trade-off in Architecting {DRAM} Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design}, booktitle = {45th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2012, Vancouver, BC, Canada, December 1-5, 2012}, pages = {235--246}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/MICRO.2012.30}, doi = {10.1109/MICRO.2012.30}, timestamp = {Tue, 31 May 2022 14:39:58 +0200}, biburl = {https://dblp.org/rec/conf/micro/QureshiL12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/SimLKOT12, author = {Jaewoong Sim and Gabriel H. Loh and Hyesoon Kim and Mike O'Connor and Mithuna Thottethodi}, title = {A Mostly-Clean {DRAM} Cache for Effective Hit Speculation and Self-Balancing Dispatch}, booktitle = {45th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2012, Vancouver, BC, Canada, December 1-5, 2012}, pages = {247--257}, publisher = {{IEEE} Computer Society}, year = {2012}, url = {https://doi.org/10.1109/MICRO.2012.31}, doi = {10.1109/MICRO.2012.31}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/SimLKOT12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsi-dat/Loh12, author = {Gabriel H. Loh}, title = {Computer architecture for die stacking}, booktitle = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012}, pages = {1--2}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/VLSI-DAT.2012.6212612}, doi = {10.1109/VLSI-DAT.2012.6212612}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/vlsi-dat/Loh12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/XieL11, author = {Yuejian Xie and Gabriel H. Loh}, title = {Thread-aware dynamic shared cache compression in multi-core processors}, booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011, Amherst, MA, USA, October 9-12, 2011}, pages = {135--141}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ICCD.2011.6081388}, doi = {10.1109/ICCD.2011.6081388}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/XieL11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/HaySSLB11, author = {Andrew W. Hay and Karin Strauss and Timothy Sherwood and Gabriel H. Loh and Doug Burger}, editor = {Carlo Galuzzi and Luigi Carro and Andreas Moshovos and Milos Prvulovic}, title = {Preventing {PCM} banks from seizing too much power}, booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011}, pages = {186--195}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2155620.2155642}, doi = {10.1145/2155620.2155642}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/HaySSLB11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/Loh11, author = {Gabriel H. Loh}, editor = {Carlo Galuzzi and Luigi Carro and Andreas Moshovos and Milos Prvulovic}, title = {A register-file approach for row buffer caches in die-stacked DRAMs}, booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011}, pages = {351--361}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2155620.2155662}, doi = {10.1145/2155620.2155662}, timestamp = {Wed, 11 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/Loh11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/LohH11, author = {Gabriel H. Loh and Mark D. Hill}, editor = {Carlo Galuzzi and Luigi Carro and Andreas Moshovos and Milos Prvulovic}, title = {Efficiently enabling conventional block sizes for very large die-stacked {DRAM} caches}, booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011}, pages = {454--464}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2155620.2155673}, doi = {10.1145/2155620.2155673}, timestamp = {Wed, 11 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/LohH11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/LohX10, author = {Gabriel H. Loh and Yuan Xie}, title = {3D Stacked Microprocessor: Are We There Yet?}, journal = {{IEEE} Micro}, volume = {30}, number = {3}, pages = {60--64}, year = {2010}, url = {https://doi.org/10.1109/MM.2010.45}, doi = {10.1109/MM.2010.45}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/LohX10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/HealyAGHKLLLLJOPSSWZLLL10, author = {Michael B. Healy and Krit Athikulwongse and Rohan Goel and Mohammad M. Hossain and Dae Hyun Kim and Young{-}Joon Lee and Dean L. Lewis and Tzu{-}Wei Lin and Chang Liu and Moongon Jung and Brian Ouellette and Mohit Pathak and Hemant Sane and Guanhao Shen and Dong Hyuk Woo and Xin Zhao and Gabriel H. Loh and Hsien{-}Hsin S. Lee and Sung Kyu Lim}, editor = {Jacqueline Snyder and Rakesh Patel and Tom Andre}, title = {Design and analysis of 3D-MAPS: {A} many-core 3D processor with stacked memory}, booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings}, pages = {1--4}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/CICC.2010.5617464}, doi = {10.1109/CICC.2010.5617464}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/cicc/HealyAGHKLLLLJOPSSWZLLL10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/OzdemirPDMLC10, author = {Serkan Ozdemir and Yan Pan and Abhishek Das and Gokhan Memik and Gabriel H. Loh and Alok N. Choudhary}, editor = {Sachin S. Sapatnekar}, title = {Quantifying and coping with parametric variations in 3D-stacked microarchitectures}, booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010, Anaheim, California, USA, July 13-18, 2010}, pages = {144--149}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1837274.1837312}, doi = {10.1145/1837274.1837312}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/OzdemirPDMLC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hipeac/XieL10, author = {Yuejian Xie and Gabriel H. Loh}, editor = {Yale N. Patt and Pierfrancesco Foglia and Evelyn Duesterwald and Paolo Faraboschi and Xavier Martorell}, title = {Scalable Shared-Cache Management by Containing Thrashing Workloads}, booktitle = {High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings}, series = {Lecture Notes in Computer Science}, volume = {5952}, pages = {262--276}, publisher = {Springer}, year = {2010}, url = {https://doi.org/10.1007/978-3-642-11515-8\_20}, doi = {10.1007/978-3-642-11515-8\_20}, timestamp = {Tue, 14 May 2019 10:00:51 +0200}, biburl = {https://dblp.org/rec/conf/hipeac/XieL10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/SchechterLSB10, author = {Stuart E. Schechter and Gabriel H. Loh and Karin Strauss and Doug Burger}, editor = {Andr{\'{e}} Seznec and Uri C. Weiser and Ronny Ronen}, title = {Use ECP, not ECC, for hard failures in resistive memories}, booktitle = {37th International Symposium on Computer Architecture {(ISCA} 2010), June 19-23, 2010, Saint-Malo, France}, pages = {141--152}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1815961.1815980}, doi = {10.1145/1815961.1815980}, timestamp = {Fri, 09 Jul 2021 15:51:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/SchechterLSB10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/taco/SubramaniamL09, author = {Samantika Subramaniam and Gabriel H. Loh}, title = {Design and optimization of the store vectors memory dependence predictor}, journal = {{ACM} Trans. Archit. Code Optim.}, volume = {6}, number = {4}, pages = {16:1--16:33}, year = {2009}, url = {https://doi.org/10.1145/1596510.1596514}, doi = {10.1145/1596510.1596514}, timestamp = {Wed, 17 Feb 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/taco/SubramaniamL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/PuttaswamyL09, author = {Kiran Puttaswamy and Gabriel H. Loh}, title = {3D-Integrated {SRAM} Components for High-Performance Microprocessors}, journal = {{IEEE} Trans. Computers}, volume = {58}, number = {10}, pages = {1369--1381}, year = {2009}, url = {https://doi.org/10.1109/TC.2009.92}, doi = {10.1109/TC.2009.92}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/PuttaswamyL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/HealyLLL09, author = {Michael B. Healy and Hsien{-}Hsin S. Lee and Gabriel H. Loh and Sung Kyu Lim}, editor = {Kazutoshi Wakabayashi}, title = {Thermal optimization in multi-granularity multi-core floorplanning}, booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference, {ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009}, pages = {43--48}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ASPDAC.2009.4796439}, doi = {10.1109/ASPDAC.2009.4796439}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/HealyLLL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/SubramaniamBWL09, author = {Samantika Subramaniam and Anne Bracy and Hong Wang and Gabriel H. Loh}, title = {Criticality-based optimizations for efficient load processing}, booktitle = {15th International Conference on High-Performance Computer Architecture {(HPCA-15} 2009), 14-18 February 2009, Raleigh, North Carolina, {USA}}, pages = {419--430}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/HPCA.2009.4798280}, doi = {10.1109/HPCA.2009.4798280}, timestamp = {Wed, 16 Oct 2019 14:14:50 +0200}, biburl = {https://dblp.org/rec/conf/hpca/SubramaniamBWL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/XieL09, author = {Yuejian Xie and Gabriel H. Loh}, editor = {Stephen W. Keckler and Luiz Andr{\'{e}} Barroso}, title = {{PIPP:} promotion/insertion pseudo-partitioning of multi-core shared caches}, booktitle = {36th International Symposium on Computer Architecture {(ISCA} 2009), June 20-24, 2009, Austin, TX, {USA}}, pages = {174--183}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1555754.1555778}, doi = {10.1145/1555754.1555778}, timestamp = {Fri, 09 Jul 2021 15:51:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/XieL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispass/LohSX09, author = {Gabriel H. Loh and Samantika Subramaniam and Yuejian Xie}, title = {Zesto: {A} cycle-level simulator for highly detailed microarchitecture exploration}, booktitle = {{IEEE} International Symposium on Performance Analysis of Systems and Software, {ISPASS} 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings}, pages = {53--64}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/ISPASS.2009.4919638}, doi = {10.1109/ISPASS.2009.4919638}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispass/LohSX09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/Loh09, author = {Gabriel H. Loh}, editor = {David H. Albonesi and Margaret Martonosi and David I. August and Jos{\'{e}} F. Mart{\'{\i}}nez}, title = {Extending the effectiveness of 3D-stacked {DRAM} caches with an adaptive multi-queue policy}, booktitle = {42st Annual {IEEE/ACM} International Symposium on Microarchitecture {(MICRO-42} 2009), December 12-16, 2009, New York, New York, {USA}}, pages = {201--212}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1669112.1669139}, doi = {10.1145/1669112.1669139}, timestamp = {Wed, 11 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/Loh09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ijpp/LohJ08, author = {Gabriel H. Loh and Daniel A. Jim{\'{e}}nez}, title = {Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors}, journal = {Int. J. Parallel Program.}, volume = {36}, number = {2}, pages = {267--286}, year = {2008}, url = {https://doi.org/10.1007/s10766-007-0063-0}, doi = {10.1007/S10766-007-0063-0}, timestamp = {Wed, 01 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ijpp/LohJ08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cf/Loh08, author = {Gabriel H. Loh}, editor = {Alex Ram{\'{\i}}rez and Gianfranco Bilardi and Michael Gschwind}, title = {A modular 3d processor for flexible product design and technology migration}, booktitle = {Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008}, pages = {159--170}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1366230.1366261}, doi = {10.1145/1366230.1366261}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cf/Loh08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/SubramaniamPL08, author = {Samantika Subramaniam and Milos Prvulovic and Gabriel H. Loh}, title = {{PEEP:} Exploiting predictability of memory dependences in {SMT} processors}, booktitle = {14th International Conference on High-Performance Computer Architecture {(HPCA-14} 2008), 16-20 February 2008, Salt Lake City, UT, {USA}}, pages = {137--148}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/HPCA.2008.4658634}, doi = {10.1109/HPCA.2008.4658634}, timestamp = {Wed, 16 Oct 2019 14:14:50 +0200}, biburl = {https://dblp.org/rec/conf/hpca/SubramaniamPL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/Loh08, author = {Gabriel H. Loh}, title = {3D-Stacked Memory Architectures for Multi-core Processors}, booktitle = {35th International Symposium on Computer Architecture {(ISCA} 2008), June 21-25, 2008, Beijing, China}, pages = {453--464}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ISCA.2008.15}, doi = {10.1109/ISCA.2008.15}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/Loh08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sbac-pad/BreternitzLBRSAW08, author = {Maur{\'{\i}}cio Breternitz Jr. and Gabriel H. Loh and Bryan Black and Jeff Rupley and Peter G. Sassone and Wesley Attrot and Youfeng Wu}, editor = {Edson Norberto C{\'{a}}cares and Walfredo Cirne and Viktor K. Prasanna}, title = {A Segmented Bloom Filter Algorithm for Efficient Predictors}, booktitle = {20th International Symposium on Computer Architecture and High Performance Computing, {SBAC-PAD} 2008, October 29 - November 1, 2008, Campo Grande, MS, Brazil}, pages = {123--130}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/SBAC-PAD.2008.24}, doi = {10.1109/SBAC-PAD.2008.24}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sbac-pad/BreternitzLBRSAW08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/LohXB07, author = {Gabriel H. Loh and Yuan Xie and Bryan Black}, title = {Processor Design in 3D Die-Stacking Technologies}, journal = {{IEEE} Micro}, volume = {27}, number = {3}, pages = {31--48}, year = {2007}, url = {https://doi.org/10.1109/MM.2007.59}, doi = {10.1109/MM.2007.59}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/LohXB07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HealyVEBLLL07, author = {Michael B. Healy and Mario Vittes and Mongkol Ekpanyapong and Chinnakrishnan S. Ballapuram and Sung Kyu Lim and Hsien{-}Hsin S. Lee and Gabriel H. Loh}, title = {Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {26}, number = {1}, pages = {38--52}, year = {2007}, url = {https://doi.org/10.1109/TCAD.2006.883925}, doi = {10.1109/TCAD.2006.883925}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HealyVEBLLL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tecs/SassoneWL07, author = {Peter G. Sassone and D. Scott Wills and Gabriel H. Loh}, title = {Static strands: Safely exposing dependence chains for increasing embedded power efficiency}, journal = {{ACM} Trans. Embed. Comput. Syst.}, volume = {6}, number = {4}, pages = {24}, year = {2007}, url = {https://doi.org/10.1145/1274858.1274862}, doi = {10.1145/1274858.1274862}, timestamp = {Tue, 08 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tecs/SassoneWL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/PuttaswamyL07, author = {Kiran Puttaswamy and Gabriel H. Loh}, title = {Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors}, booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007, San Diego, CA, USA, June 4-8, 2007}, pages = {622--625}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1145/1278480.1278636}, doi = {10.1145/1278480.1278636}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/PuttaswamyL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/PuttaswamyL07, author = {Kiran Puttaswamy and Gabriel H. Loh}, title = {Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors}, booktitle = {13st International Conference on High-Performance Computer Architecture {(HPCA-13} 2007), 10-14 February 2007, Phoenix, Arizona, {USA}}, pages = {193--204}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/HPCA.2007.346197}, doi = {10.1109/HPCA.2007.346197}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/PuttaswamyL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/SassoneRBLB07, author = {Peter G. Sassone and Jeff Rupley and Edward Brekelbaum and Gabriel H. Loh and Bryan Black}, editor = {Dean M. Tullsen and Brad Calder}, title = {Matrix scheduler reloaded}, booktitle = {34th International Symposium on Computer Architecture {(ISCA} 2007), June 9-13, 2007, San Diego, California, {USA}}, pages = {335--346}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1250662.1250704}, doi = {10.1145/1250662.1250704}, timestamp = {Fri, 09 Jul 2021 15:51:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/SassoneRBLB07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jetc/XieLBB06, author = {Yuan Xie and Gabriel H. Loh and Bryan Black and Kerry Bernstein}, title = {Design space exploration for 3D architectures}, journal = {{ACM} J. Emerg. Technol. Comput. Syst.}, volume = {2}, number = {2}, pages = {65--103}, year = {2006}, url = {https://doi.org/10.1145/1148015.1148016}, doi = {10.1145/1148015.1148016}, timestamp = {Mon, 08 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jetc/XieLBB06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cases/BallapuramPLL06, author = {Chinnakrishnan S. Ballapuram and Kiran Puttaswamy and Gabriel H. Loh and Hsien{-}Hsin S. Lee}, editor = {Seongsoo Hong and Wayne H. Wolf and Kriszti{\'{a}}n Flautner and Taewhan Kim}, title = {Entropy-based low power data {TLB} design}, booktitle = {Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, {CASES} 2006, Seoul, Korea, October 22-25, 2006}, pages = {304--311}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1176760.1176797}, doi = {10.1145/1176760.1176797}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cases/BallapuramPLL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/HealyVEBLLL06, author = {Michael B. Healy and Mario Vittes and Mongkol Ekpanyapong and Chinnakrishnan S. Ballapuram and Sung Kyu Lim and Hsien{-}Hsin S. Lee and Gabriel H. Loh}, editor = {Georges G. E. Gielen}, title = {Microarchitectural floorplanning under performance and thermal tradeoff}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2006, Munich, Germany, March 6-10, 2006}, pages = {1288--1293}, publisher = {European Design and Automation Association, Leuven, Belgium}, year = {2006}, url = {https://doi.org/10.1109/DATE.2006.244102}, doi = {10.1109/DATE.2006.244102}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/HealyVEBLLL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/PuttaswamyL06, author = {Kiran Puttaswamy and Gabriel H. Loh}, editor = {Gang Qu and Yehea I. Ismail and Narayanan Vijaykrishnan and Hai Zhou}, title = {Thermal analysis of a 3D die-stacked high-performance microprocessor}, booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006, Philadelphia, PA, USA, April 30 - May 1, 2006}, pages = {19--24}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1127908.1127915}, doi = {10.1145/1127908.1127915}, timestamp = {Wed, 16 Aug 2023 21:16:32 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/PuttaswamyL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/PuttaswamyL06a, author = {Kiran Puttaswamy and Gabriel H. Loh}, editor = {Gang Qu and Yehea I. Ismail and Narayanan Vijaykrishnan and Hai Zhou}, title = {Dynamic instruction schedulers in a 3-dimensional integration technology}, booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006, Philadelphia, PA, USA, April 30 - May 1, 2006}, pages = {153--158}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1127908.1127946}, doi = {10.1145/1127908.1127946}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/PuttaswamyL06a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/SubramaniamL06, author = {Samantika Subramaniam and Gabriel H. Loh}, title = {Store vectors for scalable memory dependence prediction and scheduling}, booktitle = {12th International Symposium on High-Performance Computer Architecture, {HPCA-12} 2006, Austin, Texas, USA, February 11-15, 2006}, pages = {65--76}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/HPCA.2006.1598113}, doi = {10.1109/HPCA.2006.1598113}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/SubramaniamL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/PuttaswamyL06, author = {Kiran Puttaswamy and Gabriel H. Loh}, title = {The impact of 3-dimensional integration on the design of arithmetic units}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24 May 2006, Island of Kos, Greece}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ISCAS.2006.1693742}, doi = {10.1109/ISCAS.2006.1693742}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/PuttaswamyL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispass/Loh06, author = {Gabriel H. Loh}, title = {Revisiting the performance impact of branch predictor latencies}, booktitle = {2006 {IEEE} International Symposium on Performance Analysis of Systems and Software, {ISPASS} 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings}, pages = {59--69}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ISPASS.2006.1620790}, doi = {10.1109/ISPASS.2006.1620790}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispass/Loh06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isvlsi/PuttaswamyL06, author = {Kiran Puttaswamy and Gabriel H. Loh}, title = {Implementing Register Files for High-Performance Microprocessors in a Die-Stacked {(3D)} Technology}, booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI} 2006), 2-3 March 2006, Karlsruhe, Germany}, pages = {384--392}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ISVLSI.2006.56}, doi = {10.1109/ISVLSI.2006.56}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/PuttaswamyL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/SubramaniamL06, author = {Samantika Subramaniam and Gabriel H. Loh}, title = {Fire-and-Forget: Load/Store Scheduling with No Store Queue at All}, booktitle = {39th Annual {IEEE/ACM} International Symposium on Microarchitecture {(MICRO-39} 2006), 9-13 December 2006, Orlando, Florida, {USA}}, pages = {273--284}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/MICRO.2006.26}, doi = {10.1109/MICRO.2006.26}, timestamp = {Tue, 31 May 2022 14:39:58 +0200}, biburl = {https://dblp.org/rec/conf/micro/SubramaniamL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/SubramanianSL06, author = {Ranjith Subramanian and Yannis Smaragdakis and Gabriel H. Loh}, title = {Adaptive Caches: Effective Shaping of Cache Behavior to Workloads}, booktitle = {39th Annual {IEEE/ACM} International Symposium on Microarchitecture {(MICRO-39} 2006), 9-13 December 2006, Orlando, Florida, {USA}}, pages = {385--396}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/MICRO.2006.7}, doi = {10.1109/MICRO.2006.7}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/SubramanianSL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/BlackABDJLMMNPRRSSW06, author = {Bryan Black and Murali Annavaram and Ned Brekelbaum and John DeVale and Lei Jiang and Gabriel H. Loh and Don McCaule and Patrick Morrow and Donald W. Nelson and Daniel Pantuso and Paul Reed and Jeff Rupley and Sadasivan Shankar and John Paul Shen and Clair Webb}, title = {Die Stacking {(3D)} Microarchitecture}, booktitle = {39th Annual {IEEE/ACM} International Symposium on Microarchitecture {(MICRO-39} 2006), 9-13 December 2006, Orlando, Florida, {USA}}, pages = {469--479}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/MICRO.2006.18}, doi = {10.1109/MICRO.2006.18}, timestamp = {Tue, 31 May 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/micro/BlackABDJLMMNPRRSSW06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sbac-pad/JimenezL06, author = {Daniel A. Jim{\'{e}}nez and Gabriel H. Loh}, title = {Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors}, booktitle = {18th Symposium on Computer Architecture and High Performance Computing {(SBAC-PAD} 2006), 17-20 October 2006, Ouro Preto, Minas Gerais, Brazil}, pages = {55--62}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/SBAC-PAD.2006.14}, doi = {10.1109/SBAC-PAD.2006.14}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sbac-pad/JimenezL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jilp/Loh05, author = {Gabriel H. Loh}, title = {Deconstructing the Frankenpredictor for Implementable Branch Predictors}, journal = {J. Instr. Level Parallelism}, volume = {7}, year = {2005}, url = {http://www.jilp.org/vol7/v7paper8.pdf}, timestamp = {Mon, 11 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jilp/Loh05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/Loh05, author = {Gabriel H. Loh}, title = {A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction}, booktitle = {14th International Conference on Parallel Architectures and Compilation Techniques {(PACT} 2005), 17-21 September 2005, St. Louis, MO, {USA}}, pages = {243--254}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/PACT.2005.6}, doi = {10.1109/PACT.2005.6}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/IEEEpact/Loh05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/PuttaswamyL05, author = {Kiran Puttaswamy and Gabriel H. Loh}, title = {Implementing Caches in a 3D Technology for High Performance Processors}, booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5 October 2005, San Jose, CA, {USA}}, pages = {525--532}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICCD.2005.65}, doi = {10.1109/ICCD.2005.65}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/PuttaswamyL05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispass/Loh05, author = {Gabriel H. Loh}, title = {Simulation Differences Between Academia and Industry: {A} Branch Prediction Case Study}, booktitle = {{IEEE} International Symposium on Performance Analysis of Systems and Software, {ISPASS} 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings}, pages = {21--31}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ISPASS.2005.1430556}, doi = {10.1109/ISPASS.2005.1430556}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispass/Loh05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/lctrts/SassoneWL05, author = {Peter G. Sassone and D. Scott Wills and Gabriel H. Loh}, editor = {Yunheung Paek and Rajiv Gupta}, title = {Static strands: safely collapsing dependence chains for increasing embedded power efficiency}, booktitle = {Proceedings of the 2005 {ACM} {SIGPLAN/SIGBED} Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005}, pages = {127--136}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1065910.1065929}, doi = {10.1145/1065910.1065929}, timestamp = {Fri, 25 Jun 2021 14:48:54 +0200}, biburl = {https://dblp.org/rec/conf/lctrts/SassoneWL05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jilp/Loh03, author = {Gabriel H. Loh}, title = {Width-Partitioned Load Value Predictors}, journal = {J. Instr. Level Parallelism}, volume = {5}, year = {2003}, url = {http://www.jilp.org/vol5/v5paper11.pdf}, timestamp = {Mon, 11 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jilp/Loh03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jilp/LohHK03, author = {Gabriel H. Loh and Dana S. Henry and Arvind Krishnamurthy}, title = {Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors}, journal = {J. Instr. Level Parallelism}, volume = {5}, year = {2003}, url = {http://www.jilp.org/vol5/v5paper8.pdf}, timestamp = {Mon, 11 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jilp/LohHK03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/mst/KuszmaulHL02, author = {Bradley C. Kuszmaul and Dana S. Henry and Gabriel H. Loh}, title = {A Comparison of Asymptotically Scalable Superscalar Processors}, journal = {Theory Comput. Syst.}, volume = {35}, number = {2}, pages = {129--150}, year = {2002}, url = {https://doi.org/10.1007/s00224-001-1029-z}, doi = {10.1007/S00224-001-1029-Z}, timestamp = {Sun, 28 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/mst/KuszmaulHL02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/IEEEpact/LohH02, author = {Gabriel H. Loh and Dana S. Henry}, title = {Predicting Conditional Branches With Fusion-Based Hybrid Predictors}, booktitle = {2002 International Conference on Parallel Architectures and Compilation Techniques {(PACT} 2002), 22-25 September 2002, Charlottesville, VA, {USA}}, pages = {165--176}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/PACT.2002.1106015}, doi = {10.1109/PACT.2002.1106015}, timestamp = {Tue, 31 May 2022 13:36:33 +0200}, biburl = {https://dblp.org/rec/conf/IEEEpact/LohH02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ieaaie/LohH02, author = {Gabriel H. Loh and Dana S. Henry}, editor = {Tim Hendtlass and Moonis Ali}, title = {Applying Machine Learning for Ensemble Branch Predictors}, booktitle = {Developments in Applied Artificial Intelligence, 15th International Conference on Industrial and Engineering, Applications of Artificial Intelligence and Expert Systems, {IEA/AIE} 2002, Cairns, Australia, June 17-20, 2002, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {2358}, pages = {264--274}, publisher = {Springer}, year = {2002}, url = {https://doi.org/10.1007/3-540-48035-8\_26}, doi = {10.1007/3-540-48035-8\_26}, timestamp = {Tue, 14 May 2019 10:00:37 +0200}, biburl = {https://dblp.org/rec/conf/ieaaie/LohH02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ishpc/HenryLS02, author = {Dana S. Henry and Gabriel H. Loh and Rahul Sami}, editor = {Hans P. Zima and Kazuki Joe and Mitsuhisa Sato and Yoshiki Seo and Masaaki Shimasaki}, title = {Speculative Clustered Caches for Clustered Processors}, booktitle = {High Performance Computing, 4th International Symposium, {ISHPC} 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {2327}, pages = {281--290}, publisher = {Springer}, year = {2002}, url = {https://doi.org/10.1007/3-540-47847-7\_24}, doi = {10.1007/3-540-47847-7\_24}, timestamp = {Tue, 14 May 2019 10:00:49 +0200}, biburl = {https://dblp.org/rec/conf/ishpc/HenryLS02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/Loh02, author = {Gabriel H. Loh}, editor = {Erik R. Altman and Kemal Ebcioglu and Scott A. Mahlke and B. Ramakrishna Rau and Sanjay J. Patel}, title = {Exploiting data-width locality to increase superscalar execution bandwidth}, booktitle = {Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002}, pages = {395--405}, publisher = {{ACM/IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/MICRO.2002.1176266}, doi = {10.1109/MICRO.2002.1176266}, timestamp = {Tue, 31 May 2022 14:39:58 +0200}, biburl = {https://dblp.org/rec/conf/micro/Loh02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sigmetrics/Loh01, author = {Gabriel H. Loh}, editor = {Mary K. Vernon}, title = {A time-stamping algorithm for efficient performance estimation of superscalar processors}, booktitle = {Proceedings of the Joint International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS/Performance 2001, June 16-20, 2001, Cambridge, MA, {USA}}, pages = {72--81}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/378420.378437}, doi = {10.1145/378420.378437}, timestamp = {Fri, 30 Jul 2021 16:13:33 +0200}, biburl = {https://dblp.org/rec/conf/sigmetrics/Loh01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/HenryKLS00, author = {Dana S. Henry and Bradley C. Kuszmaul and Gabriel H. Loh and Rahul Sami}, editor = {Alan D. Berenbaum and Joel S. Emer}, title = {Circuits for wide-window superscalar processors}, booktitle = {27th International Symposium on Computer Architecture {(ISCA} 2000), June 10-14, 2000, Vancouver, BC, Canada}, pages = {236--247}, publisher = {{IEEE} Computer Society}, year = {2000}, url = {https://doi.ieeecomputersociety.org/10.1109/ISCA.2000.854394}, doi = {10.1109/ISCA.2000.854394}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/HenryKLS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/spaa/KuszmaulHL99, author = {Bradley C. Kuszmaul and Dana S. Henry and Gabriel H. Loh}, editor = {Gary L. Miller and Vijaya Ramachandran}, title = {A Comparison of Scalable Superscalar Processors}, booktitle = {Proceedings of the Eleventh Annual {ACM} Symposium on Parallel Algorithms and Architectures, {SPAA} '99, Saint-Malo, France, June 27-30, 1999}, pages = {126--137}, publisher = {{ACM}}, year = {1999}, url = {https://doi.org/10.1145/305619.305633}, doi = {10.1145/305619.305633}, timestamp = {Wed, 21 Nov 2018 12:27:44 +0100}, biburl = {https://dblp.org/rec/conf/spaa/KuszmaulHL99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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