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BibTeX records: Guangyi Lu
@article{DBLP:journals/tcad/WeiCGWLGWLW23, author = {Jiahao Wei and Weiqi Chen and Yajie Gong and Qi Wu and Guangyi Lu and Wei Gao and Lihui Wang and Mei Li and Haiming Wang}, title = {Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {42}, number = {12}, pages = {4413--4422}, year = {2023}, url = {https://doi.org/10.1109/TCAD.2023.3294449}, doi = {10.1109/TCAD.2023.3294449}, timestamp = {Sun, 10 Dec 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/WeiCGWLGWLW23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/access/WangLW20a, author = {Yize Wang and Guangyi Lu and Yuan Wang}, title = {A New Behavioral Model of Gate-Grounded {NMOS} for Simulating Snapback Characteristics}, journal = {{IEEE} Access}, volume = {8}, pages = {64730--64738}, year = {2020}, url = {https://doi.org/10.1109/ACCESS.2020.2972042}, doi = {10.1109/ACCESS.2020.2972042}, timestamp = {Fri, 22 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/access/WangLW20a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/LuWZWH018, author = {Guangyi Lu and Yuan Wang and Lizhong Zhang and Yize Wang and Ru Huang and Xing Zhang}, title = {Investigation on the Gate Bias Voltage of BigFET in Power-rail {ESD} Clamp Circuit for Enhanced Transient Noise Immunity}, booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018, 27-30 May 2018, Florence, Italy}, pages = {1--5}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/ISCAS.2018.8350905}, doi = {10.1109/ISCAS.2018.8350905}, timestamp = {Fri, 18 Oct 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iscas/LuWZWH018.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieiceee/WangWLCZ17, author = {Yize Wang and Yuan Wang and Guangyi Lu and Jian Cao and Xing Zhang}, title = {A novel TLP-based method to deliver {IEC} 61000-4-2 {ESD} stress}, journal = {{IEICE} Electron. Express}, volume = {14}, number = {9}, pages = {20170163}, year = {2017}, url = {https://doi.org/10.1587/elex.14.20170163}, doi = {10.1587/ELEX.14.20170163}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieiceee/WangWLCZ17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/WangLWZ17, author = {Yuan Wang and Guangyi Lu and Yize Wang and Xing Zhang}, title = {Power-Rail {ESD} Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness}, journal = {{IEICE} Trans. Electron.}, volume = {100-C}, number = {3}, pages = {344--347}, year = {2017}, url = {https://doi.org/10.1587/transele.E100.C.344}, doi = {10.1587/TRANSELE.E100.C.344}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/WangLWZ17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/LuWWZ17, author = {Guangyi Lu and Yuan Wang and Yize Wang and Xing Zhang}, title = {Power-rail {ESD} clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V {CMOS} process}, booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017, Baltimore, MD, USA, May 28-31, 2017}, pages = {1--4}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/ISCAS.2017.8050381}, doi = {10.1109/ISCAS.2017.8050381}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/LuWWZ17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/chinaf/WangLGCJZ16, author = {Yuan Wang and Guangyi Lu and Haibing Guo and Jian Cao and Song Jia and Xing Zhang}, title = {Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm {CMOS} process}, journal = {Sci. China Inf. Sci.}, volume = {59}, number = {4}, pages = {042407:1--042407:9}, year = {2016}, url = {https://doi.org/10.1007/s11432-015-5398-3}, doi = {10.1007/S11432-015-5398-3}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/chinaf/WangLGCJZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/chinaf/CaoXWLZ16, author = {Jian Cao and Jingya Xu and Yuan Wang and Guangyi Lu and Xing Zhang}, title = {A compact {SCR} model using advanced {BJT} models and standard {SPICE} elements}, journal = {Sci. China Inf. Sci.}, volume = {59}, number = {10}, pages = {109302}, year = {2016}, url = {https://doi.org/10.1007/s11432-016-0072-3}, doi = {10.1007/S11432-016-0072-3}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/chinaf/CaoXWLZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/chinaf/LuWZCZ16, author = {Guangyi Lu and Yuan Wang and Lizhong Zhang and Jian Cao and Xing Zhang}, title = {Design of a novel static-triggered power-rail {ESD} clamp circuit in a 65-nm {CMOS} process}, journal = {Sci. China Inf. Sci.}, volume = {59}, number = {12}, pages = {122401:1--122401:9}, year = {2016}, url = {https://doi.org/10.1007/s11432-015-5455-y}, doi = {10.1007/S11432-015-5455-Y}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/chinaf/LuWZCZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieiceee/CaoWWLZ16, author = {Jian Cao and Yize Wang and Yuan Wang and Guangyi Lu and Xing Zhang}, title = {A novel {SPICE} circuit model of electrostatic discharge {(ESD)} generator}, journal = {{IEICE} Electron. Express}, volume = {13}, number = {9}, pages = {20160238}, year = {2016}, url = {https://doi.org/10.1587/elex.13.20160238}, doi = {10.1587/ELEX.13.20160238}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieiceee/CaoWWLZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ieicet/LuWZ16, author = {Guangyi Lu and Yuan Wang and Xing Zhang}, title = {Optimization on Layout Strategy of Gate-Grounded {NMOS} for On-Chip {ESD} Protection in a 65-nm {CMOS} Process}, journal = {{IEICE} Trans. Electron.}, volume = {99-C}, number = {5}, pages = {590--596}, year = {2016}, url = {https://doi.org/10.1587/transele.E99.C.590}, doi = {10.1587/TRANSELE.E99.C.590}, timestamp = {Sat, 11 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ieicet/LuWZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/LuWCJZ16, author = {Guangyi Lu and Yuan Wang and Jian Cao and Song Jia and Xing Zhang}, title = {A novel low-leakage power-rail {ESD} clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications}, booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016, Montr{\'{e}}al, QC, Canada, May 22-25, 2016}, pages = {265--268}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ISCAS.2016.7527221}, doi = {10.1109/ISCAS.2016.7527221}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iscas/LuWCJZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/chinaf/LuWZCJZ15, author = {Guangyi Lu and Yuan Wang and Lizhong Zhang and Jian Cao and Song Jia and Xing Zhang}, title = {Investigation on the layout strategy of ggNMOS {ESD} protection devices for uniform conduction behavior and optimal width scaling}, journal = {Sci. China Inf. Sci.}, volume = {58}, number = {4}, pages = {1--9}, year = {2015}, url = {https://doi.org/10.1007/s11432-014-5245-y}, doi = {10.1007/S11432-014-5245-Y}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/chinaf/LuWZCJZ15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asicon/CaoYWLZ15, author = {Jian Cao and Zhenxu Ye and Yuan Wang and Guangyi Lu and Xing Zhang}, title = {A low-leakage power clamp {ESD} protection circuit with prolonged {ESD} discharge time and compact detection network}, booktitle = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015, Chengdu, China, November 3-6, 2015}, pages = {1--4}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/ASICON.2015.7516982}, doi = {10.1109/ASICON.2015.7516982}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/asicon/CaoYWLZ15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asicon/HanWLCZ15, author = {Nan Han and Yuan Wang and Guangyi Lu and Jian Cao and Xing Zhang}, title = {Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level {ESD} protection}, booktitle = {2015 {IEEE} 11th International Conference on ASIC, {ASICON} 2015, Chengdu, China, November 3-6, 2015}, pages = {1--4}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/ASICON.2015.7517133}, doi = {10.1109/ASICON.2015.7517133}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/asicon/HanWLCZ15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asicon/LuWCJZZ13, author = {Guangyi Lu and Yuan Wang and Jian Cao and Song Jia and Ganggang Zhang and Xing Zhang}, title = {Novel gate-voltage-bias techniques for gate-coupled {MOS} {(GCMOS)} {ESD} protection circuits}, booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen, China, October 28-31, 2013}, pages = {1--4}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/ASICON.2013.6811960}, doi = {10.1109/ASICON.2013.6811960}, timestamp = {Fri, 15 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/asicon/LuWCJZZ13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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