BibTeX records: Shengshuo Lu

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@article{DBLP:journals/corr/abs-1808-02513,
  author    = {Parker Hill and
               Babak Zamirai and
               Shengshuo Lu and
               Yu{-}Wei Chao and
               Michael Laurenzano and
               Mehrzad Samadi and
               Marios C. Papaefthymiou and
               Scott A. Mahlke and
               Thomas F. Wenisch and
               Jia Deng and
               Lingjia Tang and
               Jason Mars},
  title     = {Rethinking Numerical Representations for Deep Neural Networks},
  journal   = {CoRR},
  volume    = {abs/1808.02513},
  year      = {2018},
  url       = {http://arxiv.org/abs/1808.02513},
  archivePrefix = {arXiv},
  eprint    = {1808.02513},
  timestamp = {Sun, 02 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/corr/abs-1808-02513},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LuZP17,
  author    = {Shengshuo Lu and
               Zhengya Zhang and
               Marios C. Papaefthymiou},
  title     = {A 1.25pJ/bit 0.048mm\({}^{\mbox{2}}\) {AES} core with {DPA} resistance
               for IoT devices},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
               Korea (South), November 6-8, 2017},
  pages     = {65--68},
  year      = {2017},
  crossref  = {DBLP:conf/asscc/2017},
  url       = {https://doi.org/10.1109/ASSCC.2017.8240217},
  doi       = {10.1109/ASSCC.2017.8240217},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asscc/LuZP17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ChenLFBDMK17,
  author    = {Yajing Chen and
               Shengshuo Lu and
               Cheng Fu and
               David T. Blaauw and
               Ronald Dreslinski Jr. and
               Trevor N. Mudge and
               Hun{-}Seok Kim},
  title     = {A Programmable Galois Field Processor for the Internet of Things},
  booktitle = {Proceedings of the 44th Annual International Symposium on Computer
               Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017},
  pages     = {55--68},
  year      = {2017},
  crossref  = {DBLP:conf/isca/2017},
  url       = {https://doi.org/10.1145/3079856.3080227},
  doi       = {10.1145/3079856.3080227},
  timestamp = {Tue, 06 Nov 2018 11:07:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/ChenLFBDMK17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/LuZP16,
  author    = {Shengshuo Lu and
               Zhengya Zhang and
               Marios C. Papaefthymiou},
  title     = {A 5.5GHz 0.84TOPS/mm\({}^{\mbox{2}}\) neural network engine with stream
               architecture and resonant clock mesh},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {133--136},
  year      = {2016},
  crossref  = {DBLP:conf/asscc/2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844153},
  doi       = {10.1109/ASSCC.2016.7844153},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asscc/LuZP16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/ChenLKBDM16,
  author    = {Yajing Chen and
               Shengshuo Lu and
               Hun{-}Seok Kim and
               David T. Blaauw and
               Ronald G. Dreslinski and
               Trevor N. Mudge},
  title     = {A low power software-defined-radio baseband processor for the Internet
               of Things},
  booktitle = {2016 {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2016, Barcelona, Spain, March 12-16, 2016},
  pages     = {40--51},
  year      = {2016},
  crossref  = {DBLP:conf/hpca/2016},
  url       = {https://doi.org/10.1109/HPCA.2016.7446052},
  doi       = {10.1109/HPCA.2016.7446052},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/ChenLKBDM16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LuZP15,
  author    = {Shengshuo Lu and
               Zhengya Zhang and
               Marios C. Papaefthymiou},
  title     = {1.32GHz high-throughput charge-recovery {AES} core with resistance
               to {DPA} attacks},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
               2015},
  pages     = {246},
  year      = {2015},
  crossref  = {DBLP:conf/vlsic/2015},
  url       = {https://doi.org/10.1109/VLSIC.2015.7231274},
  doi       = {10.1109/VLSIC.2015.7231274},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/LuZP15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asscc/2017,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
               Korea (South), November 6-8, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8226344/proceeding},
  isbn      = {978-1-5386-3178-2},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asscc/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2017,
  title     = {Proceedings of the 44th Annual International Symposium on Computer
               Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3079856},
  doi       = {10.1145/3079856},
  isbn      = {978-1-4503-4892-8},
  timestamp = {Tue, 06 Nov 2018 11:07:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asscc/2016,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7833314/proceeding},
  isbn      = {978-1-5090-3699-8},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asscc/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2016,
  title     = {2016 {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2016, Barcelona, Spain, March 12-16, 2016},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7440961/proceeding},
  isbn      = {978-1-4673-9211-2},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2015,
  title     = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
               2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7196579/proceeding},
  isbn      = {978-4-86348-502-0},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsic/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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