BibTeX records: Normann Mertig

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@article{DBLP:journals/jssc/YamamotoKAMTYTS21,
  author       = {Kasho Yamamoto and
                  Kazushi Kawamura and
                  Kota Ando and
                  Normann Mertig and
                  Takashi Takemoto and
                  Masanao Yamaoka and
                  Hiroshi Teramoto and
                  Akira Sakai and
                  Shinya Takamaeda{-}Yamazaki and
                  Masato Motomura},
  title        = {{STATICA:} {A} 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once
                  Architecture for Combinatorial Optimization With Complete Spin-Spin
                  Interactions},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {56},
  number       = {1},
  pages        = {165--178},
  year         = {2021},
  url          = {https://doi.org/10.1109/JSSC.2020.3027702},
  doi          = {10.1109/JSSC.2020.3027702},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/YamamotoKAMTYTS21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/soco/SugieYMTTNTMYK21,
  author       = {Yuya Sugie and
                  Yuki Yoshida and
                  Normann Mertig and
                  Takashi Takemoto and
                  Hiroshi Teramoto and
                  Atsuyoshi Nakamura and
                  Ichigaku Takigawa and
                  Shin{-}ichi Minato and
                  Masanao Yamaoka and
                  Tamiki Komatsuzaki},
  title        = {Minor-embedding heuristics for large-scale annealing processors with
                  sparse hardware graphs of up to 102, 400 nodes},
  journal      = {Soft Comput.},
  volume       = {25},
  number       = {3},
  pages        = {1731--1749},
  year         = {2021},
  url          = {https://doi.org/10.1007/s00500-020-05502-6},
  doi          = {10.1007/S00500-020-05502-6},
  timestamp    = {Tue, 02 Mar 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/soco/SugieYMTTNTMYK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YamamotoAMTYTST20,
  author       = {Kasho Yamamoto and
                  Kota Ando and
                  Normann Mertig and
                  Takashi Takemoto and
                  Masanao Yamaoka and
                  Hiroshi Teramoto and
                  Akira Sakai and
                  Shinya Takamaeda{-}Yamazaki and
                  Masato Motomura},
  title        = {7.3 {STATICA:} {A} 512-Spin 0.25M-Weight Full-Digital Annealing Processor
                  with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial
                  Optimization with Complete Spin-Spin Interactions},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {138--140},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062965},
  doi          = {10.1109/ISSCC19947.2020.9062965},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YamamotoAMTYTST20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/abs-2004-03819,
  author       = {Yuya Sugie and
                  Yuki Yoshida and
                  Normann Mertig and
                  Takashi Takemoto and
                  Hiroshi Teramoto and
                  Atsuyoshi Nakamura and
                  Ichigaku Takigawa and
                  Shin{-}ichi Minato and
                  Masanao Yamaoka and
                  Tamiki Komatsuzaki},
  title        = {Minor-embedding heuristics for large-scale annealing processors with
                  sparse hardware graphs of up to 102, 400 nodes},
  journal      = {CoRR},
  volume       = {abs/2004.03819},
  year         = {2020},
  url          = {https://arxiv.org/abs/2004.03819},
  eprinttype    = {arXiv},
  eprint       = {2004.03819},
  timestamp    = {Sat, 23 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2004-03819.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/reconfig/TakemotoMHSTNTM18,
  author       = {Takashi Takemoto and
                  Normann Mertig and
                  Masato Hayashi and
                  Saki Susa{-}Tanaka and
                  Hiroshi Teramoto and
                  Atsuyoshi Nakamura and
                  Ichigaku Takigawa and
                  Shin{-}ichi Minato and
                  Tamiki Komatsuzaki and
                  Masanao Yamaoka},
  editor       = {David Andrews and
                  Ren{\'{e}} Cumplido and
                  Claudia Feregrino and
                  Dirk Stroobandt},
  title        = {FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated
                  Hyperparameter Search},
  booktitle    = {2018 International Conference on ReConFigurable Computing and FPGAs,
                  ReConFig 2018, Cancun, Mexico, December 3-5, 2018},
  pages        = {1--8},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/RECONFIG.2018.8641713},
  doi          = {10.1109/RECONFIG.2018.8641713},
  timestamp    = {Wed, 07 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/reconfig/TakemotoMHSTNTM18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/tpnc/SugieYMTTNTMYK18,
  author       = {Yuya Sugie and
                  Yuki Yoshida and
                  Normann Mertig and
                  Takashi Takemoto and
                  Hiroshi Teramoto and
                  Atsuyoshi Nakamura and
                  Ichigaku Takigawa and
                  Shin{-}ichi Minato and
                  Masanao Yamaoka and
                  Tamiki Komatsuzaki},
  editor       = {David Fagan and
                  Carlos Mart{\'{\i}}n{-}Vide and
                  Michael O'Neill and
                  Miguel A. Vega{-}Rodr{\'{\i}}guez},
  title        = {Graph Minors from Simulated Annealing for Annealing Machines with
                  Sparse Connectivity},
  booktitle    = {Theory and Practice of Natural Computing - 7th International Conference,
                  {TPNC} 2018, Dublin, Ireland, December 12-14, 2018, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {11324},
  pages        = {111--123},
  publisher    = {Springer},
  year         = {2018},
  url          = {https://doi.org/10.1007/978-3-030-04070-3\_9},
  doi          = {10.1007/978-3-030-04070-3\_9},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/tpnc/SugieYMTTNTMYK18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}