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ORCIDBibTeX records: Alan Mishchenko
@article{DBLP:journals/tcad/HuangJM23,
author = {Yu{-}Shan Huang and
Jie{-}Hong R. Jiang and
Alan Mishchenko},
title = {Quantized Neural Network Synthesis for Direct Logic Circuit Implementation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {2},
pages = {473--482},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3183547},
doi = {10.1109/TCAD.2022.3183547},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuangJM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CalvinoMSMMX23,
author = {Alessandro Tempia Calvino and
Alan Mishchenko and
Herman Schmit and
Ethan Mahintorabi and
Giovanni De Micheli and
Xiaoqing Xu},
title = {Improving Standard-Cell Design Flow using Factored Form Optimization},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247905},
doi = {10.1109/DAC56929.2023.10247905},
timestamp = {Sun, 24 Sep 2023 13:31:06 +0200},
biburl = {https://dblp.org/rec/conf/dac/CalvinoMSMMX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BarzenRHKMGW23,
author = {Benjamin Lukas Cajus Barzen and
Arya Reais{-}Parsi and
Eddie Hung and
Minwoo Kang and
Alan Mishchenko and
Jonathan W. Greene and
John Wawrzynek},
title = {Narrowing the Synthesis Gap: Academic {FPGA} Synthesis is Catching
Up With the Industry},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137310},
doi = {10.23919/DATE56975.2023.10137310},
timestamp = {Wed, 07 Jun 2023 22:08:03 +0200},
biburl = {https://dblp.org/rec/conf/date/BarzenRHKMGW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiLMY23,
author = {Yingjie Li and
Mingju Liu and
Alan Mishchenko and
Cunxi Yu},
title = {Invited Paper: Verilog-to-PyG - {A} Framework for Graph Learning and
Augmentation on {RTL} Designs},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323741},
doi = {10.1109/ICCAD57390.2023.10323741},
timestamp = {Wed, 03 Jan 2024 08:34:26 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LiLMY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2310-07846,
author = {Yingjie Li and
Mingju Liu and
Mark Ren and
Alan Mishchenko and
Cunxi Yu},
title = {DAG-aware Synthesis Orchestration},
journal = {CoRR},
volume = {abs/2310.07846},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2310.07846},
doi = {10.48550/ARXIV.2310.07846},
eprinttype = {arXiv},
eprint = {2310.07846},
timestamp = {Tue, 24 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2310-07846.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2311-05722,
author = {Yingjie Li and
Mingju Liu and
Alan Mishchenko and
Cunxi Yu},
title = {Verilog-to-PyG - {A} Framework for Graph Learning and Augmentation
on {RTL} Designs},
journal = {CoRR},
volume = {abs/2311.05722},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2311.05722},
doi = {10.48550/ARXIV.2311.05722},
eprinttype = {arXiv},
eprint = {2311.05722},
timestamp = {Tue, 14 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2311-05722.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2311-09967,
author = {Dewmini Sudara Marakkalage and
Eleonora Testa and
Walter Lau Neto and
Alan Mishchenko and
Giovanni De Micheli and
Luca G. Amar{\`{u}}},
title = {Scalable Sequential Optimization Under Observability Don't Cares},
journal = {CoRR},
volume = {abs/2311.09967},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2311.09967},
doi = {10.48550/ARXIV.2311.09967},
eprinttype = {arXiv},
eprint = {2311.09967},
timestamp = {Wed, 22 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2311-09967.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeRMBM22,
author = {Siang{-}Yun Lee and
Heinz Riener and
Alan Mishchenko and
Robert K. Brayton and
Giovanni De Micheli},
title = {A Simulation-Guided Paradigm for Logic Synthesis and Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {8},
pages = {2573--2586},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3108704},
doi = {10.1109/TCAD.2021.3108704},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeRMBM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/RienerLMM22,
author = {Heinz Riener and
Siang{-}Yun Lee and
Alan Mishchenko and
Giovanni De Micheli},
title = {Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets
Resynthesis},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {395--402},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712526},
doi = {10.1109/ASP-DAC52403.2022.9712526},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/RienerLMM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/NetoAPVLMG22,
author = {Walter Lau Neto and
Luca G. Amar{\`{u}} and
Vinicius Possani and
Patrick Vuillod and
Jiong Luo and
Alan Mishchenko and
Pierre{-}Emmanuel Gaillardon},
editor = {Rob Oshana},
title = {Improving LUT-based optimization for ASICs},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {421--426},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530461},
doi = {10.1145/3489517.3530461},
timestamp = {Thu, 25 Aug 2022 14:23:32 +0200},
biburl = {https://dblp.org/rec/conf/dac/NetoAPVLMG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarakkalageTRMS21,
author = {Dewmini Sudara Marakkalage and
Eleonora Testa and
Heinz Riener and
Alan Mishchenko and
Mathias Soeken and
Giovanni De Micheli},
title = {Three-Input Gates for Logic Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {10},
pages = {2184--2188},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3032625},
doi = {10.1109/TCAD.2020.3032625},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarakkalageTRMS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AmaruPTMCLVMM21,
author = {Luca Gaetano Amar{\`{u}} and
Vinicius N. Possani and
Eleonora Testa and
Felipe S. Marranghello and
Christopher Casares and
Jiong Luo and
Patrick Vuillod and
Alan Mishchenko and
Giovanni De Micheli},
title = {LUT-Based Optimization For {ASIC} Design Flow},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {871--876},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586132},
doi = {10.1109/DAC18074.2021.9586132},
timestamp = {Sun, 14 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AmaruPTMCLVMM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhangJAMB21,
author = {He{-}Teng Zhang and
Jie{-}Hong R. Jiang and
Luca G. Amar{\`{u}} and
Alan Mishchenko and
Robert K. Brayton},
title = {Deep Integration of Circuit Simulator and {SAT} Solver},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {877--882},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586331},
doi = {10.1109/DAC18074.2021.9586331},
timestamp = {Fri, 24 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhangJAMB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RaiNMZYYFMPRABC21,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1026--1031},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9473972},
doi = {10.23919/DATE51398.2021.9473972},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RaiNMZYYFMPRABC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhangJM21,
author = {He{-}Teng Zhang and
Jie{-}Hong R. Jiang and
Alan Mishchenko},
title = {A Circuit-Based {SAT} Solver for Logic Synthesis},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643505},
doi = {10.1109/ICCAD51958.2021.9643505},
timestamp = {Tue, 28 Dec 2021 12:29:05 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhangJM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/TestaASMVGM20,
author = {Eleonora Testa and
Luca G. Amar{\`{u}} and
Mathias Soeken and
Alan Mishchenko and
Patrick Vuillod and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli},
title = {Extending Boolean Methods for Scalable Logic Synthesis},
journal = {{IEEE} Access},
volume = {8},
pages = {226828--226844},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3045014},
doi = {10.1109/ACCESS.2020.3045014},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/TestaASMVGM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ZhouWM20,
author = {Xuegong Zhou and
Lingli Wang and
Alan Mishchenko},
title = {Fast Exact {NPN} Classification by Co-Designing Canonical Form and
Its Computation Algorithm},
journal = {{IEEE} Trans. Computers},
volume = {69},
number = {9},
pages = {1293--1307},
year = {2020},
url = {https://doi.org/10.1109/TC.2020.2971466},
doi = {10.1109/TC.2020.2971466},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ZhouWM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HaaswijkSMM20,
author = {Winston Haaswijk and
Mathias Soeken and
Alan Mishchenko and
Giovanni De Micheli},
title = {SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {4},
pages = {871--884},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2897703},
doi = {10.1109/TCAD.2019.2897703},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HaaswijkSMM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PossaniMRR20,
author = {Vinicius N. Possani and
Alan Mishchenko and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Parallel Combinational Equivalence Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {10},
pages = {3081--3092},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2946254},
doi = {10.1109/TCAD.2019.2946254},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PossaniMRR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AmaruMTCPLVMM20,
author = {Luca G. Amar{\`{u}} and
Felipe S. Marranghello and
Eleonora Testa and
Christopher Casares and
Vinicius N. Possani and
Jiong Luo and
Patrick Vuillod and
Alan Mishchenko and
Giovanni De Micheli},
title = {SAT-Sweeping Enhanced for Logic Synthesis},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218691},
doi = {10.1109/DAC18072.2020.9218691},
timestamp = {Thu, 15 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/AmaruMTCPLVMM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MengQM20,
author = {Chang Meng and
Weikang Qian and
Alan Mishchenko},
title = {{ALSRAC:} Approximate Logic Synthesis by Resubstitution with Approximate
Care Set},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218627},
doi = {10.1109/DAC18072.2020.9218627},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MengQM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RienerMS20,
author = {Heinz Riener and
Alan Mishchenko and
Mathias Soeken},
title = {Exact DAG-Aware Rewriting},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {732--737},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116379},
doi = {10.23919/DATE48585.2020.9116379},
timestamp = {Thu, 25 Jun 2020 12:55:44 +0200},
biburl = {https://dblp.org/rec/conf/date/RienerMS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icml/ChatterjeeM20,
author = {Satrajit Chatterjee and
Alan Mishchenko},
title = {Circuit-Based Intrinsic Methods to Detect Overfitting},
booktitle = {Proceedings of the 37th International Conference on Machine Learning,
{ICML} 2020, 13-18 July 2020, Virtual Event},
series = {Proceedings of Machine Learning Research},
volume = {119},
pages = {1459--1468},
publisher = {{PMLR}},
year = {2020},
url = {http://proceedings.mlr.press/v119/chatterjee20a.html},
timestamp = {Tue, 15 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icml/ChatterjeeM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Mishchenko20,
author = {Alan Mishchenko},
title = {Keynote {III:} Boolean Logic Networks for Machine Learning},
booktitle = {50th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2020, Miyazaki, Japan, November 9-11, 2020},
pages = {xx},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISMVL49045.2020.00-40},
doi = {10.1109/ISMVL49045.2020.00-40},
timestamp = {Fri, 15 Jan 2021 12:47:14 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Mishchenko20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MiyasakaFMW20,
author = {Yukio Miyasaka and
Masahiro Fujita and
Alan Mishchenko and
John Wawrzynek},
editor = {Andrea Calimera and
Pierre{-}Emmanuel Gaillardon and
Kunal Korgaonkar and
Shahar Kvatinsky and
Ricardo Reis},
title = {SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable
Arrays},
booktitle = {VLSI-SoC: Design Trends - 28th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake
City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {621},
pages = {113--131},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-81641-4\_6},
doi = {10.1007/978-3-030-81641-4\_6},
timestamp = {Wed, 28 Jul 2021 16:16:21 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MiyasakaFMW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2007-02579,
author = {Siang{-}Yun Lee and
Heinz Riener and
Alan Mishchenko and
Robert K. Brayton and
Giovanni De Micheli},
title = {Simulation-Guided Boolean Resubstitution},
journal = {CoRR},
volume = {abs/2007.02579},
year = {2020},
url = {https://arxiv.org/abs/2007.02579},
eprinttype = {arXiv},
eprint = {2007.02579},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2007-02579.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2012-02530,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa Jr. and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
journal = {CoRR},
volume = {abs/2012.02530},
year = {2020},
url = {https://arxiv.org/abs/2012.02530},
eprinttype = {arXiv},
eprint = {2012.02530},
timestamp = {Thu, 24 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2012-02530.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NeutzlingMMRR19,
author = {Augusto Neutzling and
Jody Maick Matos and
Alan Mishchenko and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Effective Logic Synthesis for Threshold Logic Circuit Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {5},
pages = {926--937},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2834434},
doi = {10.1109/TCAD.2018.2834434},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NeutzlingMMRR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhouWM19,
author = {Xuegong Zhou and
Lingli Wang and
Alan Mishchenko},
title = {Fast Adjustable {NPN} Classification Using Generalized Symmetries},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
pages = {7:1--7:16},
year = {2019},
url = {https://doi.org/10.1145/3313917},
doi = {10.1145/3313917},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ZhouWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/RienerTHMAMS19,
author = {Heinz Riener and
Eleonora Testa and
Winston Haaswijk and
Alan Mishchenko and
Luca G. Amar{\`{u}} and
Giovanni De Micheli and
Mathias Soeken},
title = {Scalable Generic Logic Synthesis: One Approach to Rule Them All},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {70},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317905},
doi = {10.1145/3316781.3317905},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/RienerTHMAMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TestaASMVLCGM19,
author = {Eleonora Testa and
Luca G. Amar{\`{u}} and
Mathias Soeken and
Alan Mishchenko and
Patrick Vuillod and
Jiong Luo and
Christopher Casares and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Scalable Boolean Methods in a Modern Synthesis Flow},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {1643--1648},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714776},
doi = {10.23919/DATE.2019.8714776},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/TestaASMVLCGM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RienerHMMS19,
author = {Heinz Riener and
Winston Haaswijk and
Alan Mishchenko and
Giovanni De Micheli and
Mathias Soeken},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {1649--1654},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715185},
doi = {10.23919/DATE.2019.8715185},
timestamp = {Mon, 20 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/RienerHMMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SchmittSMM19,
author = {Bruno Schmitt and
Mathias Soeken and
Giovanni De Micheli and
Alan Mishchenko},
title = {Scaling-up {ESOP} Synthesis for Quantum Compilation},
booktitle = {2019 {IEEE} 49th International Symposium on Multiple-Valued Logic
(ISMVL), Fredericton, NB, Canada, May 21-23, 2019},
pages = {13--18},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISMVL.2019.00011},
doi = {10.1109/ISMVL.2019.00011},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/SchmittSMM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/RienerTHMAMS19,
author = {Heinz Riener and
Eleonora Testa and
Winston Haaswijk and
Alan Mishchenko and
Luca G. Amar{\`{u}} and
Giovanni De Micheli and
Mathias Soeken},
title = {Logic Optimization of Majority-Inverter Graphs},
booktitle = {22nd Workshop Methods and Description Languages for Modelling and
Verification of Circuits and Systems, {MBMV} 2019, Kaiserslautern,
Germany, March 8-9, 2019},
pages = {1--4},
publisher = {{VDE} Verlag},
year = {2019},
url = {https://ieeexplore.ieee.org/document/8727159/},
timestamp = {Thu, 11 Jul 2019 17:44:24 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/RienerTHMAMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/BerndtMBR19,
author = {Augusto Andre Souza Berndt and
Alan Mishchenko and
Paulo Francisco Butzen and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Jo{\~{a}}o Antonio Martino and
Marcelo Lubaszewski and
Matteo Sonza Reorda},
title = {Reduction of neural network circuits by constant and nearly constant
signal propagation},
booktitle = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},
pages = {29},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3338852.3339874},
doi = {10.1145/3338852.3339874},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/BerndtMBR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1907-01991,
author = {Satrajit Chatterjee and
Alan Mishchenko},
title = {Circuit-Based Intrinsic Methods to Detect Overfitting},
journal = {CoRR},
volume = {abs/1907.01991},
year = {2019},
url = {http://arxiv.org/abs/1907.01991},
eprinttype = {arXiv},
eprint = {1907.01991},
timestamp = {Mon, 08 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1907-01991.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipl/SoekenTMM18,
author = {Mathias Soeken and
Eleonora Testa and
Alan Mishchenko and
Giovanni De Micheli},
title = {Pairs of majority-decomposing functions},
journal = {Inf. Process. Lett.},
volume = {139},
pages = {35--38},
year = {2018},
url = {https://doi.org/10.1016/j.ipl.2018.07.004},
doi = {10.1016/J.IPL.2018.07.004},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipl/SoekenTMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuCM18,
author = {Cunxi Yu and
Maciej J. Ciesielski and
Alan Mishchenko},
title = {Fast Algebraic Rewriting Based on And-Inverter Graphs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1907--1911},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772854},
doi = {10.1109/TCAD.2017.2772854},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaoLM18,
author = {Ai Quoc Dao and
Mark Po{-}Hung Lin and
Alan Mishchenko},
title = {SAT-Based Fault Equivalence Checking in Functional Safety Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3198--3205},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2791465},
doi = {10.1109/TCAD.2018.2791465},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaoLM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SchmittMB18,
author = {Bruno de O. Schmitt and
Alan Mishchenko and
Robert K. Brayton},
editor = {Youngsoo Shin},
title = {SAT-based area recovery in structural technology mapping},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {586--591},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297386},
doi = {10.1109/ASPDAC.2018.8297386},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SchmittMB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DaoLCLJMB18,
author = {Ai Quoc Dao and
Nian{-}Ze Lee and
Li{-}Cheng Chen and
Mark Po{-}Hung Lin and
Jie{-}Hong R. Jiang and
Alan Mishchenko and
Robert K. Brayton},
title = {Efficient computation of {ECO} patch functions},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {51:1--51:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196039},
doi = {10.1145/3195970.3196039},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DaoLCLJMB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishchenkoBPSAD18,
author = {Alan Mishchenko and
Robert K. Brayton and
Ana Petkovska and
Mathias Soeken and
Luca G. Amar{\`{u}} and
Antun Domic},
title = {Canonical computation without canonical representation},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {52:1--52:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196006},
doi = {10.1145/3195970.3196006},
timestamp = {Thu, 11 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MishchenkoBPSAD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HaaswijkMSM18,
author = {Winston Haaswijk and
Alan Mishchenko and
Mathias Soeken and
Giovanni De Micheli},
title = {{SAT} based exact synthesis using {DAG} topology families},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {53:1--53:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196111},
doi = {10.1145/3195970.3196111},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HaaswijkMSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SoekenHTMABM18,
author = {Mathias Soeken and
Winston Haaswijk and
Eleonora Testa and
Alan Mishchenko and
Luca Gaetano Amar{\`{u}} and
Robert K. Brayton and
Giovanni De Micheli},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Practical exact synthesis},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {309--314},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342027},
doi = {10.23919/DATE.2018.8342027},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SoekenHTMABM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AmaruSVLMOBM18,
author = {Luca Gaetano Amar{\`{u}} and
Mathias Soeken and
Patrick Vuillod and
Jiong Luo and
Alan Mishchenko and
Janet Olson and
Robert K. Brayton and
Giovanni De Micheli},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Improvements to boolean resynthesis},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {755--760},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342108},
doi = {10.23919/DATE.2018.8342108},
timestamp = {Tue, 24 Apr 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/AmaruSVLMOBM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FengGM18,
author = {Wenyi Feng and
Jonathan W. Greene and
Alan Mishchenko},
editor = {Jason Helge Anderson and
Kia Bazargan},
title = {Improving {FPGA} Performance with a {S44} {LUT} Structure},
booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
pages = {61--66},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3174243.3174272},
doi = {10.1145/3174243.3174272},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FengGM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZhouWZM18,
author = {Xuegong Zhou and
Lingli Wang and
Peiyi Zhao and
Alan Mishchenko},
title = {Fast Adjustable {NPN} Classification using Generalized Symmetries},
booktitle = {28th International Conference on Field Programmable Logic and Applications,
{FPL} 2018, Dublin, Ireland, August 27-31, 2018},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FPL.2018.00008},
doi = {10.1109/FPL.2018.00008},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/ZhouWZM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PossaniLMPRR18,
author = {Vinicius N. Possani and
Yi{-}Shan Lu and
Alan Mishchenko and
Keshav Pingali and
Renato P. Ribas and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Iris Bahar},
title = {Unlocking fine-grain parallelism for {AIG} rewriting},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {87},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240861},
doi = {10.1145/3240765.3240861},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/iccad/PossaniLMPRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lpar/YuYSMC18,
author = {Cunxi Yu and
Atif Yasin and
Tiankai Su and
Alan Mishchenko and
Maciej J. Ciesielski},
editor = {Gilles Barthe and
Geoff Sutcliffe and
Margus Veanes},
title = {Rewriting Environment for Arithmetic Circuit Verification},
booktitle = {{LPAR-22.} 22nd International Conference on Logic for Programming,
Artificial Intelligence and Reasoning, Awassa, Ethiopia, 16-21 November
2018},
series = {EPiC Series in Computing},
volume = {57},
pages = {656--666},
publisher = {EasyChair},
year = {2018},
url = {https://doi.org/10.29007/rswk},
doi = {10.29007/RSWK},
timestamp = {Sun, 15 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lpar/YuYSMC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/18/PetkovskaMNOI18,
author = {Ana Petkovska and
Alan Mishchenko and
David Novo and
Muhsen Owaida and
Paolo Ienne},
editor = {Andr{\'{e}} In{\'{a}}cio Reis and
Rolf Drechsler},
title = {Progressive Generation of Canonical Irredundant Sums of Products Using
a {SAT} Solver},
booktitle = {Advanced Logic Synthesis},
pages = {169--188},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-67295-3\_8},
doi = {10.1007/978-3-319-67295-3\_8},
timestamp = {Mon, 16 Sep 2019 14:43:19 +0200},
biburl = {https://dblp.org/rec/books/sp/18/PetkovskaMNOI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/CabodiCMPP17,
author = {Gianpiero Cabodi and
Paolo Camurati and
Alan Mishchenko and
Marco Palena and
Paolo Pasini},
title = {{SAT} solver management strategies in {IC3:} an experimental approach},
journal = {Formal Methods Syst. Des.},
volume = {50},
number = {1},
pages = {39--74},
year = {2017},
url = {https://doi.org/10.1007/s10703-017-0272-0},
doi = {10.1007/S10703-017-0272-0},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fmsd/CabodiCMPP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AdnanYM17,
author = {Nurul Ain Binti Adnan and
Shigeru Yamashita and
Alan Mishchenko},
title = {Reduction of Quantum Cost by Making Temporary Changes to the Function},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {7},
pages = {1393--1402},
year = {2017},
url = {https://doi.org/10.1587/transinf.2016EDP7397},
doi = {10.1587/TRANSINF.2016EDP7397},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AdnanYM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SchmittMKBR17,
author = {Bruno de O. Schmitt and
Alan Mishchenko and
Victor N. Kravets and
Robert K. Brayton and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Fast-extract with cube hashing},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {145--150},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858311},
doi = {10.1109/ASPDAC.2017.7858311},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SchmittMKBR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SoekenMM17,
author = {Mathias Soeken and
Giovanni De Micheli and
Alan Mishchenko},
editor = {David Atienza and
Giorgio Di Natale},
title = {Busy man's synthesis: Combinational delay optimization with {SAT}},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {830--835},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927103},
doi = {10.23919/DATE.2017.7927103},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SoekenMM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/HoMB17,
author = {Yen{-}Sheng Ho and
Alan Mishchenko and
Robert K. Brayton},
editor = {Daryl Stewart and
Georg Weissenbacher},
title = {Property directed reachability with word-level abstraction},
booktitle = {2017 Formal Methods in Computer Aided Design, {FMCAD} 2017, Vienna,
Austria, October 2-6, 2017},
pages = {132--139},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/FMCAD.2017.8102251},
doi = {10.23919/FMCAD.2017.8102251},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/HoMB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AmaruSVLMGOBM17,
author = {Luca Gaetano Amar{\`{u}} and
Mathias Soeken and
Patrick Vuillod and
Jiong Luo and
Alan Mishchenko and
Pierre{-}Emmanuel Gaillardon and
Janet Olson and
Robert K. Brayton and
Giovanni De Micheli},
editor = {Sri Parameswaran},
title = {Enabling exact delay synthesis},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {352--359},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203799},
doi = {10.1109/ICCAD.2017.8203799},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/AmaruSVLMGOBM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SavojMB16,
author = {Hamid Savoj and
Alan Mishchenko and
Robert K. Brayton},
title = {m-Inductive Property of Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {6},
pages = {919--930},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2481860},
doi = {10.1109/TCAD.2015.2481860},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SavojMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aaai/BalabanovJMS16,
author = {Valeriy Balabanov and
Jie{-}Hong Roland Jiang and
Alan Mishchenko and
Christoph Scholl},
editor = {Adnan Darwiche},
title = {Clauses Versus Gates in CEGAR-Based 2QBF Solving},
booktitle = {Beyond NP, Papers from the 2016 {AAAI} Workshop, Phoenix, Arizona,
USA, February 12, 2016},
series = {{AAAI} Technical Report},
volume = {{WS-16-05}},
publisher = {{AAAI} Press},
year = {2016},
url = {http://www.aaai.org/ocs/index.php/WS/AAAIW16/paper/view/12660},
timestamp = {Tue, 05 Sep 2023 08:59:27 +0200},
biburl = {https://dblp.org/rec/conf/aaai/BalabanovJMS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/HoCRMB16,
author = {Yen{-}Sheng Ho and
Pankaj Chauhan and
Pritam Roy and
Alan Mishchenko and
Robert K. Brayton},
editor = {Ruzica Piskac and
Muralidhar Talupur},
title = {Efficient uninterpreted function abstraction and refinement for word-level
model checking},
booktitle = {2016 Formal Methods in Computer-Aided Design, {FMCAD} 2016, Mountain
View, CA, USA, October 3-6, 2016},
pages = {65--72},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FMCAD.2016.7886662},
doi = {10.1109/FMCAD.2016.7886662},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/HoCRMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/PetkovskaSMIM16,
author = {Ana Petkovska and
Mathias Soeken and
Giovanni De Micheli and
Paolo Ienne and
Alan Mishchenko},
editor = {Paolo Ienne and
Walid A. Najjar and
Jason Helge Anderson and
Philip Brisk and
Walter Stechele},
title = {Fast hierarchical {NPN} classification},
booktitle = {26th International Conference on Field Programmable Logic and Applications,
{FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPL.2016.7577306},
doi = {10.1109/FPL.2016.7577306},
timestamp = {Fri, 17 Jan 2020 17:11:15 +0100},
biburl = {https://dblp.org/rec/conf/fpl/PetkovskaSMIM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PetkovskaMSMBI16,
author = {Ana Petkovska and
Alan Mishchenko and
Mathias Soeken and
Giovanni De Micheli and
Robert K. Brayton and
Paolo Ienne},
editor = {Frank Liu},
title = {Fast generation of lexicographic satisfiable assignments: enabling
canonicity in SAT-based applications},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {4},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967040},
doi = {10.1145/2966986.2967040},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/PetkovskaMSMBI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sat/SoekenMPSIBM16,
author = {Mathias Soeken and
Alan Mishchenko and
Ana Petkovska and
Baruch Sterin and
Paolo Ienne and
Robert K. Brayton and
Giovanni De Micheli},
editor = {Nadia Creignou and
Daniel Le Berre},
title = {Heuristic {NPN} Classification for Large Functions Using AIGs and
{LEXSAT}},
booktitle = {Theory and Applications of Satisfiability Testing - {SAT} 2016 - 19th
International Conference, Bordeaux, France, July 5-8, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9710},
pages = {212--227},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-40970-2\_14},
doi = {10.1007/978-3-319-40970-2\_14},
timestamp = {Tue, 14 May 2019 10:00:41 +0200},
biburl = {https://dblp.org/rec/conf/sat/SoekenMPSIBM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sat/BalabanovJSMB16,
author = {Valeriy Balabanov and
Jie{-}Hong Roland Jiang and
Christoph Scholl and
Alan Mishchenko and
Robert K. Brayton},
editor = {Nadia Creignou and
Daniel Le Berre},
title = {2QBF: Challenges and Solutions},
booktitle = {Theory and Applications of Satisfiability Testing - {SAT} 2016 - 19th
International Conference, Bordeaux, France, July 5-8, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9710},
pages = {453--469},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-40970-2\_28},
doi = {10.1007/978-3-319-40970-2\_28},
timestamp = {Wed, 03 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sat/BalabanovJSMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/VillaPYMB15,
author = {Tiziano Villa and
Alexandre Petrenko and
Nina Yevtushenko and
Alan Mishchenko and
Robert K. Brayton},
title = {Component-Based Design by Solving Language Equations},
journal = {Proc. {IEEE}},
volume = {103},
number = {11},
pages = {2152--2167},
year = {2015},
url = {https://doi.org/10.1109/JPROC.2015.2450937},
doi = {10.1109/JPROC.2015.2450937},
timestamp = {Tue, 15 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pieee/VillaPYMB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MishchenkoBFG15,
author = {Alan Mishchenko and
Robert K. Brayton and
Wenyi Feng and
Jonathan W. Greene},
editor = {George A. Constantinides and
Deming Chen},
title = {Technology Mapping into General Programmable Cells},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {70--73},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689082},
doi = {10.1145/2684746.2689082},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MishchenkoBFG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/PetkovskaZNOMI15,
author = {Ana Petkovska and
Grace Zgheib and
David Novo and
Muhsen Owaida and
Alan Mishchenko and
Paolo Ienne},
title = {Improved carry chain mapping for the {VTR} flow},
booktitle = {2015 International Conference on Field Programmable Technology, {FPT}
2015, Queenstown, New Zealand, December 7-9, 2015},
pages = {80--87},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPT.2015.7393133},
doi = {10.1109/FPT.2015.7393133},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/PetkovskaZNOMI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NeutzlingMRRM15,
author = {Augusto Neutzling and
Jody Maick Matos and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas and
Alan Mishchenko},
editor = {Diana Marculescu and
Frank Liu},
title = {Threshold Logic Synthesis Based on Cut Pruning},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {494--499},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372610},
doi = {10.1109/ICCAD.2015.7372610},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/NeutzlingMRRM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/FujitaTIM15,
author = {Masahiro Fujita and
Naoki Taguchi and
Kentaro Iwata and
Alan Mishchenko},
title = {Incremental {ATPG} methods for multiple faults under multiple fault
models},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {177--180},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085420},
doi = {10.1109/ISQED.2015.7085420},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/FujitaTIM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AmaruGMCM15,
author = {Luca Gaetano Amar{\`{u}} and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Maciej J. Ciesielski and
Giovanni De Micheli},
title = {Exploiting Circuit Duality to Speed up {SAT}},
booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
Montpellier, France, July 8-10, 2015},
pages = {101--106},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVLSI.2015.18},
doi = {10.1109/ISVLSI.2015.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AmaruGMCM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sefm/CastagnettiPVYB15,
author = {Giovanni Castagnetti and
Matteo Piccolo and
Tiziano Villa and
Nina Yevtushenko and
Robert K. Brayton and
Alan Mishchenko},
editor = {Domenico Bianculli and
Radu Calinescu and
Bernhard Rumpe},
title = {Automated Synthesis of Protocol Converters with {BALM-II}},
booktitle = {Software Engineering and Formal Methods - {SEFM} 2015 Collocated Workshops:
ATSE, HOFM, MoKMaSD, and VERY*SCART, York, UK, September 7-8, 2015,
Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {9509},
pages = {281--296},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-662-49224-6\_23},
doi = {10.1007/978-3-662-49224-6\_23},
timestamp = {Tue, 15 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sefm/CastagnettiPVYB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SavojMB14,
author = {Hamid Savoj and
Alan Mishchenko and
Robert K. Brayton},
title = {Sequential Equivalence Checking for Clock-Gated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {305--317},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284190},
doi = {10.1109/TCAD.2013.2284190},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SavojMB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KarthikRNMBR14,
author = {Aadithya V. Karthik and
Sayak Ray and
Pierluigi Nuzzo and
Alan Mishchenko and
Robert K. Brayton and
Jaijeet Roychowdhury},
title = {{ABCD-NL:} Approximating Continuous non-linear dynamical systems using
purely Boolean models for analog/mixed-signal verification},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {250--255},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742898},
doi = {10.1109/ASPDAC.2014.6742898},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KarthikRNMBR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bcb/KarthikSRSMBR14,
author = {Aadithya V. Karthik and
David Soloveichik and
Sayak Ray and
Baruch Sterin and
Alan Mishchenko and
Robert K. Brayton and
Jaijeet Roychowdhury},
editor = {Pierre Baldi and
Wei Wang},
title = {{NINJA:} boolean modelling and formal verification of tiered-rate
chemical reaction networks (extended abstract)},
booktitle = {Proceedings of the 5th {ACM} Conference on Bioinformatics, Computational
Biology, and Health Informatics, {BCB} '14, Newport Beach, California,
USA, September 20-23, 2014},
pages = {623--624},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2649387.2660805},
doi = {10.1145/2649387.2660805},
timestamp = {Tue, 06 Nov 2018 16:59:10 +0100},
biburl = {https://dblp.org/rec/conf/bcb/KarthikSRSMBR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PetkovskaNMI14,
author = {Ana Petkovska and
David Novo and
Alan Mishchenko and
Paolo Ienne},
editor = {Yao{-}Wen Chang},
title = {Constrained interpolation for guided logic synthesis},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {462--469},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001392},
doi = {10.1109/ICCAD.2014.7001392},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/PetkovskaNMI14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/FujitaM14,
author = {Masahiro Fujita and
Alan Mishchenko},
title = {Efficient SAT-based {ATPG} techniques for all multiple stuck-at faults},
booktitle = {2014 International Test Conference, {ITC} 2014, Seattle, WA, USA,
October 20-23, 2014},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/TEST.2014.7035351},
doi = {10.1109/TEST.2014.7035351},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/FujitaM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FujitaM14,
author = {Masahiro Fujita and
Alan Mishchenko},
editor = {Lorena Garcia},
title = {Logic synthesis and verification on fixed topology},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004155},
doi = {10.1109/VLSI-SOC.2014.7004155},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FujitaM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MishchenkoEBCCS13,
author = {Alan Mishchenko and
Niklas E{\'{e}}n and
Robert K. Brayton and
Michael L. Case and
Pankaj Chauhan and
Nikhil Sharma},
editor = {Enrico Macii},
title = {A semi-canonical form for sequential AIGs},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {797--802},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.169},
doi = {10.7873/DATE.2013.169},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/MishchenkoEBCCS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MishchenkoEBBMN13,
author = {Alan Mishchenko and
Niklas E{\'{e}}n and
Robert K. Brayton and
Jason Baumgartner and
Hari Mony and
Pradeep Kumar Nalla},
editor = {Enrico Macii},
title = {{GLA:} gate-level abstraction revisited},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1399--1404},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.286},
doi = {10.7873/DATE.2013.286},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MishchenkoEBBMN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Belov0MM13,
author = {Anton Belov and
Huan Chen and
Alan Mishchenko and
Jo{\~{a}}o Marques{-}Silva},
editor = {Enrico Macii},
title = {Core minimization in SAT-based abstraction},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1411--1416},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.288},
doi = {10.7873/DATE.2013.288},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/Belov0MM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/EenM13,
author = {Niklas E{\'{e}}n and
Alan Mishchenko},
editor = {Malay K. Ganai and
Alper Sen},
title = {A Fast Reparameterization Procedure},
booktitle = {Proceedings of the Second International Workshop on Design and Implementation
of Formal Tools and Systems, Portland, OR, USA, October 19, 2013},
series = {{CEUR} Workshop Proceedings},
volume = {1130},
publisher = {CEUR-WS.org},
year = {2013},
url = {https://ceur-ws.org/Vol-1130/paper\_1.pdf},
timestamp = {Fri, 10 Mar 2023 16:22:13 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/EenM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/PalenaCM13,
author = {Marco Palena and
Gianpiero Cabodi and
Alan Mishchenko},
editor = {Malay K. Ganai and
Alper Sen},
title = {Trading-off Incrementality and Dynamic Restart of Multiple Solvers
in {IC3}},
booktitle = {Proceedings of the Second International Workshop on Design and Implementation
of Formal Tools and Systems, Portland, OR, USA, October 19, 2013},
series = {{CEUR} Workshop Proceedings},
volume = {1130},
publisher = {CEUR-WS.org},
year = {2013},
url = {https://ceur-ws.org/Vol-1130/paper\_5.pdf},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/PalenaCM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HuangWNM13,
author = {Zheng Huang and
Lingli Wang and
Yakov Nasikovskiy and
Alan Mishchenko},
title = {Fast Boolean matching based on {NPN} classification},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {310--313},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718374},
doi = {10.1109/FPT.2013.6718374},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/HuangWNM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RayMEBJC12,
author = {Sayak Ray and
Alan Mishchenko and
Niklas E{\'{e}}n and
Robert K. Brayton and
Stephen Jang and
Chao Chen},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Mapping into {LUT} structures},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {1579--1584},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176724},
doi = {10.1109/DATE.2012.6176724},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RayMEBJC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangWM12,
author = {Wenlong Yang and
Lingli Wang and
Alan Mishchenko},
editor = {Alan J. Hu},
title = {Lazy man's logic synthesis},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {597--604},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429513},
doi = {10.1145/2429384.2429513},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YangWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MishchenkoBJJ11,
author = {Alan Mishchenko and
Robert K. Brayton and
Jie{-}Hong R. Jiang and
Stephen Jang},
title = {Scalable don't-care-based logic optimization and resynthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {34:1--34:23},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068720},
doi = {10.1145/2068716.2068720},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MishchenkoBJJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/EenMB11,
author = {Niklas E{\'{e}}n and
Alan Mishchenko and
Robert K. Brayton},
editor = {Per Bjesse and
Anna Slobodov{\'{a}}},
title = {Efficient implementation of property directed reachability},
booktitle = {International Conference on Formal Methods in Computer-Aided Design,
{FMCAD} '11, Austin, TX, USA, October 30 - November 02, 2011},
pages = {125--134},
publisher = {{FMCAD} Inc.},
year = {2011},
url = {http://dl.acm.org/citation.cfm?id=2157675},
timestamp = {Mon, 09 Aug 2021 15:21:44 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/EenMB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/LongRSMB11,
author = {Jiang Long and
Sayak Ray and
Baruch Sterin and
Alan Mishchenko and
Robert K. Brayton},
editor = {Malay K. Ganai and
Armin Biere},
title = {Enhancing {ABC} for stabilization verification of SystemVerilog/VHDL
models},
booktitle = {Proceedings of the First International Workshop on Design and Implementation
of Formal Tools and Systems, Austin, USA, November 3, 2011},
series = {{CEUR} Workshop Proceedings},
volume = {832},
publisher = {CEUR-WS.org},
year = {2011},
url = {https://ceur-ws.org/Vol-832/paper\_2.pdf},
timestamp = {Fri, 10 Mar 2023 16:22:13 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/LongRSMB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoBJK11,
author = {Alan Mishchenko and
Robert K. Brayton and
Stephen Jang and
Victor N. Kravets},
editor = {Joel R. Phillips and
Alan J. Hu and
Helmut Graeb},
title = {Delay optimization using {SOP} balancing},
booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2011, San Jose, California, USA, November 7-10, 2011},
pages = {375--382},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCAD.2011.6105357},
doi = {10.1109/ICCAD.2011.6105357},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoBJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/JiangLMH10,
author = {Jie{-}Hong Roland Jiang and
Chih{-}Chun Lee and
Alan Mishchenko and
Chung{-}Yang Huang},
title = {To {SAT} or Not to {SAT:} Scalable Exploration of Functional Dependency},
journal = {{IEEE} Trans. Computers},
volume = {59},
number = {4},
pages = {457--467},
year = {2010},
url = {https://doi.org/10.1109/TC.2010.12},
doi = {10.1109/TC.2010.12},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/JiangLMH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChangBMM10,
author = {Kai{-}Hui Chang and
Valeria Bertacco and
Igor L. Markov and
Alan Mishchenko},
title = {Logic synthesis and circuit customization using extensive external
don't-cares},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {15},
number = {3},
pages = {26:1--26:24},
year = {2010},
url = {https://doi.org/10.1145/1754405.1754411},
doi = {10.1145/1754405.1754411},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChangBMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cav/BraytonM10,
author = {Robert K. Brayton and
Alan Mishchenko},
editor = {Tayssir Touili and
Byron Cook and
Paul B. Jackson},
title = {{ABC:} An Academic Industrial-Strength Verification Tool},
booktitle = {Computer Aided Verification, 22nd International Conference, {CAV}
2010, Edinburgh, UK, July 15-19, 2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6174},
pages = {24--40},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-14295-6\_5},
doi = {10.1007/978-3-642-14295-6\_5},
timestamp = {Tue, 14 May 2019 10:00:43 +0200},
biburl = {https://dblp.org/rec/conf/cav/BraytonM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/StrukovM10,
author = {Dmitri B. Strukov and
Alan Mishchenko},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Monolithically stackable hybrid {FPGA}},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {661--666},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457117},
doi = {10.1109/DATE.2010.5457117},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/StrukovM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/SavojBMB10,
author = {Hamid Savoj and
David Berthelot and
Alan Mishchenko and
Robert K. Brayton},
editor = {Roderick Bloem and
Natasha Sharygina},
title = {Combinational techniques for sequential equivalence checking},
booktitle = {Proceedings of 10th International Conference on Formal Methods in
Computer-Aided Design, {FMCAD} 2010, Lugano, Switzerland, October
20-23},
pages = {145--149},
publisher = {{IEEE}},
year = {2010},
url = {https://ieeexplore.ieee.org/document/5770943/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/SavojBMB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/EenMA10,
author = {Niklas E{\'{e}}n and
Alan Mishchenko and
Nina Amla},
editor = {Roderick Bloem and
Natasha Sharygina},
title = {A single-instance incremental {SAT} formulation of proof- and counterexample-based
abstraction},
booktitle = {Proceedings of 10th International Conference on Formal Methods in
Computer-Aided Design, {FMCAD} 2010, Lugano, Switzerland, October
20-23},
pages = {181--188},
publisher = {{IEEE}},
year = {2010},
url = {https://ieeexplore.ieee.org/document/5770948/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/EenMA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MishchenkoBJ10,
author = {Alan Mishchenko and
Robert K. Brayton and
Stephen Jang},
editor = {Peter Y. K. Cheung and
John Wawrzynek},
title = {Global delay optimization using structural choices},
booktitle = {Proceedings of the {ACM/SIGDA} 18th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2010, Monterey, California, USA,
February 21-23, 2010},
pages = {181--184},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1723112.1723144},
doi = {10.1145/1723112.1723144},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MishchenkoBJ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KenningsMVPK10,
author = {Andrew A. Kennings and
Alan Mishchenko and
Kristofer Vorwerk and
Val Pevzner and
Arun Kundu},
title = {Efficient {FPGA} Resynthesis Using Precomputed {LUT} Structures},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2010, August 31 2010 - September 2, 2010, Milano, Italy},
pages = {532--537},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FPL.2010.105},
doi = {10.1109/FPL.2010.105},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KenningsMVPK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1008-2021,
author = {Niklas E{\'{e}}n and
Alan Mishchenko and
Nina Amla},
title = {A Single-Instance Incremental {SAT} Formulation of Proof- and Counterexample-Based
Abstraction},
journal = {CoRR},
volume = {abs/1008.2021},
year = {2010},
url = {http://arxiv.org/abs/1008.2021},
eprinttype = {arXiv},
eprint = {1008.2021},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1008-2021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JangCCM09,
author = {Stephen Jang and
Billy Chan and
Kevin Chung and
Alan Mishchenko},
title = {WireMap: {FPGA} Technology Mapping for Improved Routability and Enhanced
{LUT} Merging},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {14:1--14:24},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534924},
doi = {10.1145/1534916.1534924},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JangCCM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KravetsM09,
author = {Victor N. Kravets and
Alan Mishchenko},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Sequential logic synthesis using symbolic bi-decomposition},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1458--1463},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090893},
doi = {10.1109/DATE.2009.5090893},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/KravetsM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MonyBMB09,
author = {Hari Mony and
Jason Baumgartner and
Alan Mishchenko and
Robert K. Brayton},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Speculative reduction-based scalable redundancy identification},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1674--1679},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090932},
doi = {10.1109/DATE.2009.5090932},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MonyBMB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MishchenkoBJJ09,
author = {Alan Mishchenko and
Robert K. Brayton and
Jie{-}Hong Roland Jiang and
Stephen Jang},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Scalable don't-care-based logic optimization and resynthesis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {151--160},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508152},
doi = {10.1145/1508128.1508152},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MishchenkoBJJ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JangWJCCMB09,
author = {Stephen Jang and
Dennis Wu and
Mark Jarvin and
Billy Chan and
Kevin Chung and
Alan Mishchenko and
Robert K. Brayton},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {SmartOpt: an industrial strength framework for logic synthesis},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {237--240},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508165},
doi = {10.1145/1508128.1508165},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JangWJCCMB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HurstMB08,
author = {Aaron P. Hurst and
Alan Mishchenko and
Robert K. Brayton},
editor = {Limor Fix},
title = {Scalable min-register retiming under timing and initializability constraints},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {534--539},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391604},
doi = {10.1145/1391469.1391604},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HurstMB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CaseKMB08,
author = {Michael L. Case and
Victor N. Kravets and
Alan Mishchenko and
Robert K. Brayton},
editor = {Limor Fix},
title = {Merging nodes under sequential observability},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {540--545},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391605},
doi = {10.1145/1391469.1391605},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CaseKMB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/CaseMBBM08,
author = {Michael L. Case and
Alan Mishchenko and
Robert K. Brayton and
Jason Baumgartner and
Hari Mony},
editor = {Alessandro Cimatti and
Robert B. Jones},
title = {Invariant-Strengthened Elimination of Dependent State Elements},
booktitle = {Formal Methods in Computer-Aided Design, {FMCAD} 2008, Portland, Oregon,
USA, 17-20 November 2008},
pages = {1--9},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FMCAD.2008.ECP.6},
doi = {10.1109/FMCAD.2008.ECP.6},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/CaseMBBM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/MishchenkoB08,
author = {Alan Mishchenko and
Robert K. Brayton},
editor = {Alessandro Cimatti and
Robert B. Jones},
title = {Recording Synthesis History for Sequential Verification},
booktitle = {Formal Methods in Computer-Aided Design, {FMCAD} 2008, Portland, Oregon,
USA, 17-20 November 2008},
pages = {1--8},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FMCAD.2008.ECP.8},
doi = {10.1109/FMCAD.2008.ECP.8},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/MishchenkoB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JangCCM08,
author = {Stephen Jang and
Billy Chan and
Kevin Chung and
Alan Mishchenko},
editor = {Mike Hutton and
Paul Chow},
title = {WireMap: {FPGA} technology mapping for improved routability},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {47--55},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344680},
doi = {10.1145/1344671.1344680},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JangCCM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoBC08,
author = {Alan Mishchenko and
Robert K. Brayton and
Satrajit Chatterjee},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Boolean factoring and decomposition of logic networks},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {38--44},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681549},
doi = {10.1109/ICCAD.2008.4681549},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoBC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoCBJ08,
author = {Alan Mishchenko and
Michael L. Case and
Robert K. Brayton and
Stephen Jang},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Scalable and scalably-verifiable sequential synthesis},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {234--241},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681580},
doi = {10.1109/ICCAD.2008.4681580},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoCBJ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishchenkoCB07,
author = {Alan Mishchenko and
Satrajit Chatterjee and
Robert K. Brayton},
title = {Improvements to Technology Mapping for LUT-Based FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {240--253},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887925},
doi = {10.1109/TCAD.2006.887925},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishchenkoCB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChatterjeeMBK07,
author = {Satrajit Chatterjee and
Alan Mishchenko and
Robert K. Brayton and
Andreas Kuehlmann},
title = {On Resolution Proofs for Combinational Equivalence},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {600--605},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278631},
doi = {10.1145/1278480.1278631},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChatterjeeMBK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/CaseMB07,
author = {Michael L. Case and
Alan Mishchenko and
Robert K. Brayton},
title = {Automated Extraction of Inductive Invariants to Aid Model Checking},
booktitle = {Formal Methods in Computer-Aided Design, 7th International Conference,
{FMCAD} 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings},
pages = {165--172},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/FAMCAD.2007.12},
doi = {10.1109/FAMCAD.2007.12},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/CaseMB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/HurstMB07,
author = {Aaron P. Hurst and
Alan Mishchenko and
Robert K. Brayton},
title = {Fast Minimum-Register Retiming via Binary Maximum-Flow},
booktitle = {Formal Methods in Computer-Aided Design, 7th International Conference,
{FMCAD} 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings},
pages = {181--187},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/FAMCAD.2007.31},
doi = {10.1109/FAMCAD.2007.31},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/HurstMB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LeeJHM07,
author = {Chih{-}Chun Lee and
Jie{-}Hong Roland Jiang and
Chung{-}Yang Huang and
Alan Mishchenko},
editor = {Georges G. E. Gielen},
title = {Scalable exploration of functional dependency by interpolation and
incremental {SAT} solving},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {227--233},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397270},
doi = {10.1109/ICCAD.2007.4397270},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LeeJHM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoCCB07,
author = {Alan Mishchenko and
Sungmin Cho and
Satrajit Chatterjee and
Robert K. Brayton},
editor = {Georges G. E. Gielen},
title = {Combinational and sequential mapping with priority cuts},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {354--361},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397290},
doi = {10.1109/ICCAD.2007.4397290},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoCCB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sat/EenMS07,
author = {Niklas E{\'{e}}n and
Alan Mishchenko and
Niklas S{\"{o}}rensson},
editor = {Jo{\~{a}}o Marques{-}Silva and
Karem A. Sakallah},
title = {Applying Logic Synthesis for Speeding Up {SAT}},
booktitle = {Theory and Applications of Satisfiability Testing - {SAT} 2007, 10th
International Conference, Lisbon, Portugal, May 28-31, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4501},
pages = {272--286},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-72788-0\_26},
doi = {10.1007/978-3-540-72788-0\_26},
timestamp = {Mon, 24 Feb 2020 19:23:27 +0100},
biburl = {https://dblp.org/rec/conf/sat/EenMS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4695,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {SAT-Based Complete Don't-Care Computation for Network Optimization},
journal = {CoRR},
volume = {abs/0710.4695},
year = {2007},
url = {http://arxiv.org/abs/0710.4695},
eprinttype = {arXiv},
eprint = {0710.4695},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4695.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4743,
author = {Alan Mishchenko and
Robert K. Brayton and
Jie{-}Hong Roland Jiang and
Tiziano Villa and
Nina Yevtushenko},
title = {Efficient Solution of Language Equations Using Partitioned Representations},
journal = {CoRR},
volume = {abs/0710.4743},
year = {2007},
url = {http://arxiv.org/abs/0710.4743},
eprinttype = {arXiv},
eprint = {0710.4743},
timestamp = {Tue, 15 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4743.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishchenkoZSBBC06,
author = {Alan Mishchenko and
Jin S. Zhang and
Subarnarekha Sinha and
Jerry R. Burch and
Robert K. Brayton and
Malgorzata Chrzanowska{-}Jeske},
title = {Using simulation and satisfiability to compute flexibilities in Boolean
networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {743--755},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860955},
doi = {10.1109/TCAD.2005.860955},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishchenkoZSBBC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MishchenkoB06,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {A theory of nondeterministic networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {977--999},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855978},
doi = {10.1109/TCAD.2005.855978},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MishchenkoB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangCMB06,
author = {Jin S. Zhang and
Malgorzata Chrzanowska{-}Jeske and
Alan Mishchenko and
Jerry R. Burch},
title = {Linear cofactor relationships in Boolean functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1011--1023},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855951},
doi = {10.1109/TCAD.2005.855951},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangCMB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChatterjeeMBWK06,
author = {Satrajit Chatterjee and
Alan Mishchenko and
Robert K. Brayton and
Xinning Wang and
Timothy Kam},
title = {Reducing Structural Bias in Technology Mapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {12},
pages = {2894--2903},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.882484},
doi = {10.1109/TCAD.2006.882484},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChatterjeeMBWK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhangMBC06,
author = {Jin S. Zhang and
Alan Mishchenko and
Robert K. Brayton and
Malgorzata Chrzanowska{-}Jeske},
editor = {Ellen Sentovich},
title = {Symmetry detection for large Boolean functions using circuit representation,
simulation, and satisfiability},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {510--515},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147044},
doi = {10.1145/1146909.1147044},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhangMBC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishchenkoCB06,
author = {Alan Mishchenko and
Satrajit Chatterjee and
Robert K. Brayton},
editor = {Ellen Sentovich},
title = {DAG-aware {AIG} rewriting a fresh look at combinational logic synthesis},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {532--535},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147048},
doi = {10.1145/1146909.1147048},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishchenkoCB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MishchenkoCB06,
author = {Alan Mishchenko and
Satrajit Chatterjee and
Robert K. Brayton},
editor = {Steven J. E. Wilton and
Andr{\'{e}} DeHon},
title = {Improvements to technology mapping for LUT-based FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 14th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2006, Monterey, California, USA,
February 22-24, 2006},
pages = {41--49},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117201.1117208},
doi = {10.1145/1117201.1117208},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MishchenkoCB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChatterjeeMB06,
author = {Satrajit Chatterjee and
Alan Mishchenko and
Robert K. Brayton},
editor = {Soha Hassoun},
title = {Factor cuts},
booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006,
San Jose, CA, USA, November 5-9, 2006},
pages = {143--150},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1233501.1233531},
doi = {10.1145/1233501.1233531},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChatterjeeMB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoCBE06,
author = {Alan Mishchenko and
Satrajit Chatterjee and
Robert K. Brayton and
Niklas E{\'{e}}n},
editor = {Soha Hassoun},
title = {Improvements to combinational equivalence checking},
booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006,
San Jose, CA, USA, November 5-9, 2006},
pages = {836--843},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1233501.1233679},
doi = {10.1145/1233501.1233679},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoCBE06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/NagayamaMSB05,
author = {Shinobu Nagayama and
Alan Mishchenko and
Tsutomu Sasao and
Jon T. Butler},
title = {Exact and Heuristic Minimization of the Average Path Length in Decision
Diagrams},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {11},
number = {5-6},
pages = {437--465},
year = {2005},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-11-number-5-6-2005/mvlsc-11-5-6-p-437-465/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/NagayamaMSB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhangCMB05,
author = {Jin S. Zhang and
Malgorzata Chrzanowska{-}Jeske and
Alan Mishchenko and
Jerry R. Burch},
editor = {Tingao Tang},
title = {Detecting support-reducing bound sets using two-cofactor symmetries},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {266--271},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120846},
doi = {10.1145/1120725.1120846},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZhangCMB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MishchenkoB05,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {SAT-Based Complete Don't-Care Computation for Network Optimization},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {412--417},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.264},
doi = {10.1109/DATE.2005.264},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/MishchenkoB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MishchenkoBJVY05,
author = {Alan Mishchenko and
Robert K. Brayton and
Jie{-}Hong Roland Jiang and
Tiziano Villa and
Nina Yevtushenko},
title = {Efficient Solution of Language Equations Using Partitioned Representations},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {418--423},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.130},
doi = {10.1109/DATE.2005.130},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/MishchenkoBJVY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChatterjeeMBWK05,
author = {Satrajit Chatterjee and
Alan Mishchenko and
Robert K. Brayton and
Xinning Wang and
Timothy Kam},
title = {Reducing structural bias in technology mapping},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {519--526},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560122},
doi = {10.1109/ICCAD.2005.1560122},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChatterjeeMBWK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Chrzanowska-JeskeM05,
author = {Malgorzata Chrzanowska{-}Jeske and
Alan Mishchenko},
title = {Synthesis for regularity using decision diagrams [logic {IC} synthesis
and layout]},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {4721--4724},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465687},
doi = {10.1109/ISCAS.2005.1465687},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Chrzanowska-JeskeM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JiangMB04,
author = {Jie{-}Hong Roland Jiang and
Alan Mishchenko and
Robert K. Brayton},
title = {On breakable cyclic definitions},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {411--418},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382610},
doi = {10.1109/ICCAD.2004.1382610},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/JiangMB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Mishchenko03,
author = {Alan Mishchenko},
title = {Fast computation of symmetries in Boolean functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {11},
pages = {1588--1593},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.818371},
doi = {10.1109/TCAD.2003.818371},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Mishchenko03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongHMCKC03,
author = {Xiaoyu Song and
William N. N. Hung and
Alan Mishchenko and
Malgorzata Chrzanowska{-}Jeske and
Andrew A. Kennings and
Alan J. Coppola},
title = {Board-level multiterminal net assignment for the partial cross-bar
architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {511--514},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812322},
doi = {10.1109/TVLSI.2003.812322},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongHMCKC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishchenkoWK03,
author = {Alan Mishchenko and
Xinning Wang and
Timothy Kam},
title = {A new enhanced constructive decomposition and mapping algorithm},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {143--148},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.775871},
doi = {10.1145/775832.775871},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishchenkoWK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishchenkoS03,
author = {Alan Mishchenko and
Tsutomu Sasao},
title = {Large-scale {SOP} minimization using decomposition and functional
properties},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {149--154},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.775872},
doi = {10.1145/775832.775872},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishchenkoS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JiangMB03,
author = {Jie{-}Hong Roland Jiang and
Alan Mishchenko and
Robert K. Brayton},
title = {Reducing Multi-Valued Algebraic Operations to Binary},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {10752--10757},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10037},
doi = {10.1109/DATE.2003.10037},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/JiangMB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoB03,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {A Theory of Non-Deterministic Networks},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {709--717},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.org/10.1109/ICCAD.2003.1257887},
doi = {10.1109/ICCAD.2003.1257887},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Chrzanowska-Jeske02,
author = {Malgorzata Chrzanowska{-}Jeske and
Alan Mishchenko and
Marek A. Perkowski},
title = {Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including
Minimum ESOPs},
journal = {{VLSI} Design},
volume = {14},
number = {1},
pages = {13--21},
year = {2002},
url = {https://doi.org/10.1080/10655140290009774},
doi = {10.1080/10655140290009774},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Chrzanowska-Jeske02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SongHMCCK02,
author = {Xiaoyu Song and
William N. N. Hung and
Alan Mishchenko and
Malgorzata Chrzanowska{-}Jeske and
Alan J. Coppola and
Andrew A. Kennings},
editor = {Kanad Ghose and
Patrick H. Madden and
Vivek De and
Peter M. Kogge},
title = {Board-level multiterminal net assignment},
booktitle = {Proceedings of the 12th {ACM} Great Lakes Symposium on {VLSI} 2002,
New York, NY, USA, April 18-19, 2002},
pages = {130--135},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505306.505335},
doi = {10.1145/505306.505335},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SongHMCCK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MishchenkoB02,
author = {Alan Mishchenko and
Robert K. Brayton},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Simplification of non-deterministic multi-valued networks},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {557--562},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774654},
doi = {10.1145/774572.774654},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MishchenkoB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SinhaMB02,
author = {Subarnarekha Sinha and
Alan Mishchenko and
Robert K. Brayton},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Topologically constrained logic synthesis},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {679--686},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774672},
doi = {10.1145/774572.774672},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SinhaMB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BraytonGJJLMSV02,
author = {Robert K. Brayton and
M. Gao and
Jie{-}Hong Roland Jiang and
Yunjian Jiang and
Yinghua Li and
Alan Mishchenko and
Subarnarekha Sinha and
Tiziano Villa},
title = {Optimization of Multi-Valued Multi-Level Networks},
booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2002), May 15-18, 2002, Boston, Massachusetts, {USA}},
pages = {168--179},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISMVL.2002.1011086},
doi = {10.1109/ISMVL.2002.1011086},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BraytonGJJLMSV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SinhaMB02,
author = {Subarnarekha Sinha and
Alan Mishchenko and
Robert K. Brayton},
title = {Topologically Constrained Logic Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {13--20},
year = {2002},
timestamp = {Sun, 04 Aug 2019 18:01:44 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SinhaMB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoS02,
author = {Alan Mishchenko and
Tsutomu Sasao},
title = {Encoding of Boolean Functions and its Application to {LUT} Cascade
Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {115--120},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoB02,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {A Boolean Paradigm in Multi-Valued Logic Synthesis},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {173--177},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoP02,
author = {Alan Mishchenko and
Marek A. Perkowski},
title = {Logic Synthesis of Reversible Wave Cascades},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {197--202},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/MishchenkoB02a,
author = {Alan Mishchenko and
Robert K. Brayton},
title = {Simplification of Non-Deterministic Multi-Valued Networks},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {333--338},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/MishchenkoB02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/JiangMB02,
author = {Jie{-}Hong Roland Jiang and
Alan Mishchenko and
Robert K. Brayton},
title = {Reducing Multi-Valued Algebraic Operations to Binary},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {339--344},
year = {2002},
timestamp = {Sun, 04 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iwls/JiangMB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MishchenkoSP01,
author = {Alan Mishchenko and
Bernd Steinbach and
Marek A. Perkowski},
title = {An Algorithm for Bi-Decomposition of Logic Functions},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {103--108},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378353},
doi = {10.1145/378239.378353},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MishchenkoSP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PerkowskiCMSAMKBJC01,
author = {Marek A. Perkowski and
Malgorzata Chrzanowska{-}Jeske and
Alan Mishchenko and
Xiaoyu Song and
Anas Al{-}Rabadi and
Bart Massey and
Pawel Kerntopf and
Andrzej Buller and
Lech J{\'{o}}zwiak and
Alan J. Coppola},
title = {Regular Realization of Symmetric Functions Using Reversible Logic},
booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001),
4-6 September 2001, Warsaw, Poland},
pages = {245--253},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DSD.2001.952289},
doi = {10.1109/DSD.2001.952289},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/PerkowskiCMSAMKBJC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PerkowskiMGBM99,
author = {Marek A. Perkowski and
Rahul Malvi and
Stan Grygiel and
Michael Burns and
Alan Mishchenko},
editor = {Mary Jane Irwin},
title = {Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {225--230},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309918},
doi = {10.1145/309847.309918},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PerkowskiMGBM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eh/PerkowskiMC99,
author = {Marek A. Perkowski and
Alan Mishchenko and
Anatoli N. Chebotarev},
title = {Evolvable Hardware or Learning Hardware? Induction of State Machines
from Temporal Logic Constraints},
booktitle = {1st {NASA} / DoD Workshop on Evolvable Hardware {(EH} '99), July 19-21,
1999, Pasadena, CA, {USA}},
pages = {129--138},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/EH.1999.785444},
doi = {10.1109/EH.1999.785444},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eh/PerkowskiMC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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