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ORCIDBibTeX records: Shigetoshi Nakatake
@article{DBLP:journals/sensors/GengSN20,
author = {Chao Geng and
Qingji Sun and
Shigetoshi Nakatake},
title = {Implementation of Analog Perceptron as an Essential Element of Configurable
Neural Networks},
journal = {Sensors},
volume = {20},
number = {15},
pages = {4222},
year = {2020},
url = {https://doi.org/10.3390/s20154222},
doi = {10.3390/S20154222},
timestamp = {Fri, 25 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sensors/GengSN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mocast/GengSN20,
author = {Chao Geng and
Qingji Sun and
Shigetoshi Nakatake},
title = {An Analog {CMOS} Implementation for Multi-layer Perceptron With ReLU
Activation},
booktitle = {9th International Conference on Modern Circuits and Systems Technologies,
{MOCAST} 2020, Bremen, Germany, September 7-9, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MOCAST49295.2020.9200299},
doi = {10.1109/MOCAST49295.2020.9200299},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mocast/GengSN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ZouN20,
author = {Xuncheng Zou and
Shigetoshi Nakatake},
title = {A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {199--202},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184498},
doi = {10.1109/MWSCAS48704.2020.9184498},
timestamp = {Mon, 21 Sep 2020 12:35:49 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ZouN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZouN19,
author = {Xuncheng Zou and
Shigetoshi Nakatake},
title = {A Low Voltage Stochastic Flash {ADC} without Comparator},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {102-A},
number = {7},
pages = {886--893},
year = {2019},
url = {https://doi.org/10.1587/transfun.E102.A.886},
doi = {10.1587/TRANSFUN.E102.A.886},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/ZouN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/GengLN19,
author = {Chao Geng and
Bo Liu and
Shigetoshi Nakatake},
title = {Density Optimization for Analog Layout Based on Transistor-Array},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {102-A},
number = {12},
pages = {1720--1730},
year = {2019},
url = {https://doi.org/10.1587/transfun.E102.A.1720},
doi = {10.1587/TRANSFUN.E102.A.1720},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/GengLN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ZhangN19,
author = {Xinghuai Zhang and
Shigetoshi Nakatake},
title = {On-chip resistance configuration by subthreshold MOSFET-array for
ultra weak current sensing},
booktitle = {2019 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2019, Bangkok, Thailand, November 11-14, 2019},
pages = {261--264},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/APCCAS47518.2019.8953142},
doi = {10.1109/APCCAS47518.2019.8953142},
timestamp = {Wed, 05 Feb 2020 16:48:41 +0100},
biburl = {https://dblp.org/rec/conf/apccas/ZhangN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/SakaiN19,
author = {Ryosuke Sakai and
Shigetoshi Nakatake},
title = {An Impedance Measurement of Intravesical Urine Volume Appropriate
to Seated Posture},
booktitle = {2019 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2019, Bangkok, Thailand, November 11-14, 2019},
pages = {385--388},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/APCCAS47518.2019.8953100},
doi = {10.1109/APCCAS47518.2019.8953100},
timestamp = {Wed, 05 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/SakaiN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KondoTTN18,
author = {Kenya Kondo and
Koichi Tanno and
Hiroki Tamura and
Shigetoshi Nakatake},
title = {Low Voltage {CMOS} Current Mode Reference Circuit without Operational
Amplifiers},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {101-A},
number = {5},
pages = {748--754},
year = {2018},
url = {https://doi.org/10.1587/transfun.E101.A.748},
doi = {10.1587/TRANSFUN.E101.A.748},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KondoTTN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/IshiguchiION18,
author = {Yoritaka Ishiguchi and
Daishi Isogai and
Takuma Osawa and
Shigetoshi Nakatake},
title = {Analog perceptron circuit with DAC-based multiplier},
journal = {Integr.},
volume = {63},
pages = {240--247},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2018.05.010},
doi = {10.1016/J.VLSI.2018.05.010},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/IshiguchiION18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiuCYN18,
author = {Bo Liu and
Gong Chen and
Bo Yang and
Shigetoshi Nakatake},
title = {Routable and Matched Layout Styles for Analog Module Generation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {23},
number = {4},
pages = {47:1--47:17},
year = {2018},
url = {https://doi.org/10.1145/3182169},
doi = {10.1145/3182169},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LiuCYN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ShirakawaSN18,
author = {Takaaki Shirakawa and
Ryosuke Sakai and
Shigetoshi Nakatake},
title = {On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing
Bridge},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {262--265},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8623881},
doi = {10.1109/MWSCAS.2018.8623881},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ShirakawaSN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/GengN18,
author = {Chao Geng and
Shigetoshi Nakatake},
title = {Hierarchical Floorplanning Based on Analog Structure Tree},
booktitle = {2018 New Generation of CAS, {NGCAS} 2018, Valletta, Malta, November
20-23, 2018},
pages = {138--141},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NGCAS.2018.8572241},
doi = {10.1109/NGCAS.2018.8572241},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ngcas/GengN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/ZouN18,
author = {Xuncheng Zou and
Shigetoshi Nakatake},
title = {Analog Retargeting Constraint Extraction Based on Fundamental Circuits
and Layout Regularity},
booktitle = {2018 New Generation of CAS, {NGCAS} 2018, Valletta, Malta, November
20-23, 2018},
pages = {142--145},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NGCAS.2018.8572209},
doi = {10.1109/NGCAS.2018.8572209},
timestamp = {Thu, 20 Dec 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ngcas/ZouN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZouLN17,
author = {Xuncheng Zou and
Bo Liu and
Shigetoshi Nakatake},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {Low Voltage Stochastic Flash {ADC} with Front-end of Inverter-based
Comparative Unit},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {435--438},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060466},
doi = {10.1145/3060403.3060466},
timestamp = {Wed, 12 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ZouLN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KimHLN17,
author = {Myung{-}Chul Kim and
Shih{-}Hsu Huang and
Rung{-}Bin Lin and
Shigetoshi Nakatake},
editor = {Sri Parameswaran},
title = {Overview of the 2017 {CAD} contest at {ICCAD:} Invited paper},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {855--856},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203867},
doi = {10.1109/ICCAD.2017.8203867},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/KimHLN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/Geng0N17,
author = {Chao Geng and
Bo Liu and
Shigetoshi Nakatake},
title = {Explicit layout pattern density controlling based on transistor-array-style},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {1557--1560},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8053233},
doi = {10.1109/MWSCAS.2017.8053233},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/Geng0N17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/IshiguchiION17,
author = {Yoritaka Ishiguchi and
Daishi Isogai and
Takuma Osawa and
Shigetoshi Nakatake},
title = {A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends},
booktitle = {New Generation of CAS, {NGCAS} 2017, Genova, Italy, September 6-9,
2017},
pages = {93--96},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NGCAS.2017.23},
doi = {10.1109/NGCAS.2017.23},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/ngcas/IshiguchiION17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/IsogaiLIN17,
author = {Daishi Isogai and
Bo Liu and
Yoritaka Ishiguchi and
Shigetoshi Nakatake},
title = {Analog Characterization Module with Data Converter-Coupled Signal
Reconfiguration},
booktitle = {New Generation of CAS, {NGCAS} 2017, Genova, Italy, September 6-9,
2017},
pages = {149--152},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NGCAS.2017.35},
doi = {10.1109/NGCAS.2017.35},
timestamp = {Wed, 12 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ngcas/IsogaiLIN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/GohN16,
author = {Chooi{-}Ling Goh and
Shigetoshi Nakatake},
title = {A Sensor-Based Data Visualization System for Training Blood Pressure
Measurement by Auscultatory Method},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {99-D},
number = {4},
pages = {936--943},
year = {2016},
url = {https://doi.org/10.1587/transinf.2015DAP0010},
doi = {10.1587/TRANSINF.2015DAP0010},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/GohN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HirataNNSMMTY16,
author = {Takuya Hirata and
Ryuta Nishino and
Shigetoshi Nakatake and
Masaya Shimoyama and
Masashi Miyagawa and
Ryoichi Miyauchi and
Koichi Tanno and
Akihiro Yamada},
title = {Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent
Manufacturability Evaluation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {99-A},
number = {7},
pages = {1381--1389},
year = {2016},
url = {https://doi.org/10.1587/transfun.E99.A.1381},
doi = {10.1587/TRANSFUN.E99.A.1381},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HirataNNSMMTY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChenFDNY16,
author = {Gong Chen and
Toru Fujimura and
Qing Dong and
Shigetoshi Nakatake and
Bo Yang},
title = {{DC} Characteristics and Variability on 90nm {CMOS} Transistor Array-Style
Analog Layout},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {21},
number = {3},
pages = {45:1--45:21},
year = {2016},
url = {https://doi.org/10.1145/2888395},
doi = {10.1145/2888395},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ChenFDNY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuangLKN16,
author = {Shih{-}Hsu Huang and
Rung{-}Bin Lin and
Myung{-}Chul Kim and
Shigetoshi Nakatake},
editor = {Frank Liu},
title = {Overview of the 2016 {CAD} contest at {ICCAD}},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {38},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2980070},
doi = {10.1145/2966986.2980070},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/HuangLKN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/LiuNYC16,
author = {Bo Liu and
Shigetoshi Nakatake and
Bo Yang and
Gong Chen},
title = {Twin-row-style for {MOS} analog layout},
booktitle = {2016 {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},
pages = {141--144},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICECS.2016.7841152},
doi = {10.1109/ICECS.2016.7841152},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/LiuNYC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ChenLNY16,
author = {Gong Chen and
Bo Liu and
Shigetoshi Nakatake and
Bo Yang},
title = {Routability of twisted common-centroid capacitor array under signal
coupling constraints},
booktitle = {{IEEE} 59th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/MWSCAS.2016.7870152},
doi = {10.1109/MWSCAS.2016.7870152},
timestamp = {Mon, 05 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ChenLNY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/YahiroLNNTC16,
author = {Nobuyuki Yahiro and
Bo Liu and
Atsushi Nanri and
Shigetoshi Nakatake and
Yasuhiro Takashima and
Gong Chen},
editor = {Peter M. Athanas and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Ron Sass},
title = {A multi-functional memory unit with PLA-based reconfigurable decoder},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2016, Cancun, Mexico, November 30 - Dec. 2, 2016},
pages = {1--7},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ReConFig.2016.7857145},
doi = {10.1109/RECONFIG.2016.7857145},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/YahiroLNNTC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ChenZDLN15,
author = {Gong Chen and
Yu Zhang and
Qing Dong and
Mingyu Li and
Shigetoshi Nakatake},
title = {Layout Dependent Effect-Aware Leakage Current Reduction and Its Application
to Low-Power {SAR-ADC}},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {98-A},
number = {7},
pages = {1442--1454},
year = {2015},
url = {https://doi.org/10.1587/transfun.E98.A.1442},
doi = {10.1587/TRANSFUN.E98.A.1442},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ChenZDLN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HirataNNSMTY15,
author = {Takuya Hirata and
Ryuta Nishino and
Shigetoshi Nakatake and
Masaya Shimoyama and
Masashi Miyagawa and
Koichi Tanno and
Akihiro Yamada},
title = {Subblock-level matching layout for analog block-pair and its manufacturability
evaluation},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {3012--3015},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169321},
doi = {10.1109/ISCAS.2015.7169321},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HirataNNSMTY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MurookaZDN15,
author = {Daijiro Murooka and
Yu Zhang and
Qing Dong and
Shigetoshi Nakatake},
title = {Low-Power and Low-Variability Programmable Delay Element and Its Application
to Post-Silicon Skew Tuning},
booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
Montpellier, France, July 8-10, 2015},
pages = {167--171},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVLSI.2015.91},
doi = {10.1109/ISVLSI.2015.91},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MurookaZDN15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YangDLN13,
author = {Bo Yang and
Qing Dong and
Jing Li and
Shigetoshi Nakatake},
title = {Structured Analog Circuit and Layout Design with Transistor Array},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2475--2486},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2475},
doi = {10.1587/TRANSFUN.E96.A.2475},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YangDLN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhangCYLDLN13,
author = {Yu Zhang and
Gong Chen and
Bo Yang and
Jing Li and
Qing Dong and
Mingyu Li and
Shigetoshi Nakatake},
title = {Analog Circuit Synthesis with Constraint Generation of Layout-Dependent
Effects by Geometric Programming},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2487--2498},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2487},
doi = {10.1587/TRANSFUN.E96.A.2487},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhangCYLDLN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChenYZDN13,
author = {Gong Chen and
Bo Yang and
Yu Zhang and
Qing Dong and
Shigetoshi Nakatake},
editor = {Jos{\'{e}} Luis Ayala and
Alex K. Jones and
Patrick H. Madden and
Ayse K. Coskun},
title = {A 9-bit 50msps {SAR} {ADC} with pre-charge {VCM} -based double input
range algorithm},
booktitle = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
France, May 2-4, 2013},
pages = {315--316},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2483028.2483119},
doi = {10.1145/2483028.2483119},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ChenYZDN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/Nakatake13,
author = {Shigetoshi Nakatake},
editor = {Cheng{-}Kok Koh and
Cliff C. N. Sze},
title = {Practicality on placement given by optimality of packing},
booktitle = {International Symposium on Physical Design, ISPD'13, Stateline, NV,
USA, March 24-27, 2013},
pages = {59--60},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2451916.2451931},
doi = {10.1145/2451916.2451931},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/Nakatake13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenZYDN13,
author = {Gong Chen and
Yu Zhang and
Bo Yang and
Qing Dong and
Shigetoshi Nakatake},
title = {A comparator energy model considering shallow trench isolation stress
by geometric programming},
booktitle = {International Symposium on Quality Electronic Design, {ISQED} 2013,
Santa Clara, CA, USA, March 4-6, 2013},
pages = {585--590},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISQED.2013.6523670},
doi = {10.1109/ISQED.2013.6523670},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChenZYDN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhangCDLN13,
author = {Yu Zhang and
Gong Chen and
Qing Dong and
Mingyu Li and
Shigetoshi Nakatake},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Performance-driven {SRAM} macro design with parameterized cell considering
layout-dependent effects},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {156--161},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673268},
doi = {10.1109/VLSI-SOC.2013.6673268},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhangCDLN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LiuYN12,
author = {Bo Liu and
Bo Yang and
Shigetoshi Nakatake},
title = {Layout-Aware Variability Characterization of {CMOS} Current Sources},
journal = {{IEICE} Trans. Electron.},
volume = {95-C},
number = {4},
pages = {696--705},
year = {2012},
url = {https://doi.org/10.1587/transele.E95.C.696},
doi = {10.1587/TRANSELE.E95.C.696},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LiuYN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenYNHI12,
author = {Gong Chen and
Bo Yang and
Shigetoshi Nakatake and
Zhangcai Huang and
Yasuaki Inoue},
title = {A retargeting methodology of nano-watt {CMOS} reference circuit based
on advanced compact {MOSFET} model},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {938--941},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6272199},
doi = {10.1109/ISCAS.2012.6272199},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenYNHI12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ZhangLYLN12,
author = {Yu Zhang and
Bo Liu and
Bo Yang and
Jing Li and
Shigetoshi Nakatake},
editor = {Keith A. Bowman and
Kamesh V. Gadepally and
Pallab Chatterjee and
Mark M. Budnik and
Lalitha Immaneni},
title = {{CMOS} op-amp circuit synthesis with geometric programming models
for layout-dependent effects},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
2012, Santa Clara, CA, USA, March 19-21, 2012},
pages = {464--469},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISQED.2012.6187534},
doi = {10.1109/ISQED.2012.6187534},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ZhangLYLN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/DongYCLN12,
author = {Qing Dong and
Bo Yang and
Gong Chen and
Jing Li and
Shigetoshi Nakatake},
editor = {Keith A. Bowman and
Kamesh V. Gadepally and
Pallab Chatterjee and
Mark M. Budnik and
Lalitha Immaneni},
title = {Transistor channel decomposition for structured analog layout, manufacturability
and low-power applications},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
2012, Santa Clara, CA, USA, March 19-21, 2012},
pages = {656--662},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISQED.2012.6187562},
doi = {10.1109/ISQED.2012.6187562},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/DongYCLN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ShinoharaHLDYN11,
author = {Kota Shinohara and
Mihoko Hidaka and
Jing Li and
Qing Dong and
Bo Yang and
Shigetoshi Nakatake},
editor = {David Atienza and
Yuan Xie and
Jos{\'{e}} L. Ayala and
Ken S. Stevens},
title = {Layout-aware variation evaluation of analog circuits and its validity
on op-amp designs},
booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
Lausanne, Switzerland, May 2-6, 2011},
pages = {247--252},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1973009.1973059},
doi = {10.1145/1973009.1973059},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ShinoharaHLDYN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiuDYLN11,
author = {Bo Liu and
Qing Dong and
Bo Yang and
Jing Li and
Shigetoshi Nakatake},
title = {Layout-aware mismatch modeling for {CMOS} current sources with {D/A}
converter analysis},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {525--532},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770777},
doi = {10.1109/ISQED.2011.5770777},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LiuDYLN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NakatakeKIKKIH10,
author = {Shigetoshi Nakatake and
Masahiro Kawakita and
Takao Ito and
Masahiro Kojima and
Michiko Kojima and
Kenji Izumi and
Tadayuki Habasaki},
title = {Regularity-Oriented Analog Placement with Conditional Design Rules},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {93-A},
number = {12},
pages = {2389--2398},
year = {2010},
url = {https://doi.org/10.1587/transfun.E93.A.2389},
doi = {10.1587/TRANSFUN.E93.A.2389},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/NakatakeKIKKIH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KatoEINYI10,
author = {Kokoro Kato and
Masakazu Endo and
Tadao Inoue and
Shigetoshi Nakatake and
Masaki Yamabe and
Sunao Ishihara},
title = {Photomask Data Prioritization Based on {VLSI} Design Intent and Its
Utilization for Mask Manufacturing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {93-A},
number = {12},
pages = {2424--2432},
year = {2010},
url = {https://doi.org/10.1587/transfun.E93.A.2424},
doi = {10.1587/TRANSFUN.E93.A.2424},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KatoEINYI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NakatakeKIKKIH10,
author = {Shigetoshi Nakatake and
Masahiro Kawakita and
Takao Ito and
Masahiro Kojima and
Michiko Kojima and
Kenji Izumi and
Tadayuki Habasaki},
title = {Regularity-oriented analog placement with diffusion sharing and well
island generation},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {305--311},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419878},
doi = {10.1109/ASPDAC.2010.5419878},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/NakatakeKIKKIH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuFYN10,
author = {Bo Liu and
Toru Fujimura and
Bo Yang and
Shigetoshi Nakatake},
title = {{D-A} converter based variation analysis for analog layout design},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {843--848},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419687},
doi = {10.1109/ASPDAC.2010.5419687},
timestamp = {Wed, 12 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LiuFYN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangDLN10,
author = {Bo Yang and
Qing Dong and
Jing Li and
Shigetoshi Nakatake},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Structured analog circuit design and {MOS} transistor decomposition
for high accuracy applications},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {721--728},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654264},
doi = {10.1109/ICCAD.2010.5654264},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YangDLN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiYDN10,
author = {Jing Li and
Bo Yang and
Qing Dong and
Shigetoshi Nakatake},
title = {Post-placement {STI} well width adjusting by geometric programming
for device mobility enhancement in critical path},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {929--932},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537398},
doi = {10.1109/ISCAS.2010.5537398},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiYDN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YangN09,
author = {Bo Yang and
Shigetoshi Nakatake},
title = {Fast Shape Optimization of Metalization Patterns for Power-MOSFET
Based Driver},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {92-A},
number = {12},
pages = {3052--3060},
year = {2009},
url = {https://doi.org/10.1587/transfun.E92.A.3052},
doi = {10.1587/TRANSFUN.E92.A.3052},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YangN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/DongYLN09,
author = {Qing Dong and
Bo Yang and
Jing Li and
Shigetoshi Nakatake},
title = {Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric
Programming},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {92-A},
number = {12},
pages = {3103--3110},
year = {2009},
url = {https://doi.org/10.1587/transfun.E92.A.3103},
doi = {10.1587/TRANSFUN.E92.A.3103},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/DongYLN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/DongN09,
author = {Qing Dong and
Shigetoshi Nakatake},
title = {Structured Placement with Topological Regularity Evaluation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {222--238},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.222},
doi = {10.2197/IPSJTSLDM.2.222},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/DongN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiYHDN09,
author = {Jing Li and
Bo Yang and
Xiaochuan Hu and
Qing Dong and
Shigetoshi Nakatake},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {{STI} stress aware placement optimization based on geometric programming},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {209--214},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531594},
doi = {10.1145/1531542.1531594},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/LiYHDN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DongYLN09,
author = {Qing Dong and
Bo Yang and
Jing Li and
Shigetoshi Nakatake},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {Incremental buffer insertion and module resizing algorithm using geometric
programming},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {413--416},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531636},
doi = {10.1145/1531542.1531636},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/DongYLN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YangMN08,
author = {Bo Yang and
Hiroshi Murata and
Shigetoshi Nakatake},
title = {A Finite Element-Domain Decomposition Coupled Resistance Extraction
Method with Virtual Terminal Insertion},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {91-A},
number = {2},
pages = {542--549},
year = {2008},
url = {https://doi.org/10.1093/ietfec/e91-a.2.542},
doi = {10.1093/IETFEC/E91-A.2.542},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YangMN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DongN08,
author = {Qing Dong and
Shigetoshi Nakatake},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Constraint-free analog placement with topological symmetry structure},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {186--191},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483937},
doi = {10.1109/ASPDAC.2008.4483937},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DongN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FujimuraN08,
author = {Toru Fujimura and
Shigetoshi Nakatake},
title = {Transistor-level programmable {MOS} analog {IC} with body biasing},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {153--156},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4541377},
doi = {10.1109/ISCAS.2008.4541377},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/FujimuraN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/YangNM08,
author = {Bo Yang and
Shigetoshi Nakatake and
Hiroshi Murata},
title = {Fast Shape Optimization of Metallization Patterns for {DMOS} Based
Driver},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {617--620},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479808},
doi = {10.1109/ISQED.2008.4479808},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/YangNM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Nakatake07,
author = {Shigetoshi Nakatake},
title = {Structured Placement with Topological Regularity Evaluation},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {215--220},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357988},
doi = {10.1109/ASPDAC.2007.357988},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Nakatake07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NakatakeKTS07,
author = {Shigetoshi Nakatake and
Zohreh Karimi and
Taraneh Taghavi and
Majid Sarrafzadeh},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Block placement to ensure channel routability},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {465--468},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228894},
doi = {10.1145/1228784.1228894},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/NakatakeKTS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/FuNTK06,
author = {Ning Fu and
Shigetoshi Nakatake and
Yasuhiro Takashima and
Yoji Kajitani},
title = {The Oct-Touched Tile: {A} New Architecture for Shape-Based Routing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {89-A},
number = {2},
pages = {448--455},
year = {2006},
url = {https://doi.org/10.1093/ietfec/e89-a.2.448},
doi = {10.1093/IETFEC/E89-A.2.448},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/FuNTK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KidaMTN06,
author = {Keiji Kida and
Takehiko Matsuo and
Tetsuya Tashiro and
Shigetoshi Nakatake},
title = {Sequence-Pair Based Compaction under Equi-Length Constraint},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {1015--1018},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342260},
doi = {10.1109/APCCAS.2006.342260},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/KidaMTN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/NojimaONFOK06,
author = {Takashi Nojima and
Nobuto Ono and
Shigetoshi Nakatake and
Toru Fujimura and
Koji Okazaki and
Yoji Kajitani},
title = {Adaptive Porting of Analog IPs with Reusable Conservative Properties},
booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2006), 2-3 March 2006, Karlsruhe, Germany},
pages = {18--23},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISVLSI.2006.15},
doi = {10.1109/ISVLSI.2006.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/NojimaONFOK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/FuMN06,
author = {Ning Fu and
Mitsutoshi Mineshima and
Shigetoshi Nakatake},
title = {Multi-SP: {A} Representation with United Rectangles for Analog Placement
and Routing},
booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2006), 2-3 March 2006, Karlsruhe, Germany},
pages = {38--43},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISVLSI.2006.64},
doi = {10.1109/ISVLSI.2006.64},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/FuMN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YanNN06,
author = {Tan Yan and
Shigetoshi Nakatake and
Takashi Nojima},
title = {Formulating the Empirical Strategies in Module Generation of Analog
{MOS} Layout},
booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2006), 2-3 March 2006, Karlsruhe, Germany},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISVLSI.2006.47},
doi = {10.1109/ISVLSI.2006.47},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YanNN06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FuNTK05,
author = {Ning Fu and
Shigetoshi Nakatake and
Yasuhiro Takashima and
Yoji Kajitani},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {The oct-touched tile: a new architecture for shape-based routing},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {126--129},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057692},
doi = {10.1145/1057661.1057692},
timestamp = {Wed, 15 Dec 2021 17:59:57 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/FuNTK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FuNTK04,
author = {Ning Fu and
Shigetoshi Nakatake and
Yasuhiro Takashima and
Yoji Kajitani},
editor = {Masaharu Imai},
title = {Abstraction and optimization of consistent floorplanning with pillar
block constraints},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {19--24},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.38},
doi = {10.1109/ASPDAC.2004.38},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/FuNTK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NojimaZTNK04,
author = {Takashi Nojima and
Xiaoke Zhu and
Yasuhiro Takashima and
Shigetoshi Nakatake and
Yoji Kajitani},
editor = {Masaharu Imai},
title = {Multi-level placement with circuit schema based clustering in analog
{IC} layouts},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {406--411},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.142},
doi = {10.1109/ASPDAC.2004.142},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/NojimaZTNK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NojimaTNK04,
author = {Takashi Nojima and
Yasuhiro Takashima and
Shigetoshi Nakatake and
Yoji Kajitani},
editor = {David Garrett and
John C. Lach and
Charles A. Zukowski},
title = {A device-level placement with multi-directional convex clustering},
booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
Boston, MA, USA, April 26-28, 2004},
pages = {196--201},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/988952.989001},
doi = {10.1145/988952.989001},
timestamp = {Fri, 20 Aug 2021 16:30:37 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/NojimaTNK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KidaZZTN04,
author = {Keiji Kida and
Xiaoke Zhu and
Changwen Zhuang and
Yasuhiro Takashima and
Shigetoshi Nakatake},
title = {A fast algorithm for crosspoint assignment under crosstalk constraints
with shielding effects},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {489--492},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KidaZZTN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/KuboNKK03,
author = {Yukiko Kubo and
Shigetoshi Nakatake and
Yoji Kajitani and
Masahiro Kawakita},
title = {An Incremental Wiring Algorithm for {VLSI} Layout Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {5},
pages = {1203--1206},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_5\_1203},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/KuboNKK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NakatakeKK02,
author = {Shigetoshi Nakatake and
Yukiko Kubo and
Yoji Kajitani},
title = {Consistent floorplanning with hierarchical superconstraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {1},
pages = {42--49},
year = {2002},
url = {https://doi.org/10.1109/43.974136},
doi = {10.1109/43.974136},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NakatakeKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KuboNKK02,
author = {Yukiko Kubo and
Shigetoshi Nakatake and
Yoji Kajitani and
Masahiro Kawakita},
title = {Chip size estimation based on wiring area},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2002, {APCCAS}
2002, Singapore, 16-18 December 2002},
pages = {113--118},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/APCCAS.2002.1115136},
doi = {10.1109/APCCAS.2002.1115136},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/KuboNKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KuboNKK02,
author = {Yukiko Kubo and
Shigetoshi Nakatake and
Yoji Kajitani and
Masahiro Kawakita},
title = {Explicit Expression and Simultaneous Optimization of Placement and
Routing for Analog {IC} Layouts},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {467--472},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.994964},
doi = {10.1109/ASPDAC.2002.994964},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KuboNKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/NakatakeKK01,
author = {Shigetoshi Nakatake and
Yukiko Kubo and
Yoji Kajitani},
editor = {Sachin S. Sapatnekar and
Manfred Wiesel},
title = {Consistent floorplanning with super hierarchical constraints},
booktitle = {Proceedings of the 2001 International Symposium on Physical Design,
{ISPD} 2001, Sonoma County, CA, USA, April 1-4, 2001},
pages = {144--149},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/369691.369755},
doi = {10.1145/369691.369755},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/NakatakeKK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KuboTNK00,
author = {Yukiko Kubo and
Yasuhiro Takashima and
Shigetoshi Nakatake and
Yoji Kajitani},
title = {Self-reforming routing for stochastic search in {VLSI} interconnection
layout},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {87--92},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368584},
doi = {10.1145/368434.368584},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KuboTNK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KajitaniTAN00,
author = {Yoji Kajitani and
Atsushi Takahashi and
Kengo R. Azegami and
Shigetoshi Nakatake},
title = {Partition, Packing and Clock Distribution-A New Paradigm of Physical
Design},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {11},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812577},
doi = {10.1109/ICVD.2000.812577},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/KajitaniTAN00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NakatakeFMK98,
author = {Shigetoshi Nakatake and
Kunihiro Fujiyoshi and
Hiroshi Murata and
Yoji Kajitani},
title = {Module packing based on the BSG-structure and {IC} layout applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {6},
pages = {519--530},
year = {1998},
url = {https://doi.org/10.1109/43.703832},
doi = {10.1109/43.703832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NakatakeFMK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NakatakeFK98,
author = {Shigetoshi Nakatake and
Masahiro Furuya and
Yoji Kajitani},
title = {Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear
Modules},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {571--576},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669558},
doi = {10.1109/ASPDAC.1998.669558},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/NakatakeFK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SakanushiNK98,
author = {Keishi Sakanushi and
Shigetoshi Nakatake and
Yoji Kajitani},
editor = {Hiroto Yasuura},
title = {The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear
blocks},
booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
pages = {267--274},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/288548.288624},
doi = {10.1145/288548.288624},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SakanushiNK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NakatakeSKK98,
author = {Shigetoshi Nakatake and
Keishi Sakanushi and
Yoji Kajitani and
Masahiro Kawakita},
editor = {Hiroto Yasuura},
title = {The channeled-BSG: a universal floorplan for simultaneous place/route
with {IC} applications},
booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
pages = {418--425},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/288548.289064},
doi = {10.1145/288548.289064},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/NakatakeSKK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MurataFNK96,
author = {Hiroshi Murata and
Kunihiro Fujiyoshi and
Shigetoshi Nakatake and
Yoji Kajitani},
title = {{VLSI} module placement based on rectangle-packing by the sequence-pair},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {15},
number = {12},
pages = {1518--1524},
year = {1996},
url = {https://doi.org/10.1109/43.552084},
doi = {10.1109/43.552084},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MurataFNK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NakatakeFMK96,
author = {Shigetoshi Nakatake and
Kunihiro Fujiyoshi and
Hiroshi Murata and
Yoji Kajitani},
editor = {Rob A. Rutenbar and
Ralph H. J. M. Otten},
title = {Module placement on BSG-structure and {IC} layout applications},
booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996},
pages = {484--491},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1996},
url = {https://doi.org/10.1109/ICCAD.1996.569870},
doi = {10.1109/ICCAD.1996.569870},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/NakatakeFMK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MurataFNK95,
author = {Hiroshi Murata and
Kunihiro Fujiyoshi and
Shigetoshi Nakatake and
Yoji Kajitani},
editor = {Richard L. Rudell},
title = {Rectangle-packing-based module placement},
booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
pages = {472--479},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1995},
url = {https://doi.org/10.1109/ICCAD.1995.480159},
doi = {10.1109/ICCAD.1995.480159},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MurataFNK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NakatakeK94,
author = {Shigetoshi Nakatake and
Yoji Kajitani},
editor = {Jochen A. G. Jess and
Richard L. Rudell},
title = {Channel-driven global routing with consistent placement (extended
abstract)},
booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994},
pages = {350--355},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1994},
url = {https://doi.org/10.1109/ICCAD.1994.629816},
doi = {10.1109/ICCAD.1994.629816},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/NakatakeK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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