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ORCIDBibTeX records: Hidetoshi Onodera
@article{DBLP:journals/ieiceta/SonodaSO23,
author = {Shoya Sonoda and
Jun Shiomi and
Hidetoshi Onodera},
title = {Approximation-Based System Implementation for Real-Time Minimum Energy
Point Tracking over a Wide Operating Performance Region},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {106},
number = {3},
pages = {542--550},
year = {2023},
url = {https://doi.org/10.1587/transfun.2022vlp0006},
doi = {10.1587/TRANSFUN.2022VLP0006},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceta/SonodaSO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLNSFCO22,
author = {Yih{-}Lang Li and
Shih{-}Ting Lin and
Shinichi Nishizawa and
Hong{-}Yan Su and
Ming{-}Jie Fong and
Oscar Chen and
Hidetoshi Onodera},
title = {NCTUcell: {A} {DDA-} and Delay-Aware Cell Library Generator for FinFET
Structure With Implicitly Adjustable Grid Map},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {12},
pages = {5568--5581},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3167339},
doi = {10.1109/TCAD.2022.3167339},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiLNSFCO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/SonodaSO22,
author = {Shoya Sonoda and
Jun Shiomi and
Hidetoshi Onodera},
title = {Approximation-Based Implementation for a Minimum Energy Point Tracking
Algorithm over a Wide Operating Performance Region},
booktitle = {13th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2022, Puerto Varas, Chile, March 1-4, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LASCAS53948.2022.9789067},
doi = {10.1109/LASCAS53948.2022.9789067},
timestamp = {Mon, 13 Jun 2022 16:53:37 +0200},
biburl = {https://dblp.org/rec/conf/lascas/SonodaSO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/ShiomiTIO22,
author = {Jun Shiomi and
Shogo Terada and
Tohru Ishihara and
Hidetoshi Onodera},
editor = {Sakir Sezer and
Thomas B{\"{u}}chner and
J{\"{u}}rgen Becker and
Andrew Marshall and
Fahad Siddiqui and
Tanja Harbaum and
Kieran McLaughlin},
title = {Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in
Voltage-Scaled Circuits},
booktitle = {35th {IEEE} International System-on-Chip Conference, {SOCC} 2022,
Belfast, United Kingdom, September 5-8, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/SOCC56010.2022.9908116},
doi = {10.1109/SOCC56010.2022.9908116},
timestamp = {Fri, 21 Oct 2022 09:20:15 +0200},
biburl = {https://dblp.org/rec/conf/socc/ShiomiTIO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/XuSO21,
author = {Hongjie Xu and
Jun Shiomi and
Hidetoshi Onodera},
title = {Evaluation Metrics for the Cost of Data Movement in Deep Neural Network
Acceleration},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {104-A},
number = {11},
pages = {1488--1498},
year = {2021},
url = {https://doi.org/10.1587/transfun.2020kep0003},
doi = {10.1587/TRANSFUN.2020KEP0003},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/XuSO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/MatsuoSIOSN21,
author = {Ryosuke Matsuo and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
title = {A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient
Integrated Optical Logic Circuits},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {104-A},
number = {11},
pages = {1546--1554},
year = {2021},
url = {https://doi.org/10.1587/transfun.2020kep0018},
doi = {10.1587/TRANSFUN.2020KEP0018},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/MatsuoSIOSN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/SonodaSO21,
author = {Shoya Sonoda and
Jun Shiomi and
Hidetoshi Onodera},
title = {Supply and Threshold Voltage Scaling for Minimum Energy Operation
over a Wide Operating Performance Region},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {104-A},
number = {11},
pages = {1566--1576},
year = {2021},
url = {https://doi.org/10.1587/transfun.2020kep0013},
doi = {10.1587/TRANSFUN.2020KEP0013},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/SonodaSO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetc/NagaiSO21,
author = {Kentaro Nagai and
Jun Shiomi and
Hidetoshi Onodera},
title = {A DLL-Based Body Bias Generator with Independent P-Well and N-Well
Biasing for Minimum Energy Operation},
journal = {{IEICE} Trans. Electron.},
volume = {104-C},
number = {10},
pages = {617--624},
year = {2021},
url = {https://doi.org/10.1587/transele.2020ctp0002},
doi = {10.1587/TRANSELE.2020CTP0002},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetc/NagaiSO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NishizawaLLO21,
author = {Shinichi Nishizawa and
Shih{-}Ting Lin and
Yih{-}Lang Li and
Hidetoshi Onodera},
title = {Supplemental {PDK} for {ASAP7} Using Synopsys Flow},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {24--26},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.24},
doi = {10.2197/IPSJTSLDM.14.24},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NishizawaLLO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ojcands/XuSO21,
author = {Hongjie Xu and
Jun Shiomi and
Hidetoshi Onodera},
title = {{MOSDA:} On-Chip Memory Optimized Sparse Deep Neural Network Accelerator
With Efficient Index Matching},
journal = {{IEEE} Open J. Circuits Syst.},
volume = {2},
pages = {144--155},
year = {2021},
url = {https://doi.org/10.1109/OJCAS.2020.3035402},
doi = {10.1109/OJCAS.2020.3035402},
timestamp = {Thu, 29 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ojcands/XuSO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ShiomiKDOSN21,
author = {Jun Shiomi and
Shuya Kotsugi and
Boyu Dong and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
title = {Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {139--144},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586142},
doi = {10.1109/DAC18074.2021.9586142},
timestamp = {Fri, 12 Nov 2021 12:31:50 +0100},
biburl = {https://dblp.org/rec/conf/dac/ShiomiKDOSN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/MurakamiIO21,
author = {Kensuke Murakami and
Mahfuzul Islam and
Hidetoshi Onodera},
title = {{CDF} Distance Based Statistical Parameter Extraction Using Nonlinear
Delay Variation Models},
booktitle = {27th {IEEE} International Symposium on On-Line Testing and Robust
System Design, {IOLTS} 2021, Torino, Italy, June 28-30, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/IOLTS52814.2021.9486684},
doi = {10.1109/IOLTS52814.2021.9486684},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iolts/MurakamiIO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetc/TsuchiyaHTFMNO20,
author = {Akira Tsuchiya and
Akitaka Hiratsuka and
Kenji Tanaka and
Hiroyuki Fukuyama and
Naoki Miura and
Hideyuki Nosaka and
Hidetoshi Onodera},
title = {Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm\({}^{\mbox{2}}\) Transimpedance
Amplifier with Peaking-Dedicated Inductor in 65-nm {CMOS}},
journal = {{IEICE} Trans. Electron.},
volume = {103-C},
number = {10},
pages = {489--496},
year = {2020},
url = {https://doi.org/10.1587/transele.2019CTP0008},
doi = {10.1587/TRANSELE.2019CTP0008},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicetc/TsuchiyaHTFMNO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/NagaiSO20,
author = {Kentaro Nagai and
Jun Shiomi and
Hidetoshi Onodera},
title = {A DLL-based Body Bias Generator for Minimum Energy Operation with
Independent P-well and N-well Bias},
booktitle = {2020 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2020, Ha Long, Vietnam, December 8-10, 2020},
pages = {31--34},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/APCCAS50809.2020.9301711},
doi = {10.1109/APCCAS50809.2020.9301711},
timestamp = {Wed, 27 Jan 2021 14:35:03 +0100},
biburl = {https://dblp.org/rec/conf/apccas/NagaiSO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/XuSO20,
author = {Hongjie Xu and
Jun Shiomi and
Hidetoshi Onodera},
editor = {Tinoosh Mohsenin and
Weisheng Zhao and
Yiran Chen and
Onur Mutlu},
title = {On-chip Memory Optimized {CNN} Accelerator with Efficient Partial-sum
Accumulation},
booktitle = {{GLSVLSI} '20: Great Lakes Symposium on {VLSI} 2020, Virtual Event,
China, September 7-9, 2020},
pages = {21--26},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3386263.3406925},
doi = {10.1145/3386263.3406925},
timestamp = {Mon, 04 Jul 2022 14:19:34 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/XuSO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiLNO20,
author = {Yih{-}Lang Li and
Shih{-}Ting Lin and
Shinichi Nishizawa and
Hidetoshi Onodera},
title = {MCell: Multi-Row Cell Layout Synthesis with Resource Constrained {MAX-SAT}
Based Detailed Routing},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {157:1--157:8},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415612},
doi = {10.1145/3400302.3415612},
timestamp = {Mon, 18 Jan 2021 09:56:56 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LiLNO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icrc/ShiomiIOSN20,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
title = {An Optical Accelerator for Deep Neural Network Based on Integrated
Nanophotonics},
booktitle = {International Conference on Rebooting Computing, {ICRC} 2020, Atlanta,
GA, USA, December 1-3, 2020},
pages = {95--101},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICRC2020.2020.00017},
doi = {10.1109/ICRC2020.2020.00017},
timestamp = {Fri, 30 Apr 2021 12:35:40 +0200},
biburl = {https://dblp.org/rec/conf/icrc/ShiomiIOSN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HashimotoBBTSYD20,
author = {Masanori Hashimoto and
Xu Bai and
Naoki Banno and
Munehiro Tada and
Toshitsugu Sakamoto and
Jaehoon Yu and
Ryutaro Doi and
Yusuke Araki and
Hidetoshi Onodera and
Takashi Imagawa and
Hiroyuki Ochi and
Kazutoshi Wakabayashi and
Yukio Mitsuyama and
Tadahiko Sugibayashi},
title = {33.3 Via-Switch {FPGA:} 65nm {CMOS} Implementation and Architecture
Extension for Al Applications},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {502--504},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062908},
doi = {10.1109/ISSCC19947.2020.9062908},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HashimotoBBTSYD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MatsuoSIOSN20,
author = {Ryosuke Matsuo and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
title = {A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits
Towards Light Speed Processing},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {488--493},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.000-9},
doi = {10.1109/ISVLSI49217.2020.000-9},
timestamp = {Wed, 12 Aug 2020 14:38:21 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/MatsuoSIOSN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/SonodaSO20,
author = {Shoya Sonoda and
Jun Shiomi and
Hidetoshi Onodera},
title = {Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy
Optimization over a Wide Operating Performance Region},
booktitle = {33rd {IEEE} International System-on-Chip Conference, SoCC 2020, Las
Vegas, NV, USA, September 8-11, 2020},
pages = {236--241},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SOCC49529.2020.9524767},
doi = {10.1109/SOCC49529.2020.9524767},
timestamp = {Tue, 14 Sep 2021 10:14:37 +0200},
biburl = {https://dblp.org/rec/conf/socc/SonodaSO20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KoyanagiSIO19,
author = {Takuya Koyanagi and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {A Design Method of a Cell-Based Amplifier for Body Bias Generation},
journal = {{IEICE} Trans. Electron.},
volume = {102-C},
number = {7},
pages = {565--572},
year = {2019},
url = {https://doi.org/10.1587/transele.2018CTP0014},
doi = {10.1587/TRANSELE.2018CTP0014},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KoyanagiSIO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsuchiyaHIKO19,
author = {Akira Tsuchiya and
Akitaka Hiratsuka and
Toshiyuki Inoue and
Keiji Kishine and
Hidetoshi Onodera},
title = {Impact of On-Chip Inductor and Power-Delivery-Network Stacking on
Signal and Power Integrity},
journal = {{IEICE} Trans. Electron.},
volume = {102-C},
number = {7},
pages = {573--579},
year = {2019},
url = {https://doi.org/10.1587/transele.2018CTP0007},
doi = {10.1587/TRANSELE.2018CTP0007},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/TsuchiyaHIKO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/XuSIO19,
author = {Hongjie Xu and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {On-Chip Cache Architecture Exploiting Hybrid Memory Structures for
Near-Threshold Computing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {102-A},
number = {12},
pages = {1741--1750},
year = {2019},
url = {https://doi.org/10.1587/transfun.E102.A.1741},
doi = {10.1587/TRANSFUN.E102.A.1741},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/XuSIO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MatsuoSIOSN19,
author = {Ryosuke Matsuo and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
title = {Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {102-A},
number = {12},
pages = {1751--1759},
year = {2019},
url = {https://doi.org/10.1587/transfun.E102.A.1751},
doi = {10.1587/TRANSFUN.E102.A.1751},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/MatsuoSIOSN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShiomiIO19,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Area-efficient fully digital memory using minimum height standard
cells for near-threshold voltage computing},
journal = {Integr.},
volume = {65},
pages = {201--210},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2017.07.001},
doi = {10.1016/J.VLSI.2017.07.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShiomiIO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/IslamO19,
author = {A. K. M. Mahfuzul Islam and
Hidetoshi Onodera},
title = {Circuit Techniques for Device-Circuit Interaction toward Minimum Energy
Operation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {2--12},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.2},
doi = {10.2197/IPSJTSLDM.12.2},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/IslamO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MatsuoSIOSN19,
author = {Ryosuke Matsuo and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
editor = {Toshiyuki Shibuya},
title = {BDD-based synthesis of optical logic circuits exploiting wavelength
division multiplexing},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {203--209},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287703},
doi = {10.1145/3287624.3287703},
timestamp = {Sun, 20 Jan 2019 16:08:16 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MatsuoSIOSN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiLNSFCO19,
author = {Yih{-}Lang Li and
Shih{-}Ting Lin and
Shinichi Nishizawa and
Hong{-}Yan Su and
Ming{-}Jie Fong and
Oscar Chen and
Hidetoshi Onodera},
title = {NCTUcell: {A} DDA-Aware Cell Library Generator for FinFET Structure
with Implicitly Adjustable Grid Map},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {120},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317868},
doi = {10.1145/3316781.3317868},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiLNSFCO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/IslamSO19,
author = {A. K. M. Mahfuzul Islam and
Ryota Shimizu and
Hidetoshi Onodera},
title = {Analysis of Random Telegraph Noise {(RTN)} at Near-Threshold Operation
by Measuring 154k Ring Oscillators},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2019, Monterey,
CA, USA, March 31 - April 4, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IRPS.2019.8720608},
doi = {10.1109/IRPS.2019.8720608},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/irps/IslamSO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/TsuchiyaHTFMNO19,
author = {Akira Tsuchiya and
Akitaka Hiratsuka and
Kenji Tanaka and
Hiroyuki Fukuyama and
Naoki Miura and
Hideyuki Nosaka and
Hidetoshi Onodera},
title = {A 45 Gb/s, 98 fJ/bit, 0.02 mm\({}^{\mbox{2}}\) Transimpedance Amplifier
with Peaking-Dedicated Inductor in 65-nm {CMOS}},
booktitle = {32nd {IEEE} International System-on-Chip Conference, {SOCC} 2019,
Singapore, September 3-6, 2019},
pages = {150--154},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SOCC46988.2019.1570548520},
doi = {10.1109/SOCC46988.2019.1570548520},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/TsuchiyaHTFMNO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/HiharaIHOMOKWST18,
author = {Hiroki Hihara and
Akira Iwasaki and
Masanori Hashimoto and
Hiroyuki Ochi and
Yukio Mitsuyama and
Hidetoshi Onodera and
Hiroyuki Kanbara and
Kazutoshi Wakabayashi and
Tadahiko Sugibayashi and
Takashi Takenaka and
Hiromitsu Hada and
Munehiro Tada and
Makoto Miyamura and
Toshitsugu Sakamoto},
title = {Sensor Signal Processing Using High-Level Synthesis With a Layered
Architecture},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {10},
number = {4},
pages = {119--122},
year = {2018},
url = {https://doi.org/10.1109/LES.2018.2797064},
doi = {10.1109/LES.2018.2797064},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/HiharaIHOMOKWST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NishizawaO18,
author = {Shinichi Nishizawa and
Hidetoshi Onodera},
title = {Design Methodology for Variation Tolerant D-Flip-Flop Using Regression
Analysis},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {101-A},
number = {12},
pages = {2222--2230},
year = {2018},
url = {https://doi.org/10.1587/transfun.E101.A.2222},
doi = {10.1587/TRANSFUN.E101.A.2222},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/NishizawaO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/ShiomiHIO18,
author = {Jun Shiomi and
Shu Hokimoto and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Minimum Energy Point Tracking with All-Digital On-Chip Sensors},
journal = {J. Low Power Electron.},
volume = {14},
number = {2},
pages = {227--235},
year = {2018},
url = {https://doi.org/10.1166/jolpe.2018.1561},
doi = {10.1166/JOLPE.2018.1561},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/ShiomiHIO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OchiYFHKHIDTSTW18,
author = {Hiroyuki Ochi and
Kosei Yamaguchi and
Tetsuaki Fujimoto and
Junshi Hotate and
Takashi Kishimoto and
Toshiki Higashi and
Takashi Imagawa and
Ryutaro Doi and
Munehiro Tada and
Tadahiko Sugibayashi and
Wataru Takahashi and
Kazutoshi Wakabayashi and
Hidetoshi Onodera and
Yukio Mitsuyama and
Jaehoon Yu and
Masanori Hashimoto},
title = {Via-Switch {FPGA:} Highly Dense Mixed-Grained Reconfigurable Architecture
With Overlay Via-Switch Crossbars},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {12},
pages = {2723--2736},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2018.2812914},
doi = {10.1109/TVLSI.2018.2812914},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OchiYFHKHIDTSTW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/HiratsukaTTFMNO18,
author = {Akitaka Hiratsuka and
Akira Tsuchiya and
Kenji Tanaka and
Hiroyuki Fukuyama and
Naoki Miura and
Hideyuki Nosaka and
Hidetoshi Onodera},
title = {A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance
Amplifier with Inductor-Less Bandwidth Compensation},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
Taiwan, November 5-7, 2018},
pages = {69--72},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASSCC.2018.8579296},
doi = {10.1109/ASSCC.2018.8579296},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/HiratsukaTTFMNO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/IslamO18,
author = {A. K. M. Mahfuzul Islam and
Hidetoshi Onodera},
editor = {Iris Bahar},
title = {PVT\({}^{\mbox{2}}\): process, voltage, temperature and time-dependent
variability in scaled {CMOS} process},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {126},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3243491},
doi = {10.1145/3240765.3243491},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/IslamO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icrc/EgawaIOSKNTN18,
author = {Takumi Egawa and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Shota Kita and
Kengo Nozaki and
Kenta Takata and
Masaya Notomi},
title = {Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using
Integrated Nanophotonics},
booktitle = {2018 {IEEE} International Conference on Rebooting Computing, {ICRC}
2018, McLean, VA, USA, November 7-9, 2018},
pages = {1--8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICRC.2018.8638607},
doi = {10.1109/ICRC.2018.8638607},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icrc/EgawaIOSKNTN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icrc/ShiomiIOSN18,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera and
Akihiko Shinya and
Masaya Notomi},
title = {An Integrated Optical Parallel Multiplier Exploiting Approximate Binary
Logarithms Towards Light Speed Data Processing},
booktitle = {2018 {IEEE} International Conference on Rebooting Computing, {ICRC}
2018, McLean, VA, USA, November 7-9, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICRC.2018.8638614},
doi = {10.1109/ICRC.2018.8638614},
timestamp = {Mon, 18 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icrc/ShiomiIOSN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/OkamuraIO18,
author = {Yosuke Okamura and
Tohru Ishihara and
Hidetoshi Onodera},
editor = {Dimitris Gizopoulos and
Dan Alexandrescu and
Mihalis Maniatakos and
Panagiota Papavramidou},
title = {Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation},
booktitle = {24th {IEEE} International Symposium on On-Line Testing And Robust
System Design, {IOLTS} 2018, Platja D'Aro, Spain, July 2-4, 2018},
pages = {177--182},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IOLTS.2018.8474128},
doi = {10.1109/IOLTS.2018.8474128},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iolts/OkamuraIO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/NishizawaO18,
author = {Shinichi Nishizawa and
Hidetoshi Onodera},
title = {Process variation aware D-Flip-Flop design using regression analysis},
booktitle = {19th International Symposium on Quality Electronic Design, {ISQED}
2018, Santa Clara, CA, USA, March 13-14, 2018},
pages = {88--93},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISQED.2018.8357270},
doi = {10.1109/ISQED.2018.8357270},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/NishizawaO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/InoueNTKO18,
author = {Toshiyuki Inoue and
Ryosuke Noguchi and
Akira Tsuchiya and
Keiji Kishine and
Hidetoshi Onodera},
title = {Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with
Active-Shunt-Feedback in 65-nm {CMOS} Technology},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {751--754},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8623912},
doi = {10.1109/MWSCAS.2018.8623912},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/InoueNTKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/IslamO18,
author = {A. K. M. Mahfuzul Islam and
Hidetoshi Onodera},
title = {Worst-Case Performance Analysis Under Random Telegraph Noise Induced
Threshold Voltage Variability},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {140--146},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464147},
doi = {10.1109/PATMOS.2018.8464147},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/IslamO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/XuSIO18,
author = {Hongjie Xu and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory
Structure},
booktitle = {28th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2018, Platja d'Aro, Spain, July 2-4, 2018},
pages = {237--242},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PATMOS.2018.8464141},
doi = {10.1109/PATMOS.2018.8464141},
timestamp = {Tue, 18 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/XuSIO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/HiguchiIO18,
author = {Tatsuhiro Higuchi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Performance Modeling of VIA-Switch {FPGA} for Device-Circuit-Architecture
Co-Optimization},
booktitle = {31st {IEEE} International System-on-Chip Conference, {SOCC} 2018,
Arlington, VA, USA, September 4-7, 2018},
pages = {112--117},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SOCC.2018.8618503},
doi = {10.1109/SOCC.2018.8618503},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/HiguchiIO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ShiomiIO17,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {A Necessary and Sufficient Condition of Supply and Threshold Voltages
in {CMOS} Circuits for Minimum Energy Point Operation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {100-A},
number = {12},
pages = {2764--2775},
year = {2017},
url = {https://doi.org/10.1587/transfun.E100.A.2764},
doi = {10.1587/TRANSFUN.E100.A.2764},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ShiomiIO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HokimotoIO17,
author = {Shu Hokimoto and
Tohru Ishihara and
Hidetoshi Onodera},
title = {A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage
Scaling and Adaptive Body Biasing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {100-A},
number = {12},
pages = {2776--2784},
year = {2017},
url = {https://doi.org/10.1587/transfun.E100.A.2776},
doi = {10.1587/TRANSFUN.E100.A.2776},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HokimotoIO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/HiratsukaTO17,
author = {Akitaka Hiratsuka and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance
amplifier for optical communication},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {795--798},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8053043},
doi = {10.1109/MWSCAS.2017.8053043},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/HiratsukaTO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MahfuzulO17,
author = {Islam A. K. M. Mahfuzul and
Hidetoshi Onodera},
title = {Effect of supply voltage on random telegraph noise of transistors
under switching condition},
booktitle = {27th International Symposium on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2017, Thessaloniki, Greece, September 25-27,
2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/PATMOS.2017.8106992},
doi = {10.1109/PATMOS.2017.8106992},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/MahfuzulO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/SuNWSLO17,
author = {Hong{-}Yan Su and
Shinichi Nishizawa and
Yan{-}Shiun Wu and
Jun Shiomi and
Yih{-}Lang Li and
Hidetoshi Onodera},
editor = {Massimo Alioto and
Hai Helen Li and
J{\"{u}}rgen Becker and
Ulf Schlichtmann and
Ramalingam Sridhar},
title = {Pin accessibility evaluating model for improving routability of {VLSI}
designs},
booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017,
Munich, Germany, September 5-8, 2017},
pages = {56--61},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/SOCC.2017.8226007},
doi = {10.1109/SOCC.2017.8226007},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/SuNWSLO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/KishimotoIO17,
author = {Tadashi Kishimoto and
Tohru Ishihara and
Hidetoshi Onodera},
title = {On-chip temperature and process variation sensing using a reconfigurable
Ring Oscillator},
booktitle = {2017 International Symposium on {VLSI} Design, Automation and Test,
{VLSI-DAT} 2017, Hsinchu, Taiwan, April 24-27, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-DAT.2017.7939649},
doi = {10.1109/VLSI-DAT.2017.7939649},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/KishimotoIO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Onodera16,
author = {Hidetoshi Onodera},
title = {2016 {ASP-DAC}},
journal = {{IEEE} Des. Test},
volume = {33},
number = {3},
pages = {133--134},
year = {2016},
url = {https://doi.org/10.1109/MDAT.2016.2536654},
doi = {10.1109/MDAT.2016.2536654},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/Onodera16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KamakariSIO16,
author = {Tatsuya Kamakari and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Analytical Stability Modeling for {CMOS} Latches in Low Voltage Operation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {99-A},
number = {12},
pages = {2463--2472},
year = {2016},
url = {https://doi.org/10.1587/transfun.E99.A.2463},
doi = {10.1587/TRANSFUN.E99.A.2463},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KamakariSIO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MahfuzulO16,
author = {Islam A. K. M. Mahfuzul and
Hidetoshi Onodera},
title = {On-chip monitoring and compensation scheme with fine-grain body biasing
for robust and energy-efficient operations},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {403--409},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428045},
doi = {10.1109/ASPDAC.2016.7428045},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MahfuzulO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KamakariSIO16,
author = {Tatsuya Kamakari and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {A closed-form stability model for cross-coupled inverters operating
in sub-threshold voltage region},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {691--696},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428092},
doi = {10.1109/ASPDAC.2016.7428092},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KamakariSIO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/HotateKHODTSWOM16,
author = {Junshi Hotate and
Takashi Kishimoto and
Toshiki Higashi and
Hiroyuki Ochi and
Ryutaro Doi and
Munehiro Tada and
Tadahiko Sugibayashi and
Kazutoshi Wakabayashi and
Hidetoshi Onodera and
Yukio Mitsuyama and
Masanori Hashimoto},
editor = {Paolo Ienne and
Walid A. Najjar and
Jason Helge Anderson and
Philip Brisk and
Walter Stechele},
title = {A highly-dense mixed grained reconfigurable architecture with overlay
crossbar interconnect using via-switch},
booktitle = {26th International Conference on Field Programmable Logic and Applications,
{FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPL.2016.7577337},
doi = {10.1109/FPL.2016.7577337},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/HotateKHODTSWOM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ShiomiIO16,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Variability- and correlation-aware logical effort for near-threshold
circuit design},
booktitle = {17th International Symposium on Quality Electronic Design, {ISQED}
2016, Santa Clara, CA, USA, March 15-16, 2016},
pages = {18--23},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISQED.2016.7479150},
doi = {10.1109/ISQED.2016.7479150},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ShiomiIO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ShiomiIO16,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Fully digital on-chip memory using minimum height standard cells for
near-threshold voltage computing},
booktitle = {26th International Workshop on Power and Timing Modeling, Optimization
and Simulation, {PATMOS} 2016, Bremen, Germany, September 21-23, 2016},
pages = {44--49},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/PATMOS.2016.7833424},
doi = {10.1109/PATMOS.2016.7833424},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ShiomiIO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/HokimotoIO16,
author = {Shu Hokimoto and
Tohru Ishihara and
Hidetoshi Onodera},
editor = {Karan S. Bhatia and
Massimo Alioto and
Danella Zhao and
Andrew Marshall and
Ramalingam Sridhar},
title = {Minimum energy point tracking using combined dynamic voltage scaling
and adaptive body biasing},
booktitle = {29th {IEEE} International System-on-Chip Conference, {SOCC} 2016,
Seattle, WA, USA, September 6-9, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SOCC.2016.7905420},
doi = {10.1109/SOCC.2016.7905420},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/HokimotoIO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/FurutaKO15,
author = {Jun Furuta and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Impact of Cell Distance and Well-contact Density on Neutron-induced
Multiple Cell Upsets},
journal = {{IEICE} Trans. Electron.},
volume = {98-C},
number = {4},
pages = {298--303},
year = {2015},
url = {https://doi.org/10.1587/transele.E98.C.298},
doi = {10.1587/TRANSELE.E98.C.298},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/FurutaKO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KamaeTO15,
author = {Norihiro Kamae and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {A Forward/Reverse Body Bias Generator with Wide Supply-Range down
to Threshold Voltage},
journal = {{IEICE} Trans. Electron.},
volume = {98-C},
number = {6},
pages = {504--511},
year = {2015},
url = {https://doi.org/10.1587/transele.E98.C.504},
doi = {10.1587/TRANSELE.E98.C.504},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KamaeTO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ShiomiIO15,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Statistical Timing Modeling Based on a Lognormal Distribution Model
for Near-Threshold Circuit Optimization},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {98-A},
number = {7},
pages = {1455--1466},
year = {2015},
url = {https://doi.org/10.1587/transfun.E98.A.1455},
doi = {10.1587/TRANSFUN.E98.A.1455},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ShiomiIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NishizawaIO15,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Layout Generator with Flexible Grid Assignment for Area Efficient
Standard Cell},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {131--135},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.131},
doi = {10.2197/IPSJTSLDM.8.131},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NishizawaIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MahfuzulSIO15,
author = {Islam A. K. M. Mahfuzul and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip
Process and Temperature Monitoring},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {11},
pages = {2475--2490},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2461598},
doi = {10.1109/JSSC.2015.2461598},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/MahfuzulSIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KishineIINTKO15,
author = {Keiji Kishine and
Hiromi Inaba and
Hiroshi Inoue and
Makoto Nakamura and
Akira Tsuchiya and
Hiroaki Katsurai and
Hidetoshi Onodera},
title = {A Multi-Rate Burst-Mode {CDR} Using a {GVCO} With Symmetric Loops
for Instantaneous Phase Locking in 65-nm {CMOS}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {62-I},
number = {5},
pages = {1288--1295},
year = {2015},
url = {https://doi.org/10.1109/TCSI.2015.2416812},
doi = {10.1109/TCSI.2015.2416812},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KishineIINTKO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HashimotoAKMSKK15,
author = {Masanori Hashimoto and
Dawood Alnajiar and
Hiroaki Konoura and
Yukio Mitsuyama and
Hajime Shimada and
Kazutoshi Kobayashi and
Hiroyuki Kanbara and
Hiroyuki Ochi and
Takashi Imagawa and
Kazutoshi Wakabayashi and
Takao Onoye and
Hidetoshi Onodera},
title = {Reliability-configurable mixed-grained reconfigurable array compatible
with high-level synthesis},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {14--15},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7058923},
doi = {10.1109/ASPDAC.2015.7058923},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HashimotoAKMSKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShiomiIO15,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Microarchitectural-level statistical timing models for near-threshold
circuit design},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {87--93},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7058986},
doi = {10.1109/ASPDAC.2015.7058986},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ShiomiIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/NakanoNNTOK15,
author = {Shinsuke Nakano and
Masafumi Nogawa and
Hideyuki Nosaka and
Akira Tsuchiya and
Hidetoshi Onodera and
Shunji Kimura},
title = {A 25-Gb/s 480-mW {CMOS} modulator driver using area-efficient 3D inductor
peaking},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2015, Xia'men,
China, November 9-11, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASSCC.2015.7387470},
doi = {10.1109/ASSCC.2015.7387470},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/NakanoNNTOK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/GuO15,
author = {Chenjie Gu and
Hidetoshi Onodera},
title = {Session 23 - Modeling emerging devices},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338475},
doi = {10.1109/CICC.2015.7338475},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/GuO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ShiomiIO15,
author = {Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {An energy-efficient on-chip memory structure for variability-aware
near-threshold operation},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {23--28},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085372},
doi = {10.1109/ISQED.2015.7085372},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ShiomiIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KamaeMTIO15,
author = {Norihiro Kamae and
Islam A. K. M. Mahfuzul and
Akira Tsuchiya and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Energy reduction by built-in body biasing with single supply voltage
operation},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {181--185},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085421},
doi = {10.1109/ISQED.2015.7085421},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KamaeMTIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/NishizawaIO15,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
title = {An impact of process variation on supply voltage dependence of logic
path delay variation},
booktitle = {{VLSI} Design, Automation and Test, {VLSI-DAT} 2015, Hsinchu, Taiwan,
April 27-29, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-DAT.2015.7114534},
doi = {10.1109/VLSI-DAT.2015.7114534},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/NishizawaIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KamaeTO14,
author = {Norihiro Kamae and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {A Body Bias Generator with Low Supply Voltage for Within-Die Variability
Compensation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {97-A},
number = {3},
pages = {734--740},
year = {2014},
url = {https://doi.org/10.1587/transfun.E97.A.734},
doi = {10.1587/TRANSFUN.E97.A.734},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KamaeTO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KimTO14,
author = {SinNyoung Kim and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {97-A},
number = {3},
pages = {768--776},
year = {2014},
url = {https://doi.org/10.1587/transfun.E97.A.768},
doi = {10.1587/TRANSFUN.E97.A.768},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KimTO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KimTO14a,
author = {SinNyoung Kim and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Radiation-Hardened {PLL} with a Switchable Dual Modular Redundancy
Structure},
journal = {{IEICE} Trans. Electron.},
volume = {97-C},
number = {4},
pages = {325--331},
year = {2014},
url = {https://doi.org/10.1587/transele.E97.C.325},
doi = {10.1587/TRANSELE.E97.C.325},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KimTO14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KonouraAMSKKOIW14,
author = {Hiroaki Konoura and
Dawood Alnajiar and
Yukio Mitsuyama and
Hajime Shimada and
Kazutoshi Kobayashi and
Hiroyuki Kanbara and
Hiroyuki Ochi and
Takashi Imagawa and
Kazutoshi Wakabayashi and
Masanori Hashimoto and
Takao Onoye and
Hidetoshi Onodera},
title = {Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting
C-Based Design and Its Irradiation Testing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {97-A},
number = {12},
pages = {2518--2529},
year = {2014},
url = {https://doi.org/10.1587/transfun.E97.A.2518},
doi = {10.1587/TRANSFUN.E97.A.2518},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KonouraAMSKKOIW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/DasO14,
author = {Bishnu Prasad Das and
Hidetoshi Onodera},
title = {On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring
Oscillator},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {61-II},
number = {3},
pages = {183--187},
year = {2014},
url = {https://doi.org/10.1109/TCSII.2013.2296118},
doi = {10.1109/TCSII.2013.2296118},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/DasO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DasO14,
author = {Bishnu Prasad Das and
Hidetoshi Onodera},
title = {Frequency-Independent Warning Detection Sequential for Dynamic Voltage
and Frequency Scaling in ASICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {12},
pages = {2535--2548},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2296033},
doi = {10.1109/TVLSI.2013.2296033},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DasO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/MahfuzulSIO14,
author = {Islam A. K. M. Mahfuzul and
Jun Shiomi and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Wide-supply-range all-digital leakage variation sensor for on-chip
process and temperature monitoring},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {45--48},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008856},
doi = {10.1109/ASSCC.2014.7008856},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/MahfuzulSIO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/KamaeMTO14,
author = {Norihiro Kamae and
Islam A. K. M. Mahfuzul and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {A body bias generator with wide supply-range down to threshold voltage
for within-die variability compensation},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {53--56},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008858},
doi = {10.1109/ASSCC.2014.7008858},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/KamaeMTO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/MitsuyamaO14,
author = {Yukio Mitsuyama and
Hidetoshi Onodera},
title = {Variability and Soft-Error Resilience in Dependable {VLSI} Platform},
booktitle = {23rd {IEEE} Asian Test Symposium, {ATS} 2014, Hangzhou, China, November
16-19, 2014},
pages = {45--50},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ATS.2014.20},
doi = {10.1109/ATS.2014.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/MitsuyamaO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/MatsumotoKO14,
author = {Takashi Matsumoto and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Impact of random telegraph noise on {CMOS} logic circuit reliability},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6945997},
doi = {10.1109/CICC.2014.6945997},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/MatsumotoKO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/McAndrewO14,
author = {Colin McAndrew and
Hidetoshi Onodera},
title = {Modeling of advanced devices},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6946119},
doi = {10.1109/CICC.2014.6946119},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/McAndrewO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KishineIINTOK14,
author = {Keiji Kishine and
Hiroshi Inoue and
Hiromi Inaba and
Makoto Nakamura and
Akira Tsuchiya and
Hidetoshi Onodera and
Hiroaki Katsurai},
title = {A 65-nm {CMOS} burst-mode {CDR} based on a {GVCO} with symmetric loops},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {2704--2707},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865731},
doi = {10.1109/ISCAS.2014.6865731},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KishineIINTOK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/FujitaKO14,
author = {Tomohiro Fujita and
SinNyoung Kim and
Hidetoshi Onodera},
title = {Computer simulation of radiation-induced clock-perturbation in phase-locked
loop with analog behavioral model},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
2014, Santa Clara, CA, USA, March 3-5, 2014},
pages = {230--235},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISQED.2014.6783330},
doi = {10.1109/ISQED.2014.6783330},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/FujitaKO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/KamakariNIO14,
author = {Tatsuya Kamakari and
Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
editor = {Kaijian Shi and
Thomas B{\"{u}}chner and
Danella Zhao and
Ramalingam Sridhar},
title = {Variation-aware Flip-Flop energy optimization for ultra low voltage
operation},
booktitle = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
Las Vegas, NV, USA, September 2-5, 2014},
pages = {17--22},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/SOCC.2014.6948893},
doi = {10.1109/SOCC.2014.6948893},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/KamakariNIO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/NishizawaIO14,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
editor = {Kaijian Shi and
Thomas B{\"{u}}chner and
Danella Zhao and
Ramalingam Sridhar},
title = {Design methodology of process variation tolerant D-Flip-Flops for
low voltage circuit operation},
booktitle = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
Las Vegas, NV, USA, September 2-5, 2014},
pages = {42--47},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/SOCC.2014.6948897},
doi = {10.1109/SOCC.2014.6948897},
timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/NishizawaIO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/MahfuzulO14,
author = {Islam A. K. M. Mahfuzul and
Hidetoshi Onodera},
title = {Characterization and compensation of performance variability using
on-chip monitors},
booktitle = {Technical Papers of 2014 International Symposium on {VLSI} Design,
Automation and Test, {VLSI-DAT} 2014, Hsinchu, Taiwan, April 28-30,
2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-DAT.2014.6834934},
doi = {10.1109/VLSI-DAT.2014.6834934},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi-dat/MahfuzulO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhangFYKO13,
author = {Kuiyuan Zhang and
Jun Furuta and
Ryosuke Yamamoto and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset
by Utilizing the Parasitic Bipolar Effect},
journal = {{IEICE} Trans. Electron.},
volume = {96-C},
number = {4},
pages = {511--517},
year = {2013},
url = {https://doi.org/10.1587/transele.E96.C.511},
doi = {10.1587/TRANSELE.E96.C.511},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhangFYKO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MahfuzulO13,
author = {Islam A. K. M. Mahfuzul and
Hidetoshi Onodera},
title = {On-Chip Detection of Process Shift and Process Spread for Post-Silicon
Diagnosis and Model-Hardware Correlation},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {9},
pages = {1971--1979},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1971},
doi = {10.1587/TRANSINF.E96.D.1971},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/MahfuzulO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NishizawaIO13,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Standard Cell Structure with Flexible {P/N} Well Boundaries for Near-Threshold
Voltage Operation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2499--2507},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2499},
doi = {10.1587/TRANSFUN.E96.A.2499},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/NishizawaIO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KubokiOTKO13,
author = {Takeshi Kuboki and
Yusuke Ohtomo and
Akira Tsuchiya and
Keiji Kishine and
Hidetoshi Onodera},
title = {A 25-Gb/s {LD} driver with area-effective inductor in a 0.18-{\(\mathrm{\mu}\)}m
{CMOS}},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {105--106},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509578},
doi = {10.1109/ASPDAC.2013.6509578},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KubokiOTKO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Onodera13,
author = {Hidetoshi Onodera},
title = {Dependable {VLSI} Platform using Robust Fabrics},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {119--124},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509583},
doi = {10.1109/ASPDAC.2013.6509583},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/Onodera13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/OnoderaC13,
author = {Hidetoshi Onodera and
Yu Kevin Cao},
title = {{AMS} verification in advanced technologies},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658571},
doi = {10.1109/CICC.2013.6658571},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/OnoderaC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/KimTO13,
author = {SinNyoung Kim and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Perturbation-immune radiation-hardened {PLL} with a switchable {DMR}
structure},
booktitle = {2013 {IEEE} 19th International On-Line Testing Symposium (IOLTS),
Chania, Crete, Greece, July 8-10, 2013},
pages = {128--132},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IOLTS.2013.6604063},
doi = {10.1109/IOLTS.2013.6604063},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iolts/KimTO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/NishizawaIO13,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Analysis and comparison of {XOR} cell structures for low voltage circuit
design},
booktitle = {International Symposium on Quality Electronic Design, {ISQED} 2013,
Santa Clara, CA, USA, March 4-6, 2013},
pages = {703--708},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISQED.2013.6523687},
doi = {10.1109/ISQED.2013.6523687},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/NishizawaIO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KubokiOTKO12,
author = {Takeshi Kuboki and
Yusuke Ohtomo and
Akira Tsuchiya and
Keiji Kishine and
Hidetoshi Onodera},
title = {Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed
Laser-Diode Driver for Optical Communication System},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {95-A},
number = {2},
pages = {479--486},
year = {2012},
url = {https://doi.org/10.1587/transfun.E95.A.479},
doi = {10.1587/TRANSFUN.E95.A.479},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KubokiOTKO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/DasO12,
author = {Bishnu Prasad Das and
Hidetoshi Onodera},
title = {Area-efficient reconfigurable-array-based oscillator for standard
cell characterisation},
journal = {{IET} Circuits Devices Syst.},
volume = {6},
number = {6},
pages = {429--436},
year = {2012},
url = {https://doi.org/10.1049/iet-cds.2012.0012},
doi = {10.1049/IET-CDS.2012.0012},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/DasO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KubokiOTKO12,
author = {Takeshi Kuboki and
Yusuke Ohtomo and
Akira Tsuchiya and
Keiji Kishine and
Hidetoshi Onodera},
title = {A 16Gb/s area-efficient {LD} driver with interwoven inductor in a
0.18{\(\mathrm{\mu}\)}m {CMOS}},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {561--562},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165018},
doi = {10.1109/ASPDAC.2012.6165018},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KubokiOTKO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/MahfuzulO12,
author = {Islam A. K. M. Mahfuzul and
Hidetoshi Onodera},
title = {On-Chip Detection of Process Shift and Process Spread for Silicon
Debugging and Model-Hardware Correlation},
booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November
19-22, 2012},
pages = {350--354},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ATS.2012.66},
doi = {10.1109/ATS.2012.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/MahfuzulO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/McConaghyO12,
author = {Trent McConaghy and
Hidetoshi Onodera},
title = {Modeling {\&} design for variability and reliability},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--2},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330569},
doi = {10.1109/CICC.2012.6330569},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/McConaghyO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/NishizawaIO12,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
title = {A flexible structure of standard cell and its optimization method
for near-threshold voltage operation},
booktitle = {30th International {IEEE} Conference on Computer Design, {ICCD} 2012,
Montreal, QC, Canada, September 30 - Oct. 3, 2012},
pages = {235--240},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ICCD.2012.6378646},
doi = {10.1109/ICCD.2012.6378646},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/NishizawaIO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KondoNIO12,
author = {Masahiro Kondo and
Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
editor = {Jos{\'{e}} L. Ayala and
Delong Shang and
Alex Yakovlev},
title = {A Standard Cell Optimization Method for Near-Threshold Voltage Operations},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 22nd International Workshop, {PATMOS} 2012, Newcastle
upon Tyne, UK, September 4-6, 2012, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7606},
pages = {32--41},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-36157-9\_4},
doi = {10.1007/978-3-642-36157-9\_4},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KondoNIO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HamanakaYFKKO11,
author = {Chikara Hamanaka and
Ryosuke Yamamoto and
Jun Furuta and
Kanto Kubota and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy
Flip-Flop Measured by Shift-Register-Based Monitor Structures},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {94-A},
number = {12},
pages = {2669--2675},
year = {2011},
url = {https://doi.org/10.1587/transfun.E94.A.2669},
doi = {10.1587/TRANSFUN.E94.A.2669},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HamanakaYFKKO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera11,
author = {Hidetoshi Onodera},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {1},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.1},
doi = {10.2197/IPSJTSLDM.4.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FurutaHKO11,
author = {Jun Furuta and
Chikara Hamanaka and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {A 65nm flip-flop array to measure soft error resiliency against high-energy
neutron and alpha particles},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {83--84},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722306},
doi = {10.1109/ASPDAC.2011.5722306},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/FurutaHKO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/FurutaYKO11,
author = {Jun Furuta and
Ryosuke Yamamoto and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Correlations between well potential and SEUs measured by well-potential
perturbation detectors in 65nm},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {209--212},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123639},
doi = {10.1109/ASSCC.2011.6123639},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/FurutaYKO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/KamaeTO11,
author = {Norihiro Kamae and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {An area effective forward/reverse body bias generator for within-die
variability compensation},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {217--220},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123641},
doi = {10.1109/ASSCC.2011.6123641},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/KamaeTO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Onodera11,
author = {Hidetoshi Onodera},
title = {Dependable {VLSI} Program in Japan: Program Overview and the Current
Status of Dependable {VLSI} Platform Project},
booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New
Delhi, India, November 20-23, 2011},
pages = {492--495},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ATS.2011.56},
doi = {10.1109/ATS.2011.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Onodera11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/TsuchiyaKOKMNO11,
author = {Akira Tsuchiya and
Takeshi Kuboki and
Yusuke Ohtomo and
Keiji Kishine and
Shigekazu Miyawaki and
Makoto Nakamura and
Hidetoshi Onodera},
title = {Bandwidth enhancement for high speed amplifier utilizing mutually
coupled on-chip inductors},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {36--39},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138640},
doi = {10.1109/ISOCC.2011.6138640},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/TsuchiyaKOKMNO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/MiyawakiNTKO11,
author = {Shigekazu Miyawaki and
Makoto Nakamura and
Akira Tsuchiya and
Keiji Kishine and
Hidetoshi Onodera},
title = {A 10.3Gbps translmpedance amplifier with mutually coupled inductors
in 0.18-{\(\mu\)}m {CMOS}},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {223--226},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138750},
doi = {10.1109/ISOCC.2011.6138750},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/MiyawakiNTKO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ItoMNSKO11,
author = {Kyosuke Ito and
Takashi Matsumoto and
Shinichi Nishizawa and
Hiroki Sunagawa and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Modeling of Random Telegraph Noise under circuit operation - Simulation
and measurement of RTN-induced delay fluctuation},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {22--27},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770698},
doi = {10.1109/ISQED.2011.5770698},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ItoMNSKO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/FurutaKO10,
author = {Jun Furuta and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {An Area/Delay Efficient Dual-Modular Flip-Flop with Higher {SEU/SET}
Immunity},
journal = {{IEICE} Trans. Electron.},
volume = {93-C},
number = {3},
pages = {340--346},
year = {2010},
url = {https://doi.org/10.1587/transele.E93.C.340},
doi = {10.1587/TRANSELE.E93.C.340},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/FurutaKO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera10,
author = {Hidetoshi Onodera},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {1},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.1},
doi = {10.2197/IPSJTSLDM.3.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SunagawaTTKO10,
author = {Hiroki Sunagawa and
Haruhiko Terada and
Akira Tsuchiya and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Effect of Regularity-Enhanced Layout on Variability and Circuit Performance
of Standard Cells},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {130--139},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.130},
doi = {10.2197/IPSJTSLDM.3.130},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SunagawaTTKO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KubokiOTKO10,
author = {Takeshi Kuboki and
Yusuke Ohtomo and
Akira Tsuchiya and
Keiji Kishine and
Hidetoshi Onodera},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-{\(\mathrm{\mu}\)}m
{CMOS}},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617416},
doi = {10.1109/CICC.2010.5617416},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KubokiOTKO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/DasO10,
author = {Bishnu Prasad Das and
Hidetoshi Onodera},
title = {Warning Prediction Sequential for Transient Error Prevention},
booktitle = {25th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} Systems, {DFT} 2010, Kyoto, Japan, October 6-8, 2010},
pages = {382--390},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DFT.2010.52},
doi = {10.1109/DFT.2010.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/DasO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/SunagawaO10,
author = {Hiroki Sunagawa and
Hidetoshi Onodera},
editor = {Thomas B{\"{u}}chner and
Ramalingam Sridhar and
Andrew Marshall and
Norbert Schuhmann},
title = {Variation-tolerant design of D-flipflops},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,
2010, Las Vegas, NV, USA, Proceedings},
pages = {147--151},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/SOCC.2010.5784732},
doi = {10.1109/SOCC.2010.5784732},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/SunagawaO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/KimTO10,
author = {SinNyoung Kim and
Akira Tsuchiya and
Hidetoshi Onodera},
editor = {Thomas B{\"{u}}chner and
Ramalingam Sridhar and
Andrew Marshall and
Norbert Schuhmann},
title = {A design procedure of predictive {RF} {MOSFET} model for compatibility
with {ITRS}},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,
2010, Las Vegas, NV, USA, Proceedings},
pages = {396--399},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/SOCC.2010.5784704},
doi = {10.1109/SOCC.2010.5784704},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/KimTO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/FukuokaTO09,
author = {Takayuki Fukuoka and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Statistical Gate Delay Model for Multiple Input Switching},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {92-A},
number = {12},
pages = {3070--3078},
year = {2009},
url = {https://doi.org/10.1587/transfun.E92.A.3070},
doi = {10.1587/TRANSFUN.E92.A.3070},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/FukuokaTO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera09,
author = {Hidetoshi Onodera},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {1},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.1},
doi = {10.2197/IPSJTSLDM.2.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SakaiOYH09,
author = {Shuichi Sakai and
Hidetoshi Onodera and
Hiroto Yasuura and
James C. Hoe},
editor = {Kazutoshi Wakabayashi},
title = {Dependable {VLSI:} device, design and architecture: how should they
cooperate?},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {859--860},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796588},
doi = {10.1109/ASPDAC.2009.4796588},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SakaiOYH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/GildenblatO09,
author = {Gennady Gildenblat and
Hidetoshi Onodera},
title = {Modeling of passive elements and reliability},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2009, San Jose,
California, USA, 13-16 September, 2009, Proceedings},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/CICC.2009.5280810},
doi = {10.1109/CICC.2009.5280810},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/GildenblatO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/SunagawaTTKO09,
author = {Hiroki Sunagawa and
Haruhiko Terada and
Akira Tsuchiya and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Erect of regularity-enhanced layout on printability and circuit performance
of standard cells},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {195--200},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810293},
doi = {10.1109/ISQED.2009.4810293},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/SunagawaTTKO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HashimotoYSO08,
author = {Masanori Hashimoto and
Junji Yamaguchi and
Takashi Sato and
Hidetoshi Onodera},
title = {Timing Analysis Considering Temporal Supply Voltage Fluctuation},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {91-D},
number = {3},
pages = {655--660},
year = {2008},
url = {https://doi.org/10.1093/ietisy/e91-d.3.655},
doi = {10.1093/IETISY/E91-D.3.655},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/HashimotoYSO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ShinoharaNO08,
author = {Hirofumi Shinohara and
Koji Nii and
Hidetoshi Onodera},
title = {Analytical Model of Static Noise Margin in {CMOS} {SRAM} for Variation
Consideration},
journal = {{IEICE} Trans. Electron.},
volume = {91-C},
number = {9},
pages = {1488--1500},
year = {2008},
url = {https://doi.org/10.1093/ietele/e91-c.9.1488},
doi = {10.1093/IETELE/E91-C.9.1488},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ShinoharaNO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera08,
author = {Hidetoshi Onodera},
title = {Welcome to {TSLDM} - {A} New Open-Access Online Journal from {IPSJ}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {1},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.1},
doi = {10.2197/IPSJTSLDM.1.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TeradaFTO08,
author = {Haruhiko Terada and
Takayuki Fukuoka and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Accurate Estimation of the Worst-case Delay in Statistical Static
Timing Analysis},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {116--125},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.116},
doi = {10.2197/IPSJTSLDM.1.116},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TeradaFTO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FukuokaTO08,
author = {Takayuki Fukuoka and
Akira Tsuchiya and
Hidetoshi Onodera},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Statistical gate delay model for Multiple Input Switching},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {286--291},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483959},
doi = {10.1109/ASPDAC.2008.4483959},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/FukuokaTO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KobayashiO08,
author = {Kazutoshi Kobayashi and
Hidetoshi Onodera},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Best ways to use billions of devices on a chip - Error predictive,
defect tolerant and error recovery designs},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {811--812},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484065},
doi = {10.1109/ASPDAC.2008.4484065},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KobayashiO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/OnoderaV08,
author = {Hidetoshi Onodera and
Hong{-}Ha Vuong},
title = {Session 2 - Statistical modeling},
booktitle = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference,
{CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September
21-24, 2008},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/CICC.2008.4672004},
doi = {10.1109/CICC.2008.4672004},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/OnoderaV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SugiharaKKO08,
author = {Yuuri Sugihara and
Yohei Kume and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
editor = {Mike Hutton and
Paul Chow},
title = {Speed and yield enhancement by track swapping on critical paths utilizing
random variations for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {257},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344711},
doi = {10.1145/1344671.1344711},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SugiharaKKO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KobayashiKNSO08,
author = {Kazutoshi Kobayashi and
Yohei Kume and
Cam Lai Ngo and
Yuuri Sugihara and
Hidetoshi Onodera},
title = {A variation-aware constant-order optimization scheme utilizing delay
detectors to search for fastest paths on {FPGAS}},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {107--112},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4629916},
doi = {10.1109/FPL.2008.4629916},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KobayashiKNSO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/SugiharaKKO08,
author = {Yuuri Sugihara and
Yohei Kume and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Performance optimization by track swapping on critical paths utilizing
random variations for {FPGAS}},
booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and
Applications, Heidelberg, Germany, 8-10 September 2008},
pages = {503--506},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPL.2008.4629994},
doi = {10.1109/FPL.2008.4629994},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/SugiharaKKO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KatsukiKKO07,
author = {Kazuya Katsuki and
Manabu Kotani and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {A 90 nm {LUT} Array for Speed and Yield Enhancement by Utilizing Within-Die
Delay Variations},
journal = {{IEICE} Trans. Electron.},
volume = {90-C},
number = {4},
pages = {699--707},
year = {2007},
url = {https://doi.org/10.1093/ietele/e90-c.4.699},
doi = {10.1093/IETELE/E90-C.4.699},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KatsukiKKO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsuchiyaHO07,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling},
journal = {{IEICE} Trans. Electron.},
volume = {90-C},
number = {6},
pages = {1267--1273},
year = {2007},
url = {https://doi.org/10.1093/ietele/e90-c.6.1267},
doi = {10.1093/IETELE/E90-C.6.1267},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TsuchiyaHO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KubokiTO07,
author = {Takeshi Kuboki and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Low-Power Design of {CML} Driver for On-Chip Transmission-Lines Using
Impedance-Unmatched Driver},
journal = {{IEICE} Trans. Electron.},
volume = {90-C},
number = {6},
pages = {1274--1281},
year = {2007},
url = {https://doi.org/10.1093/ietele/e90-c.6.1274},
doi = {10.1093/IETELE/E90-C.6.1274},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KubokiTO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KobayashiKKSKO07,
author = {Kazutoshi Kobayashi and
Kazuya Katsuki and
Manabu Kotani and
Yuuri Sugihara and
Yohei Kume and
Hidetoshi Onodera},
title = {A 90 nm 48 x 48 LUT-Based {FPGA} Enhancing Speed and Yield Utilizing
Within-Die Delay Variations},
journal = {{IEICE} Trans. Electron.},
volume = {90-C},
number = {10},
pages = {1919--1926},
year = {2007},
url = {https://doi.org/10.1093/ietele/e90-c.10.1919},
doi = {10.1093/IETELE/E90-C.10.1919},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KobayashiKKSKO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HashimotoYO07,
author = {Masanori Hashimoto and
Junji Yamaguchi and
Hidetoshi Onodera},
title = {Timing Analysis Considering Spatial Power/Ground Level Variation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {90-A},
number = {12},
pages = {2661--2668},
year = {2007},
url = {https://doi.org/10.1093/ietfec/e90-a.12.2661},
doi = {10.1093/IETFEC/E90-A.12.2661},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/HashimotoYO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MutaO07,
author = {Hirokazu Muta and
Hidetoshi Onodera},
title = {Manufacturability-Aware Design of Standard Cells},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {90-A},
number = {12},
pages = {2682--2690},
year = {2007},
url = {https://doi.org/10.1093/ietfec/e90-a.12.2682},
doi = {10.1093/IETFEC/E90-A.12.2682},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/MutaO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KubokiTO07,
author = {Takeshi Kuboki and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched
{CML} Driver in 90nm {CMOS} Technology},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {120--121},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357970},
doi = {10.1109/ASPDAC.2007.357970},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KubokiTO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SugiharaKKKO07,
author = {Yuuri Sugihara and
Manabu Kotani and
Kazuya Katsuki and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {A 90nm 8{\texttimes}16 {FPGA} Enhancing Speed and Yield Utilizing
Within-Die Variations},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {122--123},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357971},
doi = {10.1109/ASPDAC.2007.357971},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SugiharaKKKO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/FukuokaTO07,
author = {Takayuki Fukuoka and
Akira Tsuchiya and
Hidetoshi Onodera},
editor = {Patrick H. Madden and
David Z. Pan},
title = {Worst-case delay analysis considering the variability of transistors
and interconnects},
booktitle = {Proceedings of the 2007 International Symposium on Physical Design,
{ISPD} 2007, Austin, Texas, USA, March 18-21, 2007},
pages = {35--42},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231996.1232006},
doi = {10.1145/1231996.1232006},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/FukuokaTO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YuyamaTKO06,
author = {Yoichi Yuyama and
Akira Tsuchiya and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Alternate Self-Shielding for High-Speed and Reliable On-Chip Global
Interconnect},
journal = {{IEICE} Trans. Electron.},
volume = {89-C},
number = {3},
pages = {327--333},
year = {2006},
url = {https://doi.org/10.1093/ietele/e89-c.3.327},
doi = {10.1093/IETELE/E89-C.3.327},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/YuyamaTKO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Onodera06a,
author = {Hidetoshi Onodera},
title = {Variability: Modeling and Its Impact on Design},
journal = {{IEICE} Trans. Electron.},
volume = {89-C},
number = {3},
pages = {342--348},
year = {2006},
url = {https://doi.org/10.1093/ietele/e89-c.3.342},
doi = {10.1093/IETELE/E89-C.3.342},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Onodera06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KobayashiHO06,
author = {Kazutoshi Kobayashi and
Akihiko Higuchi and
Hidetoshi Onodera},
title = {A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors
in the Deep Submicron Era},
journal = {{IEICE} Trans. Electron.},
volume = {89-C},
number = {6},
pages = {838--843},
year = {2006},
url = {https://doi.org/10.1093/ietele/e89-c.6.838},
doi = {10.1093/IETELE/E89-C.6.838},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KobayashiHO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Onodera06,
author = {Hidetoshi Onodera},
title = {Special Section on {VLSI} Design and {CAD} Algorithms},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {89-A},
number = {12},
pages = {3377},
year = {2006},
url = {https://doi.org/10.1093/ietfec/e89-a.12.3377},
doi = {10.1093/IETFEC/E89-A.12.3377},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Onodera06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KanamotoITOH06,
author = {Toshiki Kanamoto and
Tatsuhiko Ikeda and
Akira Tsuchiya and
Hidetoshi Onodera and
Masanori Hashimoto},
title = {Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance
and Inductance Extraction in SoC Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {89-A},
number = {12},
pages = {3560--3568},
year = {2006},
url = {https://doi.org/10.1093/ietfec/e89-a.12.3560},
doi = {10.1093/IETFEC/E89-A.12.3560},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/KanamotoITOH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsuchiyaHO06,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Interconnect {RL} Extraction Based on Transfer Characteristics of
Transmission-Line},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {89-A},
number = {12},
pages = {3585--3593},
year = {2006},
url = {https://doi.org/10.1093/ietfec/e89-a.12.3585},
doi = {10.1093/IETFEC/E89-A.12.3585},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/TsuchiyaHO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KatsukiKKO06,
author = {Kazuya Katsuki and
Manabu Kotani and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
editor = {Fumiyasu Hirose},
title = {Measurement results of within-die variations on a 90nm {LUT} array
for speed and yield enhancement of reconfigurable devices},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {110--111},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594661},
doi = {10.1109/ASPDAC.2006.1594661},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KatsukiKKO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TsuchiyaHO06,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Fumiyasu Hirose},
title = {Interconnect {RL} extraction at a single representative frequency},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {515--520},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594737},
doi = {10.1109/ASPDAC.2006.1594737},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/TsuchiyaHO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KobayashiKKTOSO06,
author = {Kazutoshi Kobayashi and
Manabu Kotani and
Kazuya Katsuki and
Y. Takatsukasa and
K. Ogata and
Yuuri Sugihara and
Hidetoshi Onodera},
title = {A Yield and Speed Enhancement Technique Using Reconfigurable Devices
Against Within-Die Variations on the Nanometer Regime},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--4},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311276},
doi = {10.1109/FPL.2006.311276},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/KobayashiKKTOSO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/KounoO06,
author = {Takeshi Kouno and
Hidetoshi Onodera},
title = {Consideration of Transition-Time Variability in Statistical Timing
Analysis},
booktitle = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
24-27, 2006},
pages = {207--210},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SOCC.2006.283882},
doi = {10.1109/SOCC.2006.283882},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/KounoO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/YamaokaO06,
author = {Masanao Yamaoka and
Hidetoshi Onodera},
title = {A Detailed Vth-Variation Analysis for Sub-100-nm Embedded {SRAM} Design},
booktitle = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
24-27, 2006},
pages = {315--318},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SOCC.2006.283905},
doi = {10.1109/SOCC.2006.283905},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/YamaokaO06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MiyazakiHO05,
author = {Takahito Miyazaki and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {A Performance Prediction of Clock Generation PLLs: {A} Ring Oscillator
Based {PLL} and an {LC} Oscillator Based {PLL}},
journal = {{IEICE} Trans. Electron.},
volume = {88-C},
number = {3},
pages = {437--444},
year = {2005},
url = {https://doi.org/10.1093/ietele/e88-c.3.437},
doi = {10.1093/IETELE/E88-C.3.437},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/MiyazakiHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KobayashiAO05,
author = {Kazutoshi Kobayashi and
Masao Aramoto and
Hidetoshi Onodera},
title = {A Resource-Shared {VLIW} Processor for Low-Power On-Chip Multiprocessing
in the Nanometer Era},
journal = {{IEICE} Trans. Electron.},
volume = {88-C},
number = {4},
pages = {552--558},
year = {2005},
url = {https://doi.org/10.1093/ietele/e88-c.4.552},
doi = {10.1093/IETELE/E88-C.4.552},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KobayashiAO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TsuchiyaHO05,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Performance Limitation of On-Chip Global Interconnects for High-Speed
Signaling},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {4},
pages = {885--891},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.4.885},
doi = {10.1093/IETFEC/E88-A.4.885},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/TsuchiyaHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HashimotoYO05,
author = {Masanori Hashimoto and
Tomonori Yamamoto and
Hidetoshi Onodera},
title = {Statistical Analysis of Clock Skew Variation in H-Tree Structure},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3375--3381},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3375},
doi = {10.1093/IETFEC/E88-A.12.3375},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/HashimotoYO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/SatoHO05,
author = {Takashi Sato and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Successive Pad Assignment for Minimizing Supply Voltage Drop},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3429--3436},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3429},
doi = {10.1093/IETFEC/E88-A.12.3429},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/SatoHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MuramatsuHO05,
author = {Atsushi Muramatsu and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Effects of On-Chip Inductance on Power Distribution Grid},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3564--3572},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3564},
doi = {10.1093/IETFEC/E88-A.12.3564},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/MuramatsuHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShinmyoHO05,
author = {Akinori Shinmyo and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Tingao Tang},
title = {Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18{\(\mathrm{\mu}\)}m
{CMOS} process},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {9--10},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120890},
doi = {10.1145/1120725.1120890},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ShinmyoHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KobayashiAYHO05,
author = {Kazutoshi Kobayashi and
Masao Aramoto and
Yoichi Yuyama and
Akihiko Higuchi and
Hidetoshi Onodera},
editor = {Tingao Tang},
title = {A resource-shared {VLIW} processor architecture for area-efficient
on-chip multiprocessing},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {619--622},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120977},
doi = {10.1145/1120725.1120977},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KobayashiAYHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SatoHO05,
author = {Takashi Sato and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Tingao Tang},
title = {Successive pad assignment algorithm to optimize number and location
of power supply pad using incremental matrix inversion},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {723--728},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1121003},
doi = {10.1145/1120725.1121003},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SatoHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TsuchiyaHO05,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Tingao Tang},
title = {Return path selection for loop {RL} extraction},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {1078--1081},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120828},
doi = {10.1145/1120725.1120828},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/TsuchiyaHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HashimotoYSO05,
author = {Masanori Hashimoto and
Junji Yamaguchi and
Takashi Sato and
Hidetoshi Onodera},
editor = {Tingao Tang},
title = {Timing analysis considering temporal supply voltage fluctuation},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {1098--1101},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120833},
doi = {10.1145/1120725.1120833},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HashimotoYSO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/RochelO05,
author = {Steffen Rochel and
Hidetoshi Onodera},
title = {Substrate and phase noise characterization},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {448--449},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568704},
doi = {10.1109/CICC.2005.1568704},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/RochelO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KatsukiKKO05,
author = {Kazuya Katsuki and
Manabu Kotani and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {A yield and speed enhancement scheme under within-die variations on
90nm {LUT} array},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {601--604},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568739},
doi = {10.1109/CICC.2005.1568739},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KatsukiKKO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/TsuchiyaHO05,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Design guideline for resistive termination of on-chip high-speed interconnects},
booktitle = {Proceedings of the {IEEE} 2005 Custom Integrated Circuits Conference,
{CICC} 2005, DoubleTree Hotel, San Jose, California, USA, September
18-21, 2005},
pages = {613--616},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/CICC.2005.1568742},
doi = {10.1109/CICC.2005.1568742},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/TsuchiyaHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/MuramatsuHO05,
author = {Atsushi Muramatsu and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Patrick Groeneveld and
Louis Scheffer},
title = {Effects of on-chip inductance on power distribution grid},
booktitle = {Proceedings of the 2005 International Symposium on Physical Design,
{ISPD} 2005, San Francisco, California, USA, April 3-6, 2005},
pages = {63--69},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1055137.1055152},
doi = {10.1145/1055137.1055152},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/MuramatsuHO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/HashimotoYO05,
author = {Masanori Hashimoto and
Tomonori Yamamoto and
Hidetoshi Onodera},
title = {Statistical Analysis of Clock Skew Variation in H-Tree Structure},
booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED}
2005), 21-23 March 2005, San Jose, CA, {USA}},
pages = {402--407},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISQED.2005.114},
doi = {10.1109/ISQED.2005.114},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/HashimotoYO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KobayashiO04,
author = {Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {A Comprehensive Simulation and Test Environment for Prototype {VLSI}
Verification},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {87-D},
number = {3},
pages = {630--636},
year = {2004},
url = {http://search.ieice.org/bin/summary.php?id=e87-d\_3\_630},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KobayashiO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HashimotoYO04,
author = {Masanori Hashimoto and
Yuji Yamada and
Hidetoshi Onodera},
title = {Equivalent waveform propagation for static timing analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {4},
pages = {498--508},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.825858},
doi = {10.1109/TCAD.2004.825858},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HashimotoYO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MiyazakiHO04,
author = {Takahito Miyazaki and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Masaharu Imai},
title = {A performance comparison of PLLs for clock generation using ring oscillator
{VCO} and {LC} oscillator in a digital {CMOS} process},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {545--546},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.28},
doi = {10.1109/ASPDAC.2004.28},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MiyazakiHO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TsuchiyaHO04,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Masaharu Imai},
title = {Representative frequency for interconnect R(f)L(f)C extraction},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {691--696},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.174},
doi = {10.1109/ASPDAC.2004.174},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/TsuchiyaHO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YuyamaAKO04,
author = {Yoichi Yuyama and
Masao Aramoto and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
editor = {Masaharu Imai},
title = {An SoC architecture and its design methodology using unifunctional
heterogeneous processor array},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {737--742},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.48},
doi = {10.1109/ASPDAC.2004.48},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YuyamaAKO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/TsuchiyaGHO04,
author = {Akira Tsuchiya and
Yuuya Gotoh and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Performance limitation of on-chip global interconnects for high-speed
signaling},
booktitle = {Proceedings of the {IEEE} 2004 Custom Integrated Circuits Conference,
{CICC} 2004, Orlando, FL, USA, October 2004},
pages = {489--492},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/CICC.2004.1358864},
doi = {10.1109/CICC.2004.1358864},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/TsuchiyaGHO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HashimotoYO04,
author = {Masanori Hashimoto and
Junji Yamaguchi and
Hidetoshi Onodera},
title = {Timing analysis considering spatial power/ground level variation},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {814--820},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382687},
doi = {10.1109/ICCAD.2004.1382687},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HashimotoYO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/OkadaHO04,
author = {Ken{-}ichi Okada and
Hiroaki Hoshino and
Hidetoshi Onodera},
title = {Modelling and optimization of on-chip spiral inductor in S-parameter
domain},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {153--156},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/OkadaHO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YuyamaAKO04,
author = {Yoichi Yuyama and
Masao Aramoto and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {{RTL/ISS} co-modeling methodology for embedded processor using SystemC},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {305--308},
publisher = {{IEEE}},
year = {2004},
timestamp = {Fri, 20 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/YuyamaAKO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/HashimotoFO04,
author = {Masanori Hashimoto and
Kazunori Fujimori and
Hidetoshi Onodera},
title = {Automatic Generation of Standard Cell Library in {VDSM} Technologies},
booktitle = {5th International Symposium on Quality of Electronic Design {(ISQED}
2004), 22-24 March 2004, San Jose, CA, {USA}},
pages = {36--41},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISQED.2004.1283647},
doi = {10.1109/ISQED.2004.1283647},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/HashimotoFO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/OkadaO03,
author = {Kenichi Okada and
Hidetoshi Onodera},
title = {Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip
Variabilities with the Size Dependence},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {4},
pages = {746--751},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_4\_746},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/OkadaO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/OkadaYO03,
author = {Kenichi Okada and
Kento Yamaoka and
Hidetoshi Onodera},
title = {Statistical Gate-Delay Modeling with Intra-Gate Variability},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {12},
pages = {2914--2922},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_12\_2914},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/OkadaYO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/TsuchiyaHO03,
author = {Akira Tsuchiya and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Representative Frequency for Interconnect R(f)L(f)C Extraction},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {12},
pages = {2942--2951},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_12\_2942},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/TsuchiyaHO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/HashimotoTO03,
author = {Masanori Hashimoto and
Masao Takahashi and
Hidetoshi Onodera},
title = {Crosstalk Noise Estimation for Generic {RC} Trees},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {12},
pages = {2965--2973},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_12\_2965},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/HashimotoTO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/HashimotoHO03,
author = {Masanori Hashimoto and
Yoshiteru Hayashi and
Hidetoshi Onodera},
title = {Experimental Study on Cell-Base High-Performance Datapath Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {86-A},
number = {12},
pages = {3204--3207},
year = {2003},
url = {http://search.ieice.org/bin/summary.php?id=e86-a\_12\_3204},
timestamp = {Tue, 08 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/HashimotoHO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/OkadaYO03,
author = {Ken{-}ichi Okada and
Kento Yamaoka and
Hidetoshi Onodera},
editor = {Hiroto Yasuura},
title = {A statistical gate delay model for intra-chip and inter-chip variabilities},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {31--36},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119779},
doi = {10.1145/1119772.1119779},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/OkadaYO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HashimotoFO03,
author = {Masanori Hashimoto and
Kazunori Fujimori and
Hidetoshi Onodera},
editor = {Hiroto Yasuura},
title = {Standard cell libraries with various driving strength cells for 0.13,
0.18 and 0.35 {\(\mu\)}m technologies},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {589--590},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119905},
doi = {10.1145/1119772.1119905},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HashimotoFO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HashimotoYO03,
author = {Masanori Hashimoto and
Yuji Yamada and
Hidetoshi Onodera},
title = {Equivalent Waveform Propagation for Static Timing Analysis},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {169--175},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.org/10.1109/ICCAD.2003.1257627},
doi = {10.1109/ICCAD.2003.1257627},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HashimotoYO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/OkadaYO03,
author = {Ken{-}ichi Okada and
Kento Yamaoka and
Hidetoshi Onodera},
title = {A Statistical Gate-Delay Model Considering Intra-Gate Variability},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {908--913},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257915},
doi = {10.1109/ICCAD.2003.1257915},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/OkadaYO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/OkadaYO03,
author = {Ken{-}ichi Okada and
Kento Yamaoka and
Hidetoshi Onodera},
title = {Statistical modeling of gate-delay variation with consideration of
intra-gate variability},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {513--516},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206335},
doi = {10.1109/ISCAS.2003.1206335},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/OkadaYO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/HashimotoYO03,
author = {Masanori Hashimoto and
Yuji Yamada and
Hidetoshi Onodera},
editor = {Massoud Pedram and
Charles J. Alpert},
title = {Capturing crosstalk-induced waveform for accurate static timing analysis},
booktitle = {Proceedings of the 2003 International Symposium on Physical Design,
{ISPD} 2003, Monterey, CA, USA, April 6-9, 2003},
pages = {18--23},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/640000.640008},
doi = {10.1145/640000.640008},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/HashimotoYO03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/HashimotoO02,
author = {Masanori Hashimoto and
Hidetoshi Onodera},
title = {Increase in Delay Uncertainty by Performance Optimization},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {85-A},
number = {12},
pages = {2799--2802},
year = {2002},
url = {http://search.ieice.org/bin/summary.php?id=e85-a\_12\_2799},
timestamp = {Wed, 09 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/HashimotoO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KobayashiYO02,
author = {Kazutoshi Kobayashi and
Junji Yamaguchi and
Hidetoshi Onodera},
title = {Measurement results of on-chip IR-drop},
booktitle = {Proceedings of the {IEEE} 2002 Custom Integrated Circuits Conference,
{CICC} 2002, Orlando, FL, USA, May 12-15, 2002},
pages = {521--524},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/CICC.2002.1012897},
doi = {10.1109/CICC.2002.1012897},
timestamp = {Tue, 04 Oct 2022 22:39:17 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KobayashiYO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/HashimotoTO02,
author = {Masanori Hashimoto and
Masao Takahashi and
Hidetoshi Onodera},
editor = {Sachin S. Sapatnekar and
Massoud Pedram},
title = {Crosstalk noise optimization by post-layout transistor sizing},
booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD}
2002, Del Mar, CA, USA, April 7-10, 2002},
pages = {126--130},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505388.505420},
doi = {10.1145/505388.505420},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/HashimotoTO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/HashimotoHO02,
author = {Masanori Hashimoto and
Yashiteru Hayashi and
Hidetoshi Onodera},
title = {Experimental Study on Cell-Base High-Performance Datapath Design},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {283--287},
year = {2002},
timestamp = {Sun, 04 Aug 2019 18:01:44 +0200},
biburl = {https://dblp.org/rec/conf/iwls/HashimotoHO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KobayashiEISLTO01,
author = {Kazutoshi Kobayashi and
Makoto Eguchi and
Takuya Iwahashi and
Takehide Shibayama and
Xiang Li and
Kousuke Takai and
Hidetoshi Onodera},
editor = {Satoshi Goto},
title = {A vector-pipeline {DSP} for low-rate videophones},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {1--2},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370184},
doi = {10.1145/370155.370184},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KobayashiEISLTO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/OnoderaKDNKTH01,
author = {Hidetoshi Onodera and
Andrew B. Kahng and
Wayne Wei{-}Ming Dai and
Sani R. Nassif and
Juho Kim and
Akira Tanabe and
Toshihiro Hattori},
editor = {Satoshi Goto},
title = {Beyond the red brick wall (panel): challenges and solutions in 50nm
physical design},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {267--268},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370344},
doi = {10.1145/370155.370344},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/OnoderaKDNKTH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YasudaFO01,
author = {Takeo Yasuda and
Hiroaki Fujita and
Hidetoshi Onodera},
editor = {Satoshi Goto},
title = {A dynamically phase adjusting {PLL} with a variable delay},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {275--280},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370348},
doi = {10.1145/370155.370348},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YasudaFO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HashimotoO01,
author = {Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Satoshi Goto},
title = {Post-layout transistor sizing for power reduction in cell-based design},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {359--365},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370392},
doi = {10.1145/370155.370392},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HashimotoO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/TakahashiHO01,
author = {Masao Takahashi and
Masanori Hashimoto and
Hidetoshi Onodera},
title = {Crosstalk Noise Estimation for Generic {RC} Trees},
booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
Proceedings},
pages = {110--117},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCD.2001.955012},
doi = {10.1109/ICCD.2001.955012},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/TakahashiHO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KobayashiO01,
author = {Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {{ST:} {PERL} package for simulation and test environment},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {89--92},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.921992},
doi = {10.1109/ISCAS.2001.921992},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KobayashiO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FujitaOFOT00,
author = {Tomohiro Fujita and
Ken{-}ichi Okada and
Hiroaki Fujita and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {A method for linking process-level variability to system performances},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {547--552},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368785},
doi = {10.1145/368434.368785},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/FujitaOFOT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/OkadaO00,
author = {Kenichi Okada and
Hidetoshi Onodera},
title = {Statistical modeling of device characteristics with systematic fluctuation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {437--440},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.856358},
doi = {10.1109/ISCAS.2000.856358},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/OkadaO00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FujitaO00,
author = {Tomohiro Fujita and
Hidetoshi Onodera},
title = {Statistical delay calculation with vector synthesis model},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {473--476},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.857474},
doi = {10.1109/ISCAS.2000.857474},
timestamp = {Sun, 22 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/FujitaO00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/HashimotoO00,
author = {Masanori Hashimoto and
Hidetoshi Onodera},
editor = {Manfred Wiesel and
Dwight D. Hill},
title = {A performance optimization method by gate sizing using statistical
static timing analysis},
booktitle = {Proceedings of the 2000 International Symposium on Physical Design,
{ISPD} 2000, San Diego, CA, USA, April 9-12, 2000},
pages = {111--116},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/332357.332385},
doi = {10.1145/332357.332385},
timestamp = {Thu, 26 Aug 2021 17:11:38 +0200},
biburl = {https://dblp.org/rec/conf/ispd/HashimotoO00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HashimotoOT99,
author = {Masanori Hashimoto and
Hidetoshi Onodera and
Keikichi Tamaru},
editor = {Mary Jane Irwin},
title = {A Practical Gate Resizing Technique Considering Glitch Reduction for
Low Power Design},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {446--451},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309977},
doi = {10.1145/309847.309977},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HashimotoOT99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KondoOT98,
author = {Masaki Kondo and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {Model-adaptable {MOSFET} parameter-extraction method using an intermediate
model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {400--405},
year = {1998},
url = {https://doi.org/10.1109/43.703924},
doi = {10.1109/43.703924},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KondoOT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HirataOT98,
author = {Akio Hirata and
Hidetoshi Onodera and
Keikichi Tamaru},
editor = {Hiroto Yasuura},
title = {Proposal of a timing model for {CMOS} logic gates driving a {CRC}
load},
booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
pages = {537--544},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/288548.289083},
doi = {10.1145/288548.289083},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HirataOT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/HashimotoOT98,
author = {Masanori Hashimoto and
Hidetoshi Onodera and
Keikichi Tamaru},
editor = {Anantha P. Chandrakasan and
Sayfe Kiaei},
title = {A power optimization method considering glitch reduction by gate sizing},
booktitle = {Proceedings of the 1998 International Symposium on Low Power Electronics
and Design, 1998, Monterey, California, USA, August 10-12, 1998},
pages = {221--226},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/280756.280907},
doi = {10.1145/280756.280907},
timestamp = {Mon, 27 Sep 2021 11:47:11 +0200},
biburl = {https://dblp.org/rec/conf/islped/HashimotoOT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KobayashiKTOT97,
author = {Kazutoshi Kobayashi and
Masayoshi Kinoshita and
Masahiro Takeuchi and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {A functional memory type parallel processor for vector quantization},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {665--666},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600354},
doi = {10.1109/ASPDAC.1997.600354},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KobayashiKTOT97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KondoOT97,
author = {Masaki Kondo and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {A current mode cyclic {A/D} converter with a 0.8 {\(\mu\)}m {CMOS}
process},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {683--684},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600363},
doi = {10.1109/ASPDAC.1997.600363},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KondoOT97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChenOT96,
author = {Guangqiu Chen and
Hidetoshi Onodera and
Keikichi Tamaru},
title = {Timing and Power Optimization by Gate Sizing Considering False Paths},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {154},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497612},
doi = {10.1109/GLSV.1996.497612},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChenOT96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KondoOT95,
author = {Masaki Kondo and
Hidetoshi Onodera and
Keikichi Tamaru},
editor = {Isao Shirakawa},
title = {A model-adaptable {MOSFET} parameter extraction system},
booktitle = {Proceedings of the 1995 Conference on Asia Pacific Design Automation,
Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/224818.224926},
doi = {10.1145/224818.224926},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KondoOT95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenOT95,
author = {Guangqiu Chen and
Hidetoshi Onodera and
Keikichi Tamaru},
editor = {Richard L. Rudell},
title = {An iterative gate sizing approach with accurate delay evaluation},
booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
pages = {422--427},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1995},
url = {https://doi.org/10.1109/ICCAD.1995.480150},
doi = {10.1109/ICCAD.1995.480150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ChenOT95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MoshnyagaMOT93,
author = {Vasily G. Moshnyaga and
Hiroshi Mori and
Hidetoshi Onodera and
Keikichi Tamaru},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {Layout-driven module selection for register-transfer synthesis of
sub-micron ASIC's},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {100--103},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580038},
doi = {10.1109/ICCAD.1993.580038},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MoshnyagaMOT93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/OnoderaTT91,
author = {Hidetoshi Onodera and
Yo Taniguchi and
Keikichi Tamaru},
editor = {A. Richard Newton},
title = {Branch-and-Bound Placement for Building Block Layout},
booktitle = {Proceedings of the 28th Design Automation Conference, San Francisco,
California, USA, June 17-21, 1991},
pages = {433--439},
publisher = {{ACM}},
year = {1991},
url = {https://doi.org/10.1145/127601.127708},
doi = {10.1145/127601.127708},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/OnoderaTT91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/OkudaSOT89,
author = {R. Okuda and
Takashi Sato and
Hidetoshi Onodera and
K. Tamariu},
title = {An efficient algorithm for layout compaction problem with symmetry
constraints},
booktitle = {1989 {IEEE} International Conference on Computer-Aided Design, {ICCAD}
1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical
Papers},
pages = {148--151},
publisher = {{IEEE} Computer Society},
year = {1989},
url = {https://doi.org/10.1109/ICCAD.1989.76924},
doi = {10.1109/ICCAD.1989.76924},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/OkudaSOT89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/TamaruO87,
author = {Keikichi Tamaru and
Hidetoshi Onodera},
title = {System design of a special-purpose computer for {LSI} design rule
checking},
journal = {Syst. Comput. Jpn.},
volume = {18},
number = {2},
pages = {43--54},
year = {1987},
url = {https://doi.org/10.1002/scj.4690180205},
doi = {10.1002/SCJ.4690180205},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/TamaruO87.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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