BibTeX records: Vijaypal Singh Rathor

download as .bib file

@article{DBLP:journals/et/RathorGS18,
  author    = {Vijaypal Singh Rathor and
               Bharat Garg and
               G. K. Sharma},
  title     = {New Lightweight Architectures for Secure {FSM} Design to Thwart Fault
               Injection and Trojan Attacks},
  journal   = {J. Electronic Testing},
  volume    = {34},
  number    = {6},
  pages     = {697--708},
  year      = {2018},
  url       = {https://doi.org/10.1007/s10836-018-5762-5},
  doi       = {10.1007/s10836-018-5762-5},
  timestamp = {Wed, 17 Jul 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/et/RathorGS18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/RathorGS18,
  author    = {Vijaypal Singh Rathor and
               Bharat Garg and
               G. K. Sharma},
  title     = {An Energy-Efficient Trusted {FSM} Design Technique to Thwart Fault
               Injection and Trojan Attacks},
  booktitle = {31st International Conference on {VLSI} Design and 17th International
               Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
               6-10, 2018},
  pages     = {73--78},
  year      = {2018},
  crossref  = {DBLP:conf/vlsid/2018},
  url       = {https://doi.org/10.1109/VLSID.2018.40},
  doi       = {10.1109/VLSID.2018.40},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/RathorGS18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/RathorGS17,
  author    = {Vijaypal Singh Rathor and
               Bharat Garg and
               G. K. Sharma},
  title     = {New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy
               Designs},
  journal   = {J. Electronic Testing},
  volume    = {33},
  number    = {5},
  pages     = {657--668},
  year      = {2017},
  url       = {https://doi.org/10.1007/s10836-017-5683-8},
  doi       = {10.1007/s10836-017-5683-8},
  timestamp = {Wed, 17 Jul 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/et/RathorGS17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsid/2018,
  title     = {31st International Conference on {VLSI} Design and 17th International
               Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
               6-10, 2018},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8326586/proceeding},
  isbn      = {978-1-5386-3692-3},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of Schloss Dagstuhl - Leibniz Center for Informatics