BibTeX records: Yasuhisa Shimazaki

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Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
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@inproceedings{DBLP:conf/isscc/ShimadaSFMDKHS23,
  author       = {Kenichi Shimada and
                  Keiichiro Sano and
                  Kazuki Fukuoka and
                  Hiroshi Morita and
                  Masayuki Daito and
                  Tatsuya Kamei and
                  Hiroyuki Hamasaki and
                  Yasuhisa Shimazaki},
  title        = {A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving
                  10Gbps/W Network Routing, 40ms {CAN} Bus Start-Up and 1.4mW Standby
                  Power},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
                  San Francisco, CA, USA, February 19-23, 2023},
  pages        = {240--241},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/ISSCC42615.2023.10067585},
  doi          = {10.1109/ISSCC42615.2023.10067585},
  timestamp    = {Wed, 29 Mar 2023 15:53:39 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ShimadaSFMDKHS23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KondoSIUHSOOSOM20,
  author       = {Hiroyuki Kondo and
                  Yasuhisa Shimazaki and
                  Masao Ito and
                  Minoru Uemura and
                  Toshihiro Hattori and
                  Noriaki Sakamoto and
                  Sugako Otani and
                  Norimasa Otsuki and
                  Yasufumi Suzuki and
                  Naoto Okumura and
                  Shohei Maeda and
                  Tomonori Yanagita and
                  Takao Koike and
                  Kosuke Yayama},
  title        = {A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted
                  Processor Supporting {ISO26262} {ASIL} {D}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {55},
  number       = {1},
  pages        = {133--144},
  year         = {2020},
  url          = {https://doi.org/10.1109/JSSC.2019.2953826},
  doi          = {10.1109/JSSC.2019.2953826},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KondoSIUHSOOSOM20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/OtaniOSOMYKSIUH19,
  author       = {Sugako Otani and
                  Norimasa Otsuki and
                  Yasufumi Suzuki and
                  Naoto Okumura and
                  Shohei Maeda and
                  Tomonori Yanagita and
                  Takao Koike and
                  Yasuhisa Shimazaki and
                  Masao Ito and
                  Minoru Uemura and
                  Toshihiro Hattori and
                  Tadaaki Yamauchi and
                  Hiroyuki Kondo},
  title        = {A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted
                  Processor for Next-Generation Automotive Architecture Complying with
                  {ISO26262} {ASIL-D}},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
                  San Francisco, CA, USA, February 17-21, 2019},
  pages        = {54--56},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ISSCC.2019.8662300},
  doi          = {10.1109/ISSCC.2019.8662300},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/OtaniOSOMYKSIUH19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShibaharaTFKIHS17,
  author       = {Shinichi Shibahara and
                  Chikafumi Takahashi and
                  Kazuki Fukuoka and
                  Yuko Kitaji and
                  Takahiro Irita and
                  Hirotaka Hara and
                  Yasuhisa Shimazaki and
                  Jun Matsushima},
  title        = {A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting {ISO26262} {ASIL}
                  {B} Standard},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {52},
  number       = {1},
  pages        = {77--88},
  year         = {2017},
  url          = {https://doi.org/10.1109/JSSC.2016.2623682},
  doi          = {10.1109/JSSC.2016.2623682},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShibaharaTFKIHS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KimuraNWHKUTOIS17,
  author       = {Hayato Kimura and
                  Hideyuki Noda and
                  Hisaaki Watanabe and
                  Takashi Higuchi and
                  Ryosaku Kobayashi and
                  Masayuki Utsuno and
                  Fumitake Takami and
                  Sugako Otani and
                  Masayuki Ito and
                  Yasuhisa Shimazaki and
                  Naoki Yada and
                  Hiroyuki Kondo},
  title        = {3.5 {A} 40nm flash microcontroller with 0.80{\(\mathrm{\mu}\)}s field-oriented-control
                  intelligent motor timer and functional safety system for next-generation
                  {EV/HEV}},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {58--59},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870259},
  doi          = {10.1109/ISSCC.2017.7870259},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KimuraNWHKUTOIS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ShimazakiMB17,
  author       = {Yasuhisa Shimazaki and
                  John Maneatis and
                  Edith Beign{\'{e}}},
  title        = {Session 8 overview: Digital PLLs and security circuits},
  booktitle    = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2017, San Francisco, CA, USA, February 5-9, 2017},
  pages        = {140--141},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISSCC.2017.7870300},
  doi          = {10.1109/ISSCC.2017.7870300},
  timestamp    = {Wed, 17 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ShimazakiMB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/TakahashiSFMKSH16,
  author       = {Chikafumi Takahashi and
                  Shinichi Shibahara and
                  Kazuki Fukuoka and
                  Jun Matsushima and
                  Yuko Kitaji and
                  Yasuhisa Shimazaki and
                  Hirotaka Hara and
                  Takahiro Irita},
  title        = {4.5 {A} 16nm FinFET heterogeneous nona-core SoC complying with {ISO26262}
                  {ASIL-B:} Achieving 10-7 random hardware failures per hour reliability},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {80--81},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417916},
  doi          = {10.1109/ISSCC.2016.7417916},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/TakahashiSFMKSH16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/MaedaKMTTNS13,
  author       = {Noriaki Maeda and
                  Shigenobu Komatsu and
                  Masao Morimoto and
                  Koji Tanaka and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Yasuhisa Shimazaki},
  title        = {A 0.41 {\(\mathrm{\mu}\)}A Standby Leakage 32 kb Embedded {SRAM} with
                  Low-Voltage Resume-Standby Utilizing All Digital Current Comparator
                  in 28 nm {HKMG} {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {48},
  number       = {4},
  pages        = {917--923},
  year         = {2013},
  url          = {https://doi.org/10.1109/JSSC.2012.2237571},
  doi          = {10.1109/JSSC.2012.2237571},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MaedaKMTTNS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/coolchips/ShimazakiMK12,
  author       = {Yasuhisa Shimazaki and
                  Noriyuki Miura and
                  Tadahiro Kuroda},
  editor       = {Hiroaki Kobayashi and
                  Makoto Ikeda and
                  Fumio Arakawa},
  title        = {A 5.184Gbps/ch through-chip interface and automated place-and-route
                  design methodology for 3-D integration of 45nm {CMOS} processors},
  booktitle    = {2012 {IEEE} Symposium on Low-Power and High-Speed Chips, {COOL} Chips
                  XV, Yokohama, Japan, April 18-20, 2012},
  pages        = {1--3},
  publisher    = {{IEEE} Computer Society},
  year         = {2012},
  url          = {https://doi.org/10.1109/COOLChips.2012.6216583},
  doi          = {10.1109/COOLCHIPS.2012.6216583},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/coolchips/ShimazakiMK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/IshiiTNFYTTS12,
  author       = {Yuichiro Ishii and
                  Yasumasa Tsukamoto and
                  Koji Nii and
                  Hidehiro Fujiwara and
                  Makoto Yabuuchi and
                  Koji Tanaka and
                  Shinji Tanaka and
                  Yasuhisa Shimazaki},
  title        = {A 28nm 360ps-access-time two-port {SRAM} with a time-sharing scheme
                  to circumvent read disturbs},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {236--238},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176991},
  doi          = {10.1109/ISSCC.2012.6176991},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/IshiiTNFYTTS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/MaedaKMS12,
  author       = {Noriaki Maeda and
                  Shigenobu Komatsu and
                  Masao Morimoto and
                  Yasuhisa Shimazaki},
  title        = {A 0.41{\(\mathrm{\mu}\)}A standby leakage 32Kb embedded {SRAM} with
                  Low-Voltage resume-standby utilizing all digital current comparator
                  in 28nm {HKMG} {CMOS}},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
                  13-15, 2012},
  pages        = {58--59},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/VLSIC.2012.6243788},
  doi          = {10.1109/VLSIC.2012.6243788},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/MaedaKMS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/SaenOONSSKKNIHHK10,
  author       = {Makoto Saen and
                  Kenichi Osada and
                  Yasuyuki Okuma and
                  Kiichi Niitsu and
                  Yasuhisa Shimazaki and
                  Yasufumi Sugimori and
                  Yoshinori Kohama and
                  Kazutaka Kasuga and
                  Itaru Nonomura and
                  Naohiko Irie and
                  Toshihiro Hattori and
                  Atsushi Hasegawa and
                  Tadahiro Kuroda},
  title        = {3-D System Integration of Processor and Multi-Stacked SRAMs Using
                  Inductive-Coupling Link},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {4},
  pages        = {856--862},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2010.2040310},
  doi          = {10.1109/JSSC.2010.2040310},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/SaenOONSSKKNIHHK10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/KomatsuYMMSO09,
  author       = {Shigenobu Komatsu and
                  Masanao Yamaoka and
                  Masao Morimoto and
                  Noriaki Maeda and
                  Yasuhisa Shimazaki and
                  Kenichi Osada},
  title        = {A 40-nm low-power {SRAM} with multi-stage replica-bitline technique
                  for reducing timing variation},
  booktitle    = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2009, San Jose,
                  California, USA, 13-16 September, 2009, Proceedings},
  pages        = {701--704},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/CICC.2009.5280731},
  doi          = {10.1109/CICC.2009.5280731},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/KomatsuYMMSO09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/NiitsuSSKKNSKOIHHK09,
  author       = {Kiichi Niitsu and
                  Yasuhisa Shimazaki and
                  Yasufumi Sugimori and
                  Yoshinori Kohama and
                  Kazutaka Kasuga and
                  Itaru Nonomura and
                  Makoto Saen and
                  Shigenobu Komatsu and
                  Kenichi Osada and
                  Naohiko Irie and
                  Toshihiro Hattori and
                  Atsushi Hasegawa and
                  Tadahiro Kuroda},
  title        = {An inductive-coupling link for 3D integration of a 90nm {CMOS} processor
                  and a 65nm {CMOS} {SRAM}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {480--481},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977517},
  doi          = {10.1109/ISSCC.2009.4977517},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/NiitsuSSKKNSKOIHHK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YamaokaMSO08,
  author       = {Masanao Yamaoka and
                  Noriaki Maeda and
                  Yasuhisa Shimazaki and
                  Kenichi Osada},
  title        = {65nm Low-Power High-Density {SRAM} Operable at 1.0V under 3{\(\sigma\)}
                  Systematic Variation Using Separate Vth Monitoring and Body Bias for
                  {NMOS} and {PMOS}},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {384--385},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523218},
  doi          = {10.1109/ISSCC.2008.4523218},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YamaokaMSO08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/KannoMYHSHMIYIH07,
  author       = {Yusuke Kanno and
                  Hiroyuki Mizuno and
                  Yoshihiko Yasu and
                  Kenji Hirose and
                  Yasuhisa Shimazaki and
                  Tadashi Hoshi and
                  Yujiro Miyairi and
                  Toshifumi Ishii and
                  Tetsuya Yamada and
                  Takahiro Irita and
                  Toshihiro Hattori and
                  Kazumasa Yanagisawa and
                  Naohiko Irie},
  title        = {Hierarchical Power Distribution With Power Tree in Dozens of Power
                  Domains for 90-nm Low-Power Multi-CPU SoCs},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {42},
  number       = {1},
  pages        = {74--83},
  year         = {2007},
  url          = {https://doi.org/10.1109/JSSC.2006.885057},
  doi          = {10.1109/JSSC.2006.885057},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KannoMYHSHMIYIH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/YamaokaMSSNSYK06,
  author       = {Masanao Yamaoka and
                  Noriaki Maeda and
                  Yoshihiro Shinozaki and
                  Yasuhisa Shimazaki and
                  Koji Nii and
                  Shigeru Shimada and
                  Kazumasa Yanagisawa and
                  Takayuki Kawahara},
  title        = {90-nm process-variation adaptive embedded {SRAM} modules with power-line-floating
                  write technique},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {41},
  number       = {3},
  pages        = {705--711},
  year         = {2006},
  url          = {https://doi.org/10.1109/JSSC.2006.869786},
  doi          = {10.1109/JSSC.2006.869786},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/YamaokaMSSNSYK06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dac/HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO06,
  author       = {Toshihiro Hattori and
                  Takahiro Irita and
                  Masayuki Ito and
                  Eiji Yamamoto and
                  Hisashi Kato and
                  Go Sado and
                  Tetsuhiro Yamada and
                  Kunihiko Nishiyama and
                  Hiroshi Yagi and
                  Takao Koike and
                  Yoshihiko Tsuchihashi and
                  Motoki Higashida and
                  Hiroyuki Asano and
                  Izumi Hayashibara and
                  Ken Tatezawa and
                  Yasuhisa Shimazaki and
                  Naozumi Morino and
                  Yoshihiko Yasu and
                  Tadashi Hoshi and
                  Yujiro Miyairi and
                  Kazumasa Yanagisawa and
                  Kenji Hirose and
                  Saneaki Tamaki and
                  Shinichi Yoshioka and
                  Toshifumi Ishii and
                  Yusuke Kanno and
                  Hiroyuki Mizuno and
                  Tetsuya Yamada and
                  Naohiko Irie and
                  Reiko Tsuchihashi and
                  Nobuto Arai and
                  Tomohiro Akiyama and
                  Koji Ohno},
  editor       = {Ellen Sentovich},
  title        = {Hierarchical power distribution and power management scheme for a
                  single chip mobile processor},
  booktitle    = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
                  San Francisco, CA, USA, July 24-28, 2006},
  pages        = {292--295},
  publisher    = {{ACM}},
  year         = {2006},
  url          = {https://doi.org/10.1145/1146909.1146986},
  doi          = {10.1145/1146909.1146986},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/KannoMYHSHMIYIH06,
  author       = {Yusuke Kanno and
                  Hiroyuki Mizuno and
                  Yoshihiko Yasu and
                  Kenji Hirose and
                  Yasuhisa Shimazaki and
                  Tadashi Hoshi and
                  Yujiro Miyairi and
                  Toshifumi Ishii and
                  Tetsuya Yamada and
                  Takahiro Irita and
                  Toshihiro Hattori and
                  Kazumasa Yanagisawa and
                  Naohiko Irie},
  title        = {Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power
                  Multi-CPU Processor},
  booktitle    = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
                  2006, Digest of Technical Papers, an Francisco, CA, USA, February
                  6-9, 2006},
  pages        = {2200--2209},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSCC.2006.1696281},
  doi          = {10.1109/ISSCC.2006.1696281},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/KannoMYHSHMIYIH06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/HattorilIYKSYNY06,
  author       = {Toshihiro Hattori and
                  Takahiro Irita and
                  Masayuki Ito and
                  Eiji Yamamoto and
                  Hisashi Kato and
                  Go Sado and
                  Tetsuhiro Yamada and
                  Kunihiko Nishiyama and
                  Hiroshi Yagi and
                  Takao Koike and
                  Yoshihiko Tsuchihashi and
                  Motoki Higashida and
                  Hiroyuki Asano and
                  Izumi Hayashibara and
                  Ken Tatezawa and
                  Yasuhisa Shimazaki and
                  Naozumi Morino and
                  Kenji Hirose and
                  Saneaki Tamaki and
                  Shinichi Yoshioka and
                  Reiko Tsuchihashi and
                  Nobuto Arai and
                  Tomohiro Akiyama and
                  Koji Ohno},
  title        = {A Power Management Scheme Controlling 20 Power Domains for a Single-Chip
                  Mobile Processor},
  booktitle    = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
                  2006, Digest of Technical Papers, an Francisco, CA, USA, February
                  6-9, 2006},
  pages        = {2210--2219},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSCC.2006.1696282},
  doi          = {10.1109/ISSCC.2006.1696282},
  timestamp    = {Thu, 14 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/HattorilIYKSYNY06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ieicet/IshikawaKKYSOTFHANHYH05,
  author       = {Makoto Ishikawa and
                  Tatsuya Kamei and
                  Yuki Kondo and
                  Masanao Yamaoka and
                  Yasuhisa Shimazaki and
                  Motokazu Ozawa and
                  Saneaki Tamaki and
                  Mikio Furuyama and
                  Tadashi Hoshi and
                  Fumio Arakawa and
                  Osamu Nishii and
                  Kenji Hirose and
                  Shinichi Yoshioka and
                  Toshihiro Hattori},
  title        = {A 4500 MIPS/W, 86 {\(\mathrm{\mu}\)}A Resume-Standby, 11 {\(\mathrm{\mu}\)}A
                  Ultra-Standby Application Processor for 3G Cellular Phones},
  journal      = {{IEICE} Trans. Electron.},
  volume       = {88-C},
  number       = {4},
  pages        = {528--535},
  year         = {2005},
  url          = {https://doi.org/10.1093/ietele/e88-c.4.528},
  doi          = {10.1093/IETELE/E88-C.4.528},
  timestamp    = {Sat, 11 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/IshikawaKKYSOTFHANHYH05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/YamaokaSMSKSYO05,
  author       = {Masanao Yamaoka and
                  Yoshihiro Shinozaki and
                  Noriaki Maeda and
                  Yasuhisa Shimazaki and
                  Kei Kato and
                  Shigeru Shimada and
                  Kazumasa Yanagisawa and
                  Kenichi Osada},
  title        = {A 300-MHz 25-{\(\mu\)}A/Mb-leakage on-chip {SRAM} module featuring
                  process-variation immunity and low-leakage-active mode for mobile-phone
                  application processor},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {40},
  number       = {1},
  pages        = {186--194},
  year         = {2005},
  url          = {https://doi.org/10.1109/JSSC.2004.838014},
  doi          = {10.1109/JSSC.2004.838014},
  timestamp    = {Mon, 14 Mar 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/YamaokaSMSKSYO05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShimazakiZN04,
  author       = {Yasuhisa Shimazaki and
                  Radu Zlatanovici and
                  Borivoje Nikolic},
  title        = {A shared-well dual-supply-voltage 64-bit {ALU}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {39},
  number       = {3},
  pages        = {494--500},
  year         = {2004},
  url          = {https://doi.org/10.1109/JSSC.2003.822775},
  doi          = {10.1109/JSSC.2003.822775},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShimazakiZN04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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