BibTeX records: Abhishek A. Sinkar

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@inproceedings{DBLP:conf/dac/MoghaddamGSPK16,
  author       = {Hadi Asghari Moghaddam and
                  Hamid Reza Ghasemi and
                  Abhishek Arvind Sinkar and
                  Indrani Paul and
                  Nam Sung Kim},
  title        = {VR-scale: runtime dynamic phase scaling of processor voltage regulators
                  for improving power efficiency},
  booktitle    = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
                  2016, Austin, TX, USA, June 5-9, 2016},
  pages        = {151:1--151:6},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2897937.2898109},
  doi          = {10.1145/2897937.2898109},
  timestamp    = {Tue, 06 Nov 2018 16:58:19 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/MoghaddamGSPK16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SinkarGSKK14,
  author       = {Abhishek A. Sinkar and
                  Hamid Reza Ghasemi and
                  Michael J. Schulte and
                  Ulya R. Karpuzcu and
                  Nam Sung Kim},
  title        = {Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance
                  Processors},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {22},
  number       = {4},
  pages        = {747--758},
  year         = {2014},
  url          = {https://doi.org/10.1109/TVLSI.2013.2257900},
  doi          = {10.1109/TVLSI.2013.2257900},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SinkarGSKK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/KimRSK14,
  author       = {Hoyoung Kim and
                  Soojung Ryu and
                  Abhishek A. Sinkar and
                  Nam Sung Kim},
  title        = {Quantitative comparison of the power reduction techniques for samsung
                  reconfigurable processor},
  booktitle    = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
                  Melbourne, Victoria, Australia, June 1-5, 2014},
  pages        = {1736--1739},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISCAS.2014.6865490},
  doi          = {10.1109/ISCAS.2014.6865490},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/KimRSK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isqed/SinkarWK14,
  author       = {Abhishek A. Sinkar and
                  Hao Wang and
                  Nam Sung Kim},
  title        = {Maximizing throughput of power/thermal-constrained processors by balancing
                  power consumption of cores},
  booktitle    = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
                  2014, Santa Clara, CA, USA, March 3-5, 2014},
  pages        = {633--638},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISQED.2014.6783386},
  doi          = {10.1109/ISQED.2014.6783386},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/SinkarWK14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SinkarPK13,
  author       = {Abhishek A. Sinkar and
                  Taejoon Park and
                  Nam Sung Kim},
  title        = {Clamping Virtual Supply Voltage of Power-Gated Circuits for Active
                  Leakage Reduction and Gate-Oxide Reliability},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {21},
  number       = {3},
  pages        = {580--584},
  year         = {2013},
  url          = {https://doi.org/10.1109/TVLSI.2012.2189422},
  doi          = {10.1109/TVLSI.2012.2189422},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SinkarPK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hpca/KarpuzcuSKT13,
  author       = {Ulya R. Karpuzcu and
                  Abhishek A. Sinkar and
                  Nam Sung Kim and
                  Josep Torrellas},
  title        = {EnergySmart: Toward energy-efficient manycores for Near-Threshold
                  Computing},
  booktitle    = {19th {IEEE} International Symposium on High Performance Computer Architecture,
                  {HPCA} 2013, Shenzhen, China, February 23-27, 2013},
  pages        = {542--553},
  publisher    = {{IEEE} Computer Society},
  year         = {2013},
  url          = {https://doi.org/10.1109/HPCA.2013.6522348},
  doi          = {10.1109/HPCA.2013.6522348},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/KarpuzcuSKT13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iccad/WangSK13,
  author       = {Hao Wang and
                  Abhishek A. Sinkar and
                  Nam Sung Kim},
  editor       = {J{\"{o}}rg Henkel},
  title        = {Improving platform energy: chip area trade-off in near-threshold computing
                  environment},
  booktitle    = {The {IEEE/ACM} International Conference on Computer-Aided Design,
                  ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
  pages        = {318--325},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ICCAD.2013.6691138},
  doi          = {10.1109/ICCAD.2013.6691138},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iccad/WangSK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/KimSSS12,
  author       = {Nam Sung Kim and
                  Abhishek A. Sinkar and
                  Jun Seomun and
                  Youngsoo Shin},
  title        = {Maximizing Frequency and Yield of Power-Constrained Designs Using
                  Programmable Power-Gating},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {20},
  number       = {10},
  pages        = {1885--1890},
  year         = {2012},
  url          = {https://doi.org/10.1109/TVLSI.2011.2163533},
  doi          = {10.1109/TVLSI.2011.2163533},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/KimSSS12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dac/GhasemiSSK12,
  author       = {Hamid Reza Ghasemi and
                  Abhishek A. Sinkar and
                  Michael J. Schulte and
                  Nam Sung Kim},
  editor       = {Patrick Groeneveld and
                  Donatella Sciuto and
                  Soha Hassoun},
  title        = {Cost-effective power delivery to support per-core voltage domains
                  for power-constrained processors},
  booktitle    = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
                  Francisco, CA, USA, June 3-7, 2012},
  pages        = {56--61},
  publisher    = {{ACM}},
  year         = {2012},
  url          = {https://doi.org/10.1145/2228360.2228372},
  doi          = {10.1145/2228360.2228372},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dac/GhasemiSSK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/date/SinkarWK12,
  author       = {Abhishek A. Sinkar and
                  Hao Wang and
                  Nam Sung Kim},
  editor       = {Wolfgang Rosenstiel and
                  Lothar Thiele},
  title        = {Workload-aware voltage regulator optimization for power efficient
                  multi-core processors},
  booktitle    = {2012 Design, Automation {\&} Test in Europe Conference {\&}
                  Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
  pages        = {1134--1137},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/DATE.2012.6176667},
  doi          = {10.1109/DATE.2012.6176667},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/date/SinkarWK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/SinkarK11,
  author       = {Abhishek A. Sinkar and
                  Nam Sung Kim},
  title        = {AVS-aware power-gate sizing for maximum performance and power efficiency
                  of power-constrained processors},
  booktitle    = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
                  {ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
  pages        = {725--730},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ASPDAC.2011.5722282},
  doi          = {10.1109/ASPDAC.2011.5722282},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/SinkarK11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isqed/SinkarK10,
  author       = {Abhishek A. Sinkar and
                  Nam Sung Kim},
  title        = {Analyzing and minimizing effects of temperature variation and {NBTI}
                  on active leakage power of power-gated circuits},
  booktitle    = {11th International Symposium on Quality of Electronic Design {(ISQED}
                  2010), 22-24 March 2010, San Jose, CA, {USA}},
  pages        = {791--796},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISQED.2010.5450491},
  doi          = {10.1109/ISQED.2010.5450491},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isqed/SinkarK10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/micro/GunadiSKL10,
  author       = {Erika Gunadi and
                  Abhishek A. Sinkar and
                  Nam Sung Kim and
                  Mikko H. Lipasti},
  title        = {Combating Aging with the Colt Duty Cycle Equalizer},
  booktitle    = {43rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
                  {MICRO} 2010, 4-8 December 2010, Atlanta, Georgia, {USA}},
  pages        = {103--114},
  publisher    = {{IEEE} Computer Society},
  year         = {2010},
  url          = {https://doi.org/10.1109/MICRO.2010.37},
  doi          = {10.1109/MICRO.2010.37},
  timestamp    = {Tue, 31 May 2022 14:39:58 +0200},
  biburl       = {https://dblp.org/rec/conf/micro/GunadiSKL10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/AndersonDLSK09,
  author       = {Michael J. Anderson and
                  Azadeh Davoodi and
                  Jungseob Lee and
                  Abhishek A. Sinkar and
                  Nam Sung Kim},
  editor       = {J{\"{o}}rg Henkel and
                  Ali Keshavarzi and
                  Naehyuck Chang and
                  Tahir Ghani},
  title        = {Statistical static timing analysis considering leakage variability
                  in power gated designs},
  booktitle    = {Proceedings of the 2009 International Symposium on Low Power Electronics
                  and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
  pages        = {57--62},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1594233.1594247},
  doi          = {10.1145/1594233.1594247},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/AndersonDLSK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/KimSSLHCS09,
  author       = {Nam Sung Kim and
                  Jun Seomun and
                  Abhishek A. Sinkar and
                  Jungseob Lee and
                  Tae Hee Han and
                  Ken Choi and
                  Youngsoo Shin},
  editor       = {J{\"{o}}rg Henkel and
                  Ali Keshavarzi and
                  Naehyuck Chang and
                  Tahir Ghani},
  title        = {Frequency and yield optimization using power gates in power-constrained
                  designs},
  booktitle    = {Proceedings of the 2009 International Symposium on Low Power Electronics
                  and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
  pages        = {121--126},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1594233.1594263},
  doi          = {10.1145/1594233.1594263},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/KimSSLHCS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/SinkarK09,
  author       = {Abhishek A. Sinkar and
                  Nam Sung Kim},
  editor       = {J{\"{o}}rg Henkel and
                  Ali Keshavarzi and
                  Naehyuck Chang and
                  Tahir Ghani},
  title        = {Analyzing potential power reduction with adaptive voltage positioning
                  optimized for multicore processors},
  booktitle    = {Proceedings of the 2009 International Symposium on Low Power Electronics
                  and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
  pages        = {189--194},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1594233.1594281},
  doi          = {10.1145/1594233.1594281},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/SinkarK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsid/YaoSS09,
  author       = {Chunhua Yao and
                  Kewal K. Saluja and
                  Abhishek A. Sinkar},
  title        = {{WOR-BIST:} {A} Complete Test Solution for Designs Meeting Power,
                  Area and Performance Requirements},
  booktitle    = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
                  The 22nd International Conference on {VLSI} Design, New Delhi, India,
                  5-9 January 2009},
  pages        = {479--484},
  publisher    = {{IEEE} Computer Society},
  year         = {2009},
  url          = {https://doi.org/10.1109/VLSI.Design.2009.74},
  doi          = {10.1109/VLSI.DESIGN.2009.74},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/YaoSS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vts/XieDSS09,
  author       = {Lin Xie and
                  Azadeh Davoodi and
                  Kewal K. Saluja and
                  Abhishek A. Sinkar},
  title        = {False Path Aware Timing Yield Estimation under Variability},
  booktitle    = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa
                  Cruz, California, {USA}},
  pages        = {161--166},
  publisher    = {{IEEE} Computer Society},
  year         = {2009},
  url          = {https://doi.org/10.1109/VTS.2009.17},
  doi          = {10.1109/VTS.2009.17},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vts/XieDSS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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