BibTeX records: Markus Winter 0002

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@article{DBLP:journals/tecs/ArnoldMN0LF14,
  author       = {Oliver Arnold and
                  Emil Mat{\'{u}}s and
                  Benedikt Noethen and
                  Markus Winter and
                  Torsten Limberg and
                  Gerhard P. Fettweis},
  title        = {Tomahawk: Parallelism and heterogeneity in communications signal processing
                  MPSoCs},
  journal      = {{ACM} Trans. Embed. Comput. Syst.},
  volume       = {13},
  number       = {3s},
  pages        = {107:1--107:24},
  year         = {2014},
  url          = {https://doi.org/10.1145/2517087},
  doi          = {10.1145/2517087},
  timestamp    = {Tue, 08 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tecs/ArnoldMN0LF14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@phdthesis{DBLP:phd/dnb/Winter12,
  author       = {Markus Winter},
  title        = {Unterst{\"{u}}tzung und Organisation von Quality-of-Service-Techniken
                  in Kommunikationsnetzwerken auf einem Chip (Network-on-Chip)},
  school       = {Dresden University of Technology},
  year         = {2012},
  url          = {https://d-nb.info/1020073403},
  isbn         = {978-3-938860-46-5},
  timestamp    = {Sat, 17 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/phd/dnb/Winter12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/WalterHEEHHSWF12,
  author       = {Dennis Walter and
                  Sebastian H{\"{o}}ppner and
                  Holger Eisenreich and
                  Georg Ellguth and
                  Stephan Henker and
                  Stefan H{\"{a}}nzsche and
                  Ren{\'{e}} Sch{\"{u}}ffny and
                  Markus Winter and
                  Gerhard P. Fettweis},
  title        = {A source-synchronous 90Gb/s capacitively driven serial on-chip link
                  over 6mm in 65nm {CMOS}},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {180--182},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176902},
  doi          = {10.1109/ISSCC.2012.6176902},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/WalterHEEHHSWF12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/WinterKAMMFEEHSSK12,
  author       = {Markus Winter and
                  Steffen Kunze and
                  Esther P. Adeva and
                  Bj{\"{o}}rn Mennenga and
                  Emil Mat{\'{u}}s and
                  Gerhard P. Fettweis and
                  Holger Eisenreich and
                  Georg Ellguth and
                  Sebastian H{\"{o}}ppner and
                  Stefan Scholze and
                  Ren{\'{e}} Sch{\"{u}}ffny and
                  Tomoyoshi Kobori},
  title        = {A 335Mb/s 3.9mm\({}^{\mbox{2}}\) 65nm {CMOS} flexible {MIMO} detection-decoding
                  engine achieving 4G wireless data rates},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {216--218},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6176981},
  doi          = {10.1109/ISSCC.2012.6176981},
  timestamp    = {Wed, 15 Nov 2017 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/WinterKAMMFEEHSSK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/date/WinterF11,
  author       = {Markus Winter and
                  Gerhard P. Fettweis},
  title        = {Guaranteed service virtual channel allocation in NoCs for run-time
                  task scheduling},
  booktitle    = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
                  March 14-18, 2011},
  pages        = {419--424},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/DATE.2011.5763073},
  doi          = {10.1109/DATE.2011.5763073},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/date/WinterF11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/GuderianFWF11,
  author       = {Falko Guderian and
                  Erik Fischer and
                  Markus Winter and
                  Gerhard P. Fettweis},
  title        = {Fair rate packet arbitration in Network-on-Chip},
  booktitle    = {{IEEE} 24th International SoC Conference, {SOCC} 2011, Taipei, Taiwan,
                  September 26-28, 2011},
  pages        = {278--283},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/SOCC.2011.6085085},
  doi          = {10.1109/SOCC.2011.6085085},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/GuderianFWF11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dsd/WinterF08,
  author       = {Markus Winter and
                  Gerhard P. Fettweis},
  editor       = {Luca Fanucci},
  title        = {A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in
                  Multi-Processor System-on-Chips},
  booktitle    = {11th Euromicro Conference on Digital System Design: Architectures,
                  Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
  pages        = {133--140},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/DSD.2008.14},
  doi          = {10.1109/DSD.2008.14},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dsd/WinterF08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/esscirc/Limberg0BKMTFAR08,
  author       = {Torsten Limberg and
                  Markus Winter and
                  Marcel Bimberg and
                  Reimund Klemm and
                  Emil Mat{\'{u}}s and
                  Marcos B. S. Tavares and
                  Gerhard P. Fettweis and
                  Hendrik Ahlendorf and
                  Pablo Robelly},
  editor       = {William Redman{-}White and
                  Anthony J. Walton},
  title        = {A fully programmable 40 {GOPS} {SDR} single chip baseband for LTE/WiMAX
                  terminals},
  booktitle    = {{ESSCIRC} 2008 - 34th European Solid-State Circuits Conference, Edinburgh,
                  Scotland, UK, 15-19 September 2008},
  pages        = {466--469},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ESSCIRC.2008.4681893},
  doi          = {10.1109/ESSCIRC.2008.4681893},
  timestamp    = {Mon, 09 Aug 2021 14:54:02 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/Limberg0BKMTFAR08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/issoc/WinterF06,
  author       = {Markus Winter and
                  Gerhard P. Fettweis},
  title        = {Interconnection Generation for System-on-Chip Design},
  booktitle    = {International Symposium on System-on-Chip, SoC 2006, Tampere, Finland,
                  November 13-16, 2006},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSOC.2006.321975},
  doi          = {10.1109/ISSOC.2006.321975},
  timestamp    = {Mon, 09 Aug 2021 14:54:02 +0200},
  biburl       = {https://dblp.org/rec/conf/issoc/WinterF06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}