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BibTeX records: Evangeline F. Y. Young
@article{DBLP:journals/dt/Young24, author = {Evangeline F. Y. Young}, title = {Recap of the 42nd Edition of the International Conference on Computer- Aided Design {(ICCAD} 2023)}, journal = {{IEEE} Des. Test}, volume = {41}, number = {2}, pages = {88--89}, year = {2024}, url = {https://doi.org/10.1109/MDAT.2024.3351568}, doi = {10.1109/MDAT.2024.3351568}, timestamp = {Sat, 16 Mar 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/dt/Young24.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenKZHY23, author = {Jingsong Chen and Jian Kuang and Guowei Zhao and Dennis J.{-}H. Huang and Evangeline F. Y. Young}, title = {{PROS} 2.0: {A} Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {42}, number = {1}, pages = {164--177}, year = {2023}, url = {https://doi.org/10.1109/TCAD.2022.3168259}, doi = {10.1109/TCAD.2022.3168259}, timestamp = {Sun, 15 Jan 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/ChenKZHY23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinLYW23, author = {Shiju Lin and Jinwei Liu and Evangeline F. Y. Young and Martin D. F. Wong}, title = {{GAMER:} GPU-Accelerated Maze Routing}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {42}, number = {2}, pages = {583--593}, year = {2023}, url = {https://doi.org/10.1109/TCAD.2022.3184281}, doi = {10.1109/TCAD.2022.3184281}, timestamp = {Fri, 10 Feb 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LinLYW23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JiangZWY23, author = {Bentian Jiang and Xinshi Zang and Martin D. F. Wong and Evangeline F. Y. Young}, title = {Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {42}, number = {9}, pages = {3067--3077}, year = {2023}, url = {https://doi.org/10.1109/TCAD.2022.3232992}, doi = {10.1109/TCAD.2022.3232992}, timestamp = {Thu, 14 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JiangZWY23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/ZhengY23, author = {Dan Zheng and Evangeline F. Y. Young}, editor = {Atsushi Takahashi}, title = {An Integrated Circuit Partitioning and {TDM} Assignment Optimization Framework for Multi-FPGA Systems}, booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference, {ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023}, pages = {522--528}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3566097.3567897}, doi = {10.1145/3566097.3567897}, timestamp = {Mon, 26 Jun 2023 20:46:40 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/ZhengY23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuY23, author = {Jinwei Liu and Evangeline F. Y. Young}, title = {{EDGE:} Efficient DAG-based Global Routing Engine}, booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco, CA, USA, July 9-13, 2023}, pages = {1--6}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.1109/DAC56929.2023.10247702}, doi = {10.1109/DAC56929.2023.10247702}, timestamp = {Sun, 24 Sep 2023 13:31:06 +0200}, biburl = {https://dblp.org/rec/conf/dac/LiuY23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuY23a, author = {Tianji Liu and Evangeline F. Y. Young}, title = {Rethinking {AIG} Resynthesis in Parallel}, booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco, CA, USA, July 9-13, 2023}, pages = {1--6}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.1109/DAC56929.2023.10247961}, doi = {10.1109/DAC56929.2023.10247961}, timestamp = {Sun, 24 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/LiuY23a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/ZangCLTSYW23, author = {Xinshi Zang and Lei Chen and Xing Li and Wilson W. K. Thong and Weihua Sheng and Evangeline F. Y. Young and Martin D. F. Wong}, editor = {Himanshu Thapliyal and Ronald F. DeMara and Inna Partin{-}Vaisband and Srinivas Katkoori}, title = {{CPP:} {A} Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems}, booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023, {GLSVLSI} 2023, Knoxville, TN, USA, June 5-7, 2023}, pages = {357--361}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3583781.3590289}, doi = {10.1145/3583781.3590289}, timestamp = {Mon, 19 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/ZangCLTSYW23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/ZangYW23, author = {Xinshi Zang and Evangeline F. Y. Young and Martin D. F. Wong}, editor = {Himanshu Thapliyal and Ronald F. DeMara and Inna Partin{-}Vaisband and Srinivas Katkoori}, title = {{SPARK:} {A} Scalable Partitioning and Routing Framework for Multi-FPGA Systems}, booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023, {GLSVLSI} 2023, Knoxville, TN, USA, June 5-7, 2023}, pages = {593--598}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3583781.3590231}, doi = {10.1145/3583781.3590231}, timestamp = {Thu, 15 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/ZangYW23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/WangLY23, author = {Fangzhou Wang and Jinwei Liu and Evangeline F. Y. Young}, editor = {David G. Chinnery and Iris Hui{-}Ru Jiang}, title = {FastPass: Fast Pin Access Analysis with Incremental {SAT} Solving}, booktitle = {Proceedings of the 2023 International Symposium on Physical Design, {ISPD} 2023, Virtual Event, USA, March 26-29, 2023}, pages = {9--16}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3569052.3571879}, doi = {10.1145/3569052.3571879}, timestamp = {Tue, 28 Mar 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/WangLY23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/Young23, author = {Evangeline F. Y. Young}, editor = {David G. Chinnery and Iris Hui{-}Ru Jiang}, title = {{GPU} Acceleration in Physical Synthesis}, booktitle = {Proceedings of the 2023 International Symposium on Physical Design, {ISPD} 2023, Virtual Event, USA, March 26-29, 2023}, pages = {167}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3569052.3578912}, doi = {10.1145/3569052.3578912}, timestamp = {Tue, 28 Mar 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/Young23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/WangWFJ0ASKHY23, author = {Fangzhou Wang and Qijing Wang and Bangqi Fu and Shui Jiang and Xiaopeng Zhang and Lilas Alrahis and Ozgur Sinanoglu and Johann Knechtel and Tsung{-}Yi Ho and Evangeline F. Y. Young}, editor = {David G. Chinnery and Iris Hui{-}Ru Jiang}, title = {Security Closure of {IC} Layouts Against Hardware Trojans}, booktitle = {Proceedings of the 2023 International Symposium on Physical Design, {ISPD} 2023, Virtual Event, USA, March 26-29, 2023}, pages = {229--237}, publisher = {{ACM}}, year = {2023}, url = {https://doi.org/10.1145/3569052.3571878}, doi = {10.1145/3569052.3571878}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/WangWFJ0ASKHY23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiCCYY22, author = {Haocheng Li and Wing{-}Kai Chow and Gengjie Chen and Bei Yu and Evangeline F. Y. Young}, title = {Pin-Accessible Legalization for Mixed-Cell-Height Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {41}, number = {1}, pages = {143--154}, year = {2022}, url = {https://doi.org/10.1109/TCAD.2021.3053223}, doi = {10.1109/TCAD.2021.3053223}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LiCCYY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JiangCLLWZY22, author = {Bentian Jiang and Jingsong Chen and Jinwei Liu and Lixin Liu and Fangzhou Wang and Xiaopeng Zhang and Evangeline F. Y. Young}, title = {CU.POKer: Placing DNNs on {WSE} With Optimal Kernel Sizing and Efficient Protocol Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {41}, number = {6}, pages = {1888--1901}, year = {2022}, url = {https://doi.org/10.1109/TCAD.2021.3096458}, doi = {10.1109/TCAD.2021.3096458}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JiangCLLWZY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JiangLMYY22, author = {Bentian Jiang and Lixin Liu and Yuzhe Ma and Bei Yu and Evangeline F. Y. Young}, title = {Neural-ILT 2.0: Migrating {ILT} to Domain-Specific and Multitask-Enabled Neural Network}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {41}, number = {8}, pages = {2671--2684}, year = {2022}, url = {https://doi.org/10.1109/TCAD.2021.3109556}, doi = {10.1109/TCAD.2021.3109556}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JiangLMYY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LinLLWY22, author = {Shiju Lin and Jinwei Liu and Tianji Liu and Martin D. F. Wong and Evangeline F. Y. Young}, editor = {Rob Oshana}, title = {NovelRewrite: node-level parallel {AIG} rewriting}, booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022}, pages = {427--432}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3489517.3530462}, doi = {10.1145/3489517.3530462}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/LinLLWY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuZLZCJWY22, author = {Jinwei Liu and Xiaopeng Zhang and Shiju Lin and Xinshi Zang and Jingsong Chen and Bentian Jiang and Martin D. F. Wong and Evangeline F. Y. Young}, editor = {Rob Oshana}, title = {Partition and place finite element model on wafer-scale engine}, booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022}, pages = {631--636}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3489517.3530565}, doi = {10.1145/3489517.3530565}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/LiuZLZCJWY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/WangJWY22, author = {Qijing Wang and Bentian Jiang and Martin D. F. Wong and Evangeline F. Y. Young}, editor = {Rob Oshana}, title = {{A2-ILT:} {GPU} accelerated {ILT} with spatial attention mechanism}, booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022}, pages = {967--972}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3489517.3530579}, doi = {10.1145/3489517.3530579}, timestamp = {Mon, 01 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/WangJWY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuFWY22, author = {Lixin Liu and Bangqi Fu and Martin D. F. Wong and Evangeline F. Y. Young}, editor = {Rob Oshana}, title = {Xplace: an extremely fast and extensible global placement framework}, booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022}, pages = {1309--1314}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3489517.3530485}, doi = {10.1145/3489517.3530485}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/LiuFWY22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/PosserYHLP22, author = {Gracieli Posser and Evangeline F. Y. Young and Stephan Held and Yih{-}Lang Li and David Z. Pan}, editor = {Laleh Behjat and Stephen Yang}, title = {Challenges and Approaches in {VLSI} Routing}, booktitle = {{ISPD} 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27 - 30, 2022}, pages = {185--192}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3505170.3511477}, doi = {10.1145/3505170.3511477}, timestamp = {Thu, 14 Apr 2022 14:53:52 +0200}, biburl = {https://dblp.org/rec/conf/ispd/PosserYHLP22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/0007HC0YLCHH22, author = {Xiaopeng Zhang and Shoubo Hu and Zhitang Chen and Shengyu Zhu and Evangeline F. Y. Young and Pengyun Li and Cheng Chen and Yu Huang and Jianye Hao}, title = {RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement}, booktitle = {{IEEE} International Test Conference, {ITC} 2022, Anaheim, CA, USA, September 23-30, 2022}, pages = {100--107}, publisher = {{IEEE}}, year = {2022}, url = {https://doi.org/10.1109/ITC50671.2022.00017}, doi = {10.1109/ITC50671.2022.00017}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/itc/0007HC0YLCHH22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/iccad/2022, editor = {Tulika Mitra and Evangeline F. Y. Young and Jinjun Xiong}, title = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022}, publisher = {{ACM}}, year = {2022}, url = {https://doi.org/10.1145/3508352}, doi = {10.1145/3508352}, isbn = {978-1-4503-9217-4}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/2022.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2211-07997, author = {Fangzhou Wang and Qijing Wang and Bangqi Fu and Shui Jiang and Xiaopeng Zhang and Lilas Alrahis and Ozgur Sinanoglu and Johann Knechtel and Tsung{-}Yi Ho and Evangeline F. Y. Young}, title = {Security Closure of {IC} Layouts Against Hardware Trojans}, journal = {CoRR}, volume = {abs/2211.07997}, year = {2022}, url = {https://doi.org/10.48550/arXiv.2211.07997}, doi = {10.48550/ARXIV.2211.07997}, eprinttype = {arXiv}, eprint = {2211.07997}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2211-07997.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiPAYKYSY21, author = {Haocheng Li and Satwik Patnaik and Mohammed Ashraf and Haoyu Yang and Johann Knechtel and Bei Yu and Ozgur Sinanoglu and Evangeline F. Y. Young}, title = {Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {40}, number = {10}, pages = {1995--2008}, year = {2021}, url = {https://doi.org/10.1109/TCAD.2020.3037297}, doi = {10.1109/TCAD.2020.3037297}, timestamp = {Mon, 28 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiPAYKYSY21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/ZhengZPY21, author = {Dan Zheng and Xiaopeng Zhang and Chak{-}Wa Pui and Evangeline F. Y. Young}, title = {Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment}, booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021}, pages = {176--182}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3394885.3431565}, doi = {10.1145/3394885.3431565}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/ZhengZPY21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/YangZ0LTKG0Y21, author = {Haoyu Yang and Shifan Zhang and Kang Liu and Siting Liu and Benjamin Tan and Ramesh Karri and Siddharth Garg and Bei Yu and Evangeline F. Y. Young}, title = {Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method}, booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021}, pages = {885--891}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3394885.3431571}, doi = {10.1145/3394885.3431571}, timestamp = {Mon, 08 Jan 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/YangZ0LTKG0Y21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ZhangYY21, author = {Xiaopeng Zhang and Haoyu Yang and Evangeline F. Y. Young}, title = {Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation}, booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco, CA, USA, December 5-9, 2021}, pages = {169--174}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/DAC18074.2021.9586227}, doi = {10.1109/DAC18074.2021.9586227}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/ZhangYY21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuCY21, author = {Jinwei Liu and Gengjie Chen and Evangeline F. Y. Young}, title = {{REST:} Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning}, booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco, CA, USA, December 5-9, 2021}, pages = {1135--1140}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/DAC18074.2021.9586209}, doi = {10.1109/DAC18074.2021.9586209}, timestamp = {Fri, 12 Nov 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LiuCY21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/JiangZLY21, author = {Bentian Jiang and Xiaopeng Zhang and Lixin Liu and Evangeline F. Y. Young}, editor = {Jens Lienig and Laleh Behjat and Stephen Yang}, title = {Building up End-to-end Mask Optimization Framework with Self-training}, booktitle = {{ISPD} '21: International Symposium on Physical Design, Virtual Event, USA, March 22-24, 2021}, pages = {63--70}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3439706.3447050}, doi = {10.1145/3439706.3447050}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/JiangZLY21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenY20, author = {Gengjie Chen and Evangeline F. Y. Young}, title = {{SALT:} Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {39}, number = {6}, pages = {1217--1230}, year = {2020}, url = {https://doi.org/10.1109/TCAD.2019.2894653}, doi = {10.1109/TCAD.2019.2894653}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TuPY20, author = {Peishan Tu and Chak{-}Wa Pui and Evangeline F. Y. Young}, title = {Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {39}, number = {6}, pages = {1245--1257}, year = {2020}, url = {https://doi.org/10.1109/TCAD.2019.2912930}, doi = {10.1109/TCAD.2019.2912930}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TuPY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenPLY20, author = {Gengjie Chen and Chak{-}Wa Pui and Haocheng Li and Evangeline F. Y. Young}, title = {Dr. {CU:} Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {39}, number = {9}, pages = {1902--1915}, year = {2020}, url = {https://doi.org/10.1109/TCAD.2019.2927542}, doi = {10.1109/TCAD.2019.2927542}, timestamp = {Thu, 02 Sep 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenPLY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YangLDMYY20, author = {Haoyu Yang and Shuhe Li and Zihao Deng and Yuzhe Ma and Bei Yu and Evangeline F. Y. Young}, title = {{GAN-OPC:} Mask Optimization With Lithography-Guided Generative Adversarial Nets}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {39}, number = {10}, pages = {2822--2834}, year = {2020}, url = {https://doi.org/10.1109/TCAD.2019.2939329}, doi = {10.1109/TCAD.2019.2939329}, timestamp = {Tue, 06 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YangLDMYY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/PuiY20, author = {Chak{-}Wa Pui and Evangeline F. Y. Young}, title = {Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {25}, number = {2}, pages = {21:1--21:23}, year = {2020}, url = {https://doi.org/10.1145/3377551}, doi = {10.1145/3377551}, timestamp = {Wed, 01 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/todaes/PuiY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/LiuYMTYYKG20, author = {Kang Liu and Haoyu Yang and Yuzhe Ma and Benjamin Tan and Bei Yu and Evangeline F. Y. Young and Ramesh Karri and Siddharth Garg}, title = {Adversarial Perturbation Attacks on ML-based {CAD:} {A} Case Study on CNN-based Lithographic Hotspot Detection}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {25}, number = {5}, pages = {48:1--48:31}, year = {2020}, url = {https://doi.org/10.1145/3408288}, doi = {10.1145/3408288}, timestamp = {Sun, 12 Nov 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/LiuYMTYYKG20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiuPWY20, author = {Jinwei Liu and Chak{-}Wa Pui and Fangzhou Wang and Evangeline F. Y. Young}, title = {{CUGR:} Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model}, booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco, CA, USA, July 20-24, 2020}, pages = {1--6}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/DAC18072.2020.9218646}, doi = {10.1109/DAC18072.2020.9218646}, timestamp = {Wed, 14 Oct 2020 10:56:17 +0200}, biburl = {https://dblp.org/rec/conf/dac/LiuPWY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/Chen0ZHY20, author = {Jingsong Chen and Jian Kuang and Guowei Zhao and Dennis J.{-}H. Huang and Evangeline F. Y. Young}, title = {{PROS:} {A} Plug-in for Routability Optimization applied in the State-of-the-art commercial {EDA} tool using deep learning}, booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD} 2020, San Diego, CA, USA, November 2-5, 2020}, pages = {17:1--17:8}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1145/3400302.3415662}, doi = {10.1145/3400302.3415662}, timestamp = {Mon, 18 Jan 2021 09:56:56 +0100}, biburl = {https://dblp.org/rec/conf/iccad/Chen0ZHY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/JiangLM00Y20, author = {Bentian Jiang and Lixin Liu and Yuzhe Ma and Hang Zhang and Bei Yu and Evangeline F. Y. Young}, title = {Neural-ILT: Migrating {ILT} to Neural Networks for Mask Printability and Complexity Co-optimization}, booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD} 2020, San Diego, CA, USA, November 2-5, 2020}, pages = {20:1--20:9}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1145/3400302.3415704}, doi = {10.1145/3400302.3415704}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/JiangLM00Y20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ZhangSY20, author = {Xiaopeng Zhang and James P. Shiely and Evangeline F. Y. Young}, title = {Layout Pattern Generation and Legalization with Generative Learning Models}, booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD} 2020, San Diego, CA, USA, November 2-5, 2020}, pages = {32:1--32:9}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1145/3400302.3415607}, doi = {10.1145/3400302.3415607}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/ZhangSY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/JiangCLLWZY20, author = {Bentian Jiang and Jingsong Chen and Jinwei Liu and Lixin Liu and Fangzhou Wang and Xiaopeng Zhang and Evangeline F. Y. Young}, title = {CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing}, booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD} 2020, San Diego, CA, USA, November 2-5, 2020}, pages = {142:1--142:9}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1145/3400302.3415688}, doi = {10.1145/3400302.3415688}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/JiangCLLWZY20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2007-03989, author = {Haocheng Li and Satwik Patnaik and Abhrajit Sengupta and Haoyu Yang and Johann Knechtel and Bei Yu and Evangeline F. Y. Young and Ozgur Sinanoglu}, title = {Attacking Split Manufacturing from a Deep Learning Perspective}, journal = {CoRR}, volume = {abs/2007.03989}, year = {2020}, url = {https://arxiv.org/abs/2007.03989}, eprinttype = {arXiv}, eprint = {2007.03989}, timestamp = {Mon, 20 Jul 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2007-03989.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YangSZMYY19, author = {Haoyu Yang and Jing Su and Yi Zou and Yuzhe Ma and Bei Yu and Evangeline F. Y. Young}, title = {Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {38}, number = {6}, pages = {1175--1187}, year = {2019}, url = {https://doi.org/10.1109/TCAD.2018.2837078}, doi = {10.1109/TCAD.2018.2837078}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YangSZMYY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KuangY19, author = {Jian Kuang and Evangeline F. Y. Young}, title = {Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {38}, number = {9}, pages = {1731--1743}, year = {2019}, url = {https://doi.org/10.1109/TCAD.2018.2859255}, doi = {10.1109/TCAD.2018.2859255}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KuangY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/KangQPKYCG19, author = {Ilgweon Kang and Fang Qiao and Dongwon Park and Daniel Kane and Evangeline F. Y. Young and Chung{-}Kuan Cheng and Ronald L. Graham}, title = {Three-dimensional Floorplan Representations by Using Corner Links and Partial Order}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {24}, number = {1}, pages = {13:1--13:33}, year = {2019}, url = {https://doi.org/10.1145/3289179}, doi = {10.1145/3289179}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/KangQPKYCG19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/JiangZYY19, author = {Bentian Jiang and Hang Zhang and Jinglei Yang and Evangeline F. Y. Young}, editor = {Toshiyuki Shibuya}, title = {A fast machine learning-based mask printability predictor for {OPC} acceleration}, booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference, {ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019}, pages = {412--419}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3287624.3287682}, doi = {10.1145/3287624.3287682}, timestamp = {Sun, 25 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/JiangZYY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/ChenPLCJY19, author = {Gengjie Chen and Chak{-}Wa Pui and Haocheng Li and Jingsong Chen and Bentian Jiang and Evangeline F. Y. Young}, editor = {Toshiyuki Shibuya}, title = {Detailed routing by sparse grid graph and minimum-area-captured path search}, booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference, {ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019}, pages = {754--760}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3287624.3287678}, doi = {10.1145/3287624.3287678}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/ChenPLCJY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiPSYKYYS19, author = {Haocheng Li and Satwik Patnaik and Abhrajit Sengupta and Haoyu Yang and Johann Knechtel and Bei Yu and Evangeline F. Y. Young and Ozgur Sinanoglu}, title = {Attacking Split Manufacturing from a Deep Learning Perspective}, booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019, {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019}, pages = {135}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3316781.3317780}, doi = {10.1145/3316781.3317780}, timestamp = {Tue, 21 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LiPSYKYYS19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChenLCZY19, author = {Jingsong Chen and Jinwei Liu and Gengjie Chen and Dan Zheng and Evangeline F. Y. Young}, title = {{MARCH:} MAze Routing Under a Concurrent and Hierarchical Scheme for Buses}, booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019, {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019}, pages = {216}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3316781.3317860}, doi = {10.1145/3316781.3317860}, timestamp = {Sun, 08 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/ChenLCZY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/JiangZCCTLYY19, author = {Bentian Jiang and Xiaopeng Zhang and Ran Chen and Gengjie Chen and Peishan Tu and Wei Li and Evangeline F. Y. Young and Bei Yu}, title = {{FIT:} Fill Insertion Considering Timing}, booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019, {DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019}, pages = {221}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3316781.3317826}, doi = {10.1145/3316781.3317826}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/JiangZCCTLYY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ChenY19, author = {Gengjie Chen and Evangeline F. Y. Young}, editor = {J{\"{u}}rgen Teich and Franco Fummi}, title = {Dim Sum: Light Clock Tree by Small Diameter Sum}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2019, Florence, Italy, March 25-29, 2019}, pages = {174--179}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.23919/DATE.2019.8715285}, doi = {10.23919/DATE.2019.8715285}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/date/ChenY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LiCJCY19, author = {Haocheng Li and Gengjie Chen and Bentian Jiang and Jingsong Chen and Evangeline F. Y. Young}, editor = {David Z. Pan}, title = {Dr. {CU} 2.0: {A} Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019}, pages = {1--7}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1109/ICCAD45719.2019.8942074}, doi = {10.1109/ICCAD45719.2019.8942074}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/LiCJCY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/PuiY19, author = {Chak{-}Wa Pui and Evangeline F. Y. Young}, editor = {David Z. Pan}, title = {Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019}, pages = {1--8}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1109/ICCAD45719.2019.8942125}, doi = {10.1109/ICCAD45719.2019.8942125}, timestamp = {Wed, 19 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/PuiY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/Young19, author = {Evangeline F. Y. Young}, editor = {Ismail Bustany and William Swartz}, title = {Session details: Patterning and Machine Learning}, booktitle = {Proceedings of the 2019 International Symposium on Physical Design, {ISPD} 2019, San Francisco, CA, USA, April 14-17, 2019}, publisher = {{ACM}}, year = {2019}, url = {https://dl.acm.org/citation.cfm?id=3325188}, timestamp = {Fri, 12 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/Young19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/PuiWMY19, author = {Chak{-}Wa Pui and Gang Wu and Freddy Y. C. Mang and Evangeline F. Y. Young}, title = {An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems}, booktitle = {21st {ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2019, Las Vegas, NV, USA, June 1-2, 2019}, pages = {1--8}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.1109/SLIP.2019.8771330}, doi = {10.1109/SLIP.2019.8771330}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/slip/PuiWMY19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-1906-10773, author = {Kang Liu and Haoyu Yang and Yuzhe Ma and Benjamin Tan and Bei Yu and Evangeline F. Y. Young and Ramesh Karri and Siddharth Garg}, title = {Are Adversarial Perturbations a Showstopper for ML-Based CAD? {A} Case Study on CNN-Based Lithographic Hotspot Detection}, journal = {CoRR}, volume = {abs/1906.10773}, year = {2019}, url = {http://arxiv.org/abs/1906.10773}, eprinttype = {arXiv}, eprint = {1906.10773}, timestamp = {Mon, 29 Nov 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/corr/abs-1906-10773.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KuangYY18, author = {Jian Kuang and Junjie Ye and Evangeline F. Y. Young}, title = {{STOMA:} Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {37}, number = {6}, pages = {1251--1264}, year = {2018}, url = {https://doi.org/10.1109/TCAD.2017.2748022}, doi = {10.1109/TCAD.2017.2748022}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KuangYY18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenPCLKYY18, author = {Gengjie Chen and Chak{-}Wa Pui and Wing{-}Kai Chow and Ka{-}Chun Lam and Jian Kuang and Evangeline F. Y. Young and Bei Yu}, title = {RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {37}, number = {10}, pages = {2022--2035}, year = {2018}, url = {https://doi.org/10.1109/TCAD.2017.2778058}, doi = {10.1109/TCAD.2017.2778058}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenPCLKYY18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KuangYY18a, author = {Jian Kuang and Evangeline F. Y. Young and Bei Yu}, title = {{CRMA:} Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {37}, number = {10}, pages = {2036--2049}, year = {2018}, url = {https://doi.org/10.1109/TCAD.2017.2778069}, doi = {10.1109/TCAD.2017.2778069}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KuangYY18a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/PuiTLCY18, author = {Chak{-}Wa Pui and Peishan Tu and Haocheng Li and Gengjie Chen and Evangeline F. Y. Young}, editor = {Youngsoo Shin}, title = {A two-step search engine for large scale boolean matching under {NP3} equivalence}, booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC} 2018, Jeju, Korea (South), January 22-25, 2018}, pages = {592--598}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/ASPDAC.2018.8297387}, doi = {10.1109/ASPDAC.2018.8297387}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/PuiTLCY18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/YangLMYY18, author = {Haoyu Yang and Shuhe Li and Yuzhe Ma and Bei Yu and Evangeline F. Y. Young}, title = {{GAN-OPC:} mask optimization with lithography-guided generative adversarial nets}, booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC} 2018, San Francisco, CA, USA, June 24-29, 2018}, pages = {131:1--131:6}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3195970.3196056}, doi = {10.1145/3195970.3196056}, timestamp = {Wed, 16 Oct 2019 14:14:54 +0200}, biburl = {https://dblp.org/rec/conf/dac/YangLMYY18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/LiCCYY18, author = {Haocheng Li and Wing{-}Kai Chow and Gengjie Chen and Evangeline F. Y. Young and Bei Yu}, title = {Routability-driven and fence-aware legalization for mixed-cell-height circuits}, booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC} 2018, San Francisco, CA, USA, June 24-29, 2018}, pages = {150:1--150:6}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3195970.3196107}, doi = {10.1145/3195970.3196107}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/LiCCYY18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/DaiZZUYZ18, author = {Steve Dai and Yuan Zhou and Hang Zhang and Ecenur Ustun and Evangeline F. Y. Young and Zhiru Zhang}, title = {Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning}, booktitle = {26th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May 1, 2018}, pages = {129--132}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/FCCM.2018.00029}, doi = {10.1109/FCCM.2018.00029}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/DaiZZUYZ18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/TuPY18, author = {Peishan Tu and Chak{-}Wa Pui and Evangeline F. Y. Young}, editor = {Deming Chen and Houman Homayoun and Baris Taskin}, title = {Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration}, booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI, {GLSVLSI} 2018, Chicago, IL, USA, May 23-25, 2018}, pages = {261--266}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3194554.3194556}, doi = {10.1145/3194554.3194556}, timestamp = {Wed, 10 Mar 2021 14:55:38 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/TuPY18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/0001Y17, author = {Jian Kuang and Evangeline F. Y. Young}, title = {Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond}, booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC} 2017, Austin, TX, USA, June 18-22, 2017}, pages = {61:1--61:6}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3061639.3062250}, doi = {10.1145/3061639.3062250}, timestamp = {Tue, 06 Nov 2018 16:58:15 +0100}, biburl = {https://dblp.org/rec/conf/dac/0001Y17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/YangSZYY17, author = {Haoyu Yang and Jing Su and Yi Zou and Bei Yu and Evangeline F. Y. Young}, title = {Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning}, booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC} 2017, Austin, TX, USA, June 18-22, 2017}, pages = {62:1--62:6}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3061639.3062270}, doi = {10.1145/3061639.3062270}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/YangSZYY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/Chen0ZZYY17, author = {Gengjie Chen and Jian Kuang and Zhiliang Zeng and Hang Zhang and Evangeline F. Y. Young and Bei Yu}, title = {Minimizing Thermal Gradient and Pumping Power in 3D {IC} Liquid Cooling Network Design}, booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC} 2017, Austin, TX, USA, June 18-22, 2017}, pages = {70:1--70:6}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3061639.3062285}, doi = {10.1145/3061639.3062285}, timestamp = {Sun, 25 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/Chen0ZZYY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChenTY17, author = {Gengjie Chen and Peishan Tu and Evangeline F. Y. Young}, editor = {Sri Parameswaran}, title = {{SALT:} Provably good routing topology by a novel steiner shallow-light tree algorithm}, booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017}, pages = {569--576}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/ICCAD.2017.8203828}, doi = {10.1109/ICCAD.2017.8203828}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iccad/ChenTY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/PuiCMYY17, author = {Chak{-}Wa Pui and Gengjie Chen and Yuzhe Ma and Evangeline F. Y. Young and Bei Yu}, editor = {Sri Parameswaran}, title = {Clock-aware ultrascale {FPGA} placement with machine learning routability prediction: (Invited paper)}, booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017}, pages = {929--936}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/ICCAD.2017.8203880}, doi = {10.1109/ICCAD.2017.8203880}, timestamp = {Thu, 12 Apr 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/PuiCMYY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/ZhangZLYY17, author = {Hang Zhang and Fengyuan Zhu and Haocheng Li and Evangeline F. Y. Young and Bei Yu}, editor = {Mustafa Ozdal and Chris Chu}, title = {Bilinear Lithography Hotspot Detection}, booktitle = {Proceedings of the 2017 {ACM} on International Symposium on Physical Design, {ISDP} 2017, Portland, OR, USA, March 19-22, 2017}, pages = {7--14}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3036669.3036673}, doi = {10.1145/3036669.3036673}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/ZhangZLYY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/Chow0TY17, author = {Wing{-}Kai Chow and Jian Kuang and Peishan Tu and Evangeline F. Y. Young}, title = {Fence-aware detailed-routability driven placement}, booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017}, pages = {1--7}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/SLIP.2017.7974905}, doi = {10.1109/SLIP.2017.7974905}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/slip/Chow0TY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/TuCY17, author = {Peishan Tu and Wing{-}Kai Chow and Evangeline F. Y. Young}, title = {Timing driven routing tree construction}, booktitle = {{ACM/IEEE} 2017 International Workshop on System Level Interconnect Prediction, {SLIP} 2017, Austin, TX, USA, June 17, 2017}, pages = {1--8}, publisher = {{IEEE} Computer Society}, year = {2017}, url = {https://doi.org/10.1109/SLIP.2017.7974908}, doi = {10.1109/SLIP.2017.7974908}, timestamp = {Tue, 18 Jul 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/TuCY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/socc/YangLYY17, author = {Haoyu Yang and Yajun Lin and Bei Yu and Evangeline F. Y. Young}, editor = {Massimo Alioto and Hai Helen Li and J{\"{u}}rgen Becker and Ulf Schlichtmann and Ramalingam Sridhar}, title = {Lithography hotspot detection: From shallow to deep learning}, booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017, Munich, Germany, September 5-8, 2017}, pages = {233--238}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/SOCC.2017.8226047}, doi = {10.1109/SOCC.2017.8226047}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/socc/YangLYY17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/KuangY16, author = {Jian Kuang and Evangeline F. Y. Young}, title = {Row-structure stencil planning approaches for E-beam lithography with overlapped characters}, journal = {Integr.}, volume = {55}, pages = {232--245}, year = {2016}, url = {https://doi.org/10.1016/j.vlsi.2016.07.002}, doi = {10.1016/J.VLSI.2016.07.002}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/KuangY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ipsj/ChowY16, author = {Wing{-}Kai Chow and Evangeline F. Y. Young}, title = {Placement: From Wirelength to Detailed Routability}, journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.}, volume = {9}, pages = {2--12}, year = {2016}, url = {https://doi.org/10.2197/ipsjtsldm.9.2}, doi = {10.2197/IPSJTSLDM.9.2}, timestamp = {Tue, 29 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ipsj/ChowY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/YoungD16, author = {Evangeline F. Y. Young and Azadeh Davoodi}, title = {Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {21}, number = {3}, pages = {36:1}, year = {2016}, url = {https://doi.org/10.1145/2902365}, doi = {10.1145/2902365}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/YoungD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/LiuTWTJKY16, author = {Chuangwen Liu and Peishan Tu and Pangbo Wu and Haomo Tang and Yande Jiang and Jian Kuang and Evangeline F. Y. Young}, title = {An Effective Chemical Mechanical Polishing Fill Insertion Approach}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {21}, number = {3}, pages = {54:1--54:21}, year = {2016}, url = {https://doi.org/10.1145/2886097}, doi = {10.1145/2886097}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/LiuTWTJKY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/HeWGY16, author = {Xu He and Yao Wang and Yang Guo and Evangeline F. Y. Young}, title = {Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {22}, number = {1}, pages = {10:1--10:26}, year = {2016}, url = {https://doi.org/10.1145/2925989}, doi = {10.1145/2925989}, timestamp = {Sun, 23 Apr 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/todaes/HeWGY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/0001CY16, author = {Jian Kuang and Wing{-}Kai Chow and Evangeline F. Y. Young}, title = {Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {24}, number = {4}, pages = {1319--1332}, year = {2016}, url = {https://doi.org/10.1109/TVLSI.2015.2461463}, doi = {10.1109/TVLSI.2015.2461463}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/0001CY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/3dic/QiaoKKYCG16, author = {Fang Qiao and Ilgweon Kang and Daniel Kane and Fung Yu Young and Chung{-}Kuan Cheng and Ronald L. Graham}, title = {3D floorplan representations: Corner links and partial order}, booktitle = {2016 {IEEE} International 3D Systems Integration Conference, 3DIC 2016, San Francisco, CA, USA, November 8-11, 2016}, pages = {1--5}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/3DIC.2016.7970023}, doi = {10.1109/3DIC.2016.7970023}, timestamp = {Wed, 16 Oct 2019 14:14:50 +0200}, biburl = {https://dblp.org/rec/conf/3dic/QiaoKKYCG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/apccas/ZhangYYY16, author = {Hang Zhang and Haoyu Yang and Bei Yu and Evangeline F. Y. Young}, title = {{VLSI} layout hotspot detection based on discriminative feature extraction}, booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2016, Jeju, South Korea, October 25-28, 2016}, pages = {542--545}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/APCCAS.2016.7804024}, doi = {10.1109/APCCAS.2016.7804024}, timestamp = {Sun, 25 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/apccas/ZhangYYY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/0001YY16, author = {Jian Kuang and Junjie Ye and Evangeline F. Y. Young}, title = {Simultaneous template optimization and mask assignment for {DSA} with multiple patterning}, booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC} 2016, Macao, Macao, January 25-28, 2016}, pages = {75--82}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ASPDAC.2016.7427992}, doi = {10.1109/ASPDAC.2016.7427992}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/0001YY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ChowPY16, author = {Wing{-}Kai Chow and Chak{-}Wa Pui and Evangeline F. Y. Young}, title = {Legalization algorithm for multiple-row height standard cell design}, booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC} 2016, Austin, TX, USA, June 5-9, 2016}, pages = {83:1--83:6}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2897937.2898038}, doi = {10.1145/2897937.2898038}, timestamp = {Tue, 06 Nov 2018 16:58:19 +0100}, biburl = {https://dblp.org/rec/conf/dac/ChowPY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/0001Y16, author = {Jian Kuang and Evangeline F. Y. Young}, editor = {Luca Fanucci and J{\"{u}}rgen Teich}, title = {Optimization for Multiple Patterning Lithography with cutting process and beyond}, booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016}, pages = {43--48}, publisher = {{IEEE}}, year = {2016}, url = {https://ieeexplore.ieee.org/document/7459278/}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/0001Y16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ZhangYY16, author = {Hang Zhang and Bei Yu and Evangeline F. Y. Young}, editor = {Frank Liu}, title = {Enabling online learning in lithography hotspot detection with information-theoretic feature optimization}, booktitle = {Proceedings of the 35th International Conference on Computer-Aided Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016}, pages = {47}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2966986.2967032}, doi = {10.1145/2966986.2967032}, timestamp = {Fri, 23 Jun 2023 22:29:48 +0200}, biburl = {https://dblp.org/rec/conf/iccad/ZhangYY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/0001YY16, author = {Jian Kuang and Evangeline F. Y. Young and Bei Yu}, editor = {Frank Liu}, title = {Incorporating cut redistribution with mask assignment to enable 1D gridded design}, booktitle = {Proceedings of the 35th International Conference on Computer-Aided Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016}, pages = {48}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2966986.2967048}, doi = {10.1145/2966986.2967048}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/0001YY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/PuiCCL0TZYY16, author = {Chak{-}Wa Pui and Gengjie Chen and Wing{-}Kai Chow and Ka{-}Chun Lam and Jian Kuang and Peishan Tu and Hang Zhang and Evangeline F. Y. Young and Bei Yu}, editor = {Frank Liu}, title = {RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs}, booktitle = {Proceedings of the 35th International Conference on Computer-Aided Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016}, pages = {67}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2966986.2980084}, doi = {10.1145/2966986.2980084}, timestamp = {Sun, 25 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/PuiCCL0TZYY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/ispd/2016, editor = {Evangeline F. Y. Young and Mustafa Ozdal}, title = {Proceedings of the 2016 on International Symposium on Physical Design, {ISPD} 2016, Santa Rosa, CA, USA, April 3-6, 2016}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2872334}, doi = {10.1145/2872334}, isbn = {978-1-4503-4039-7}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/2016.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:reference/algo/Young16b, author = {Evangeline F. Y. Young}, title = {Slicing Floorplan Orientation}, booktitle = {Encyclopedia of Algorithms}, pages = {2002--2006}, year = {2016}, url = {https://doi.org/10.1007/978-1-4939-2864-4\_379}, doi = {10.1007/978-1-4939-2864-4\_379}, timestamp = {Wed, 12 Jul 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/reference/algo/Young16b.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KnechtelYL15, author = {Johann Knechtel and Evangeline F. Y. Young and Jens Lienig}, title = {Planning Massive Interconnects in 3-D Chips}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {34}, number = {11}, pages = {1808--1821}, year = {2015}, url = {https://doi.org/10.1109/TCAD.2015.2432141}, doi = {10.1109/TCAD.2015.2432141}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KnechtelYL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/0001CY15, author = {Jian Kuang and Wing{-}Kai Chow and Evangeline F. Y. Young}, editor = {Wolfgang Nebel and David Atienza}, title = {A robust approach for process variation aware mask optimization}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, pages = {1591--1594}, publisher = {{ACM}}, year = {2015}, url = {http://dl.acm.org/citation.cfm?id=2757180}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/0001CY15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LiuLY15, author = {Zhiqing Liu and Chuangwen Liu and Evangeline F. Y. Young}, editor = {Wolfgang Nebel and David Atienza}, title = {An effective triple patterning aware grid-based detailed routing approach}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, pages = {1641--1646}, publisher = {{ACM}}, year = {2015}, url = {http://dl.acm.org/citation.cfm?id=2757193}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/LiuLY15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isvlsi/LiuTWTJ0Y15, author = {Chuangwen Liu and Peishan Tu and Pangbo Wu and Haomo Tang and Yande Jiang and Jian Kuang and Evangeline F. Y. Young}, title = {An Effective Chemical Mechanical Polishing Filling Approach}, booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015, Montpellier, France, July 8-10, 2015}, pages = {44--49}, publisher = {{IEEE} Computer Society}, year = {2015}, url = {https://doi.org/10.1109/ISVLSI.2015.75}, doi = {10.1109/ISVLSI.2015.75}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/LiuTWTJ0Y15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/ispd/2015, editor = {Azadeh Davoodi and Evangeline F. Y. Young}, title = {Proceedings of the 2015 Symposium on International Symposium on Physical Design, {ISPD} 2015, Monterey, CA, USA, March 29 - April 1, 2015}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2717764}, doi = {10.1145/2717764}, isbn = {978-1-4503-3399-3}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/2015.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/ChowLYS14, author = {Wing{-}Kai Chow and Liang Li and Evangeline F. Y. Young and Chiu{-}Wing Sham}, title = {Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach}, journal = {Integr.}, volume = {47}, number = {1}, pages = {105--114}, year = {2014}, url = {https://doi.org/10.1016/j.vlsi.2013.08.001}, doi = {10.1016/J.VLSI.2013.08.001}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/ChowLYS14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/KnechtelYL14, author = {Johann Knechtel and Evangeline F. Y. Young and Jens Lienig}, title = {Structural planning of 3D-IC interconnects by block alignment}, booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2014, Singapore, January 20-23, 2014}, pages = {53--60}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ASPDAC.2014.6742866}, doi = {10.1109/ASPDAC.2014.6742866}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/KnechtelYL14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/YeungY14, author = {Jackson H. C. Yeung and Evangeline F. Y. Young}, title = {General purpose cross-referencing Microfluidic Biochip with reduced pin-count}, booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2014, Singapore, January 20-23, 2014}, pages = {238--243}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ASPDAC.2014.6742896}, doi = {10.1109/ASPDAC.2014.6742896}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/YeungY14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/LamTY14, author = {Ka{-}Chun Lam and Wai{-}Chung Tang and Evangeline F. Y. Young}, editor = {Vaughn Betz and George A. Constantinides}, title = {A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)}, booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014}, pages = {242}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2554688.2554711}, doi = {10.1145/2554688.2554711}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/LamTY14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/0001CY14, author = {Jian Kuang and Wing{-}Kai Chow and Evangeline F. Y. Young}, editor = {Yao{-}Wen Chang}, title = {Triple patterning lithography aware optimization for standard cell based design}, booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014}, pages = {108--115}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ICCAD.2014.7001340}, doi = {10.1109/ICCAD.2014.7001340}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iccad/0001CY14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/0001Y14, author = {Jian Kuang and Evangeline F. Y. Young}, editor = {Yao{-}Wen Chang}, title = {Overlapping-aware throughput-driven stencil planning for E-beam lithography}, booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014}, pages = {254--261}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ICCAD.2014.7001360}, doi = {10.1109/ICCAD.2014.7001360}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/0001Y14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/YeungYC14, author = {Ho Chuen Jackson Yeung and Evangeline F. Y. Young and Chiu{-}sing Choy}, title = {Reducing pin count on cross-referencing Digital Microfluidic Biochip}, booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014, Melbourne, Victoria, Australia, June 1-5, 2014}, pages = {790--793}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ISCAS.2014.6865254}, doi = {10.1109/ISCAS.2014.6865254}, timestamp = {Wed, 09 Feb 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iscas/YeungYC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/Chow0HCY14, author = {Wing{-}Kai Chow and Jian Kuang and Xu He and Wenzan Cai and Evangeline F. Y. Young}, editor = {Cliff C. N. Sze and Azadeh Davoodi}, title = {Cell density-driven detailed placement with displacement constraint}, booktitle = {International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014}, pages = {3--10}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2560519.2560523}, doi = {10.1145/2560519.2560523}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/Chow0HCY14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/0001Y14, author = {Jian Kuang and Evangeline F. Y. Young}, editor = {Cliff C. N. Sze and Azadeh Davoodi}, title = {A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters}, booktitle = {International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014}, pages = {109--116}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2560519.2560521}, doi = {10.1145/2560519.2560521}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/0001Y14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isvlsi/CaiY14, author = {Wenzan Cai and Evangeline F. Y. Young}, title = {A Fast Hypergraph Bipartitioning Algorithm}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2014, Tampa, FL, USA, July 9-11, 2014}, pages = {607--612}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/ISVLSI.2014.58}, doi = {10.1109/ISVLSI.2014.58}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/CaiY14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jnca/XiongZLY13, author = {Junjie Xiong and Yangfan Zhou and Michael R. Lyu and Evan F. Y. Young}, title = {MDiag: Mobility-assisted diagnosis for wireless sensor networks}, journal = {J. Netw. Comput. Appl.}, volume = {36}, number = {1}, pages = {167--177}, year = {2013}, url = {https://doi.org/10.1016/j.jnca.2012.09.008}, doi = {10.1016/J.JNCA.2012.09.008}, timestamp = {Mon, 24 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/jnca/XiongZLY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangY13, author = {Tao Huang and Evangeline F. Y. Young}, title = {ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {32}, number = {6}, pages = {882--893}, year = {2013}, url = {https://doi.org/10.1109/TCAD.2013.2238291}, doi = {10.1109/TCAD.2013.2238291}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuangY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HeHXTY13, author = {Xu He and Tao Huang and Linfu Xiao and Haitong Tian and Evangeline F. Y. Young}, title = {Ripple: {A} Robust and Effective Routability-Driven Placer}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {32}, number = {10}, pages = {1546--1556}, year = {2013}, url = {https://doi.org/10.1109/TCAD.2013.2265371}, doi = {10.1109/TCAD.2013.2265371}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HeHXTY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/KuangY13, author = {Jian Kuang and Evangeline F. Y. Young}, title = {An efficient layout decomposition approach for triple patterning lithography}, booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin, TX, USA, May 29 - June 07, 2013}, pages = {69:1--69:6}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2463209.2488818}, doi = {10.1145/2463209.2488818}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/KuangY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/HeHCKLCY13, author = {Xu He and Tao Huang and Wing{-}Kai Chow and Jian Kuang and Ka{-}Chun Lam and Wenzan Cai and Evangeline F. Y. Young}, title = {Ripple 2.0: high quality routability-driven placement via global router integration}, booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin, TX, USA, May 29 - June 07, 2013}, pages = {152:1--152:6}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2463209.2488922}, doi = {10.1145/2463209.2488922}, timestamp = {Mon, 06 Jan 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/HeHCKLCY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/HeCY13, author = {Xu He and Wing{-}Kai Chow and Evangeline F. Y. Young}, editor = {Cheng{-}Kok Koh and Cliff C. N. Sze}, title = {{SRP:} simultaneous routing and placement for congestion refinement}, booktitle = {International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013}, pages = {108--113}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2451916.2451943}, doi = {10.1145/2451916.2451943}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/HeCY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TianTYS12, author = {Haitong Tian and Wai{-}Chung Tang and Evangeline F. Y. Young and Cliff C. N. Sze}, title = {Postgrid Clock Routing for High Performance Microprocessor Designs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {31}, number = {2}, pages = {255--259}, year = {2012}, url = {https://doi.org/10.1109/TCAD.2011.2170688}, doi = {10.1109/TCAD.2011.2170688}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TianTYS12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/LeungCY12, author = {Mario K. Y. Leung and Eric K. I. Chio and Evangeline F. Y. Young}, title = {Postplacement Voltage Island Generation}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {17}, number = {1}, pages = {4:1--4:15}, year = {2012}, url = {https://doi.org/10.1145/2071356.2071360}, doi = {10.1145/2071356.2071360}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/LeungCY12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/QianTY12, author = {Fuqiang Qian and Haitong Tian and Evangeline F. Y. Young}, editor = {Erik Brunvard and Ken Stevens and Joseph R. Cavallaro and Tong Zhang}, title = {Crosslink insertion for variation-driven clock network construction}, booktitle = {Great Lakes Symposium on {VLSI} 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012}, pages = {321--326}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2206781.2206860}, doi = {10.1145/2206781.2206860}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/QianTY12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/HuangY12, author = {Tao Huang and Evangeline F. Y. Young}, editor = {Alan J. Hu}, title = {Construction of rectilinear Steiner minimum trees with slew constraints over obstacles}, booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012}, pages = {144--151}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2429384.2429411}, doi = {10.1145/2429384.2429411}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/HuangY12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MaXTY11, author = {Qiang Ma and Linfu Xiao and Yiu{-}Cheong Tam and Evangeline F. Y. Young}, title = {Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {1}, pages = {85--95}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2010.2064490}, doi = {10.1109/TCAD.2010.2064490}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MaXTY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangZCYCG11, author = {Renshen Wang and Yulei Zhang and Nan{-}Chi Chou and Evangeline F. Y. Young and Chung{-}Kuan Cheng and Ronald L. Graham}, title = {Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {2}, pages = {167--179}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2010.2097170}, doi = {10.1109/TCAD.2010.2097170}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangZCYCG11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangLY11, author = {Tao Huang and Liang Li and Evangeline F. Y. Young}, title = {On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {5}, pages = {718--731}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2010.2098930}, doi = {10.1109/TCAD.2010.2098930}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuangLY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/XiaoY11, author = {Zigang Xiao and Evangeline F. Y. Young}, title = {Placement and Routing for Cross-Referencing Digital Microfluidic Biochips}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {7}, pages = {1000--1010}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2011.2113730}, doi = {10.1109/TCAD.2011.2113730}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/XiaoY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MaQYZ11, author = {Qiang Ma and Zaichen Qian and Evangeline F. Y. Young and Hai Zhou}, title = {MSV-Driven Floorplanning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {8}, pages = {1152--1162}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2011.2131890}, doi = {10.1109/TCAD.2011.2131890}, timestamp = {Wed, 16 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MaQYZ11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/MaKWY11, author = {Qiang Ma and Hui Kong and Martin D. F. Wong and Evangeline F. Y. Young}, title = {A provably good approximation algorithm for Rectangle Escape Problem with application to {PCB} routing}, booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference, {ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011}, pages = {843--848}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/ASPDAC.2011.5722308}, doi = {10.1109/ASPDAC.2011.5722308}, timestamp = {Fri, 06 Oct 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/MaKWY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/HuangY11, author = {Tao Huang and Evangeline F. Y. Young}, editor = {Leon Stok and Nikil D. Dutt and Soha Hassoun}, title = {An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles}, booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011, San Diego, California, USA, June 5-10, 2011}, pages = {164--169}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2024724.2024762}, doi = {10.1145/2024724.2024762}, timestamp = {Mon, 06 Jan 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/HuangY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/MaYW11, author = {Qiang Ma and Evangeline F. Y. Young and Martin D. F. Wong}, editor = {Leon Stok and Nikil D. Dutt and Soha Hassoun}, title = {An optimal algorithm for layer assignment of bus escape routing on PCBs}, booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011, San Diego, California, USA, June 5-10, 2011}, pages = {176--181}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/2024724.2024764}, doi = {10.1145/2024724.2024764}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/MaYW11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/YeungYL11, author = {Jackson H. C. Yeung and Evangeline F. Y. Young and Philip Heng Wai Leong}, editor = {John Wawrzynek and Katherine Compton}, title = {A monte-carlo floating-point unit for self-validating arithmetic}, booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA, February 27, March 1, 2011}, pages = {199--208}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/1950413.1950453}, doi = {10.1145/1950413.1950453}, timestamp = {Tue, 29 Dec 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/YeungYL11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/HeHXTCY11, author = {Xu He and Tao Huang and Linfu Xiao and Haitong Tian and Guxin Cui and Evangeline F. Y. Young}, editor = {Joel R. Phillips and Alan J. Hu and Helmut Graeb}, title = {Ripple: An effective routability-driven placer by iterative cell movement}, booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2011, San Jose, California, USA, November 7-10, 2011}, pages = {74--79}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ICCAD.2011.6105308}, doi = {10.1109/ICCAD.2011.6105308}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/HeHXTCY11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/TianTYS11, author = {Haitong Tian and Wai{-}Chung Tang and Evangeline F. Y. Young and Cliff C. N. Sze}, editor = {Yao{-}Wen Chang and Jiang Hu}, title = {Grid-to-ports clock routing for high performance microprocessor designs}, booktitle = {Proceedings of the 2011 International Symposium on Physical Design, {ISPD} 2011, Santa Barbara, California, USA, March 27-30, 2011}, pages = {21--28}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/1960397.1960406}, doi = {10.1145/1960397.1960406}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/TianTYS11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/0002Y10, author = {Qiang Ma and Evangeline F. Y. Young}, title = {Multivoltage Floorplan Design}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {29}, number = {4}, pages = {607--617}, year = {2010}, url = {https://doi.org/10.1109/TCAD.2010.2042895}, doi = {10.1109/TCAD.2010.2042895}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/0002Y10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/WangYC10, author = {Renshen Wang and Evangeline F. Y. Young and Chung{-}Kuan Cheng}, title = {Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {15}, number = {4}, pages = {33:1--33:22}, year = {2010}, url = {https://doi.org/10.1145/1835420.1835426}, doi = {10.1145/1835420.1835426}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/WangYC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/XiaoY10, author = {Zigang Xiao and Evangeline F. Y. Young}, title = {CrossRouter: a droplet router for cross-referencing digital microfluidic biochips}, booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010}, pages = {269--274}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ASPDAC.2010.5419884}, doi = {10.1109/ASPDAC.2010.5419884}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/XiaoY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/LuCSY10, author = {Jingwei Lu and Wing{-}Kai Chow and Chiu{-}Wing Sham and Evangeline F. Y. Young}, title = {A dual-MST approach for clock network synthesis}, booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010}, pages = {467--473}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ASPDAC.2010.5419838}, doi = {10.1109/ASPDAC.2010.5419838}, timestamp = {Thu, 01 Jun 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/LuCSY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/XiaoSXY10, author = {Linfu Xiao and Subarna Sinha and Jingyu Xu and Evangeline F. Y. Young}, title = {Fixed-outline thermal-aware 3D floorplanning}, booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010}, pages = {561--567}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ASPDAC.2010.5419822}, doi = {10.1109/ASPDAC.2010.5419822}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/XiaoSXY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/XiaoXQJHTY10, author = {Linfu Xiao and Zigang Xiao and Zaichen Qian and Yan Jiang and Tao Huang and Haitong Tian and Evangeline F. Y. Young}, editor = {Louis Scheffer and Joel R. Phillips and Alan J. Hu}, title = {Local clock skew minimization using blockage-aware mixed tree-mesh clock network}, booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010, San Jose, CA, USA, November 7-11, 2010}, pages = {458--462}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ICCAD.2010.5653732}, doi = {10.1109/ICCAD.2010.5653732}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/XiaoXQJHTY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/HuangY10, author = {Tao Huang and Evangeline F. Y. Young}, editor = {Louis Scheffer and Joel R. Phillips and Alan J. Hu}, title = {Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach}, booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010, San Jose, CA, USA, November 7-11, 2010}, pages = {610--613}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ICCAD.2010.5654220}, doi = {10.1109/ICCAD.2010.5654220}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/HuangY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/XiaoYHP10, author = {Linfu Xiao and Evangeline F. Y. Young and Xiao{-}Yong He and Kong{-}Pang Pun}, editor = {Louis Scheffer and Joel R. Phillips and Alan J. Hu}, title = {Practical placement and routing techniques for analog circuit designs}, booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010, San Jose, CA, USA, November 7-11, 2010}, pages = {675--679}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ICCAD.2010.5654239}, doi = {10.1109/ICCAD.2010.5654239}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/XiaoYHP10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/WangYGC10, author = {Renshen Wang and Evangeline F. Y. Young and Ronald L. Graham and Chung{-}Kuan Cheng}, editor = {Prashant Saxena and Yao{-}Wen Chang}, title = {Physical synthesis of bus matrix for high bandwidth low power on-chip communications}, booktitle = {Proceedings of the 2010 International Symposium on Physical Design, {ISPD} 2010, San Francisco, California, USA, March 14-17, 2010}, pages = {91--96}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1735023.1735049}, doi = {10.1145/1735023.1735049}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/WangYGC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/XiaoY10, author = {Zigang Xiao and Evangeline F. Y. Young}, editor = {Prashant Saxena and Yao{-}Wen Chang}, title = {Droplet-routing-aware module placement for cross-referencing biochips}, booktitle = {Proceedings of the 2010 International Symposium on Physical Design, {ISPD} 2010, San Francisco, California, USA, March 14-17, 2010}, pages = {193--199}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1735023.1735067}, doi = {10.1145/1735023.1735067}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/XiaoY10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/ShamY09, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young}, title = {Block flipping and white space distribution for wirelength minimization}, journal = {Integr.}, volume = {42}, number = {2}, pages = {246--253}, year = {2009}, url = {https://doi.org/10.1016/j.vlsi.2008.08.001}, doi = {10.1016/J.VLSI.2008.08.001}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/ShamY09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/LaiYC09, author = {Steve T. W. Lai and Evangeline F. Y. Young and Chris C. N. Chu}, title = {Handling routability in floorplan design with twin binary trees}, journal = {Integr.}, volume = {42}, number = {4}, pages = {449--456}, year = {2009}, url = {https://doi.org/10.1016/j.vlsi.2009.03.001}, doi = {10.1016/J.VLSI.2009.03.001}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/LaiYC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/ShamYL09, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young and Jingwei Lu}, title = {Congestion prediction in early stages of physical design}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {14}, number = {1}, pages = {12:1--12:18}, year = {2009}, url = {https://doi.org/10.1145/1455229.1455241}, doi = {10.1145/1455229.1455241}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/ShamYL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/XiaoY09, author = {Linfu Xiao and Evangeline F. Y. Young}, editor = {Kazutoshi Wakabayashi}, title = {Analog placement with common centroid and 1-D symmetry constraints}, booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference, {ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009}, pages = {353--360}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ASPDAC.2009.4796506}, doi = {10.1109/ASPDAC.2009.4796506}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/XiaoY09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LiQY09, author = {Liang Li and Zaichen Qian and Evangeline F. Y. Young}, editor = {Jaijeet S. Roychowdhury}, title = {Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree}, booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009, San Jose, CA, USA, November 2-5, 2009}, pages = {21--25}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1687399.1687405}, doi = {10.1145/1687399.1687405}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/LiQY09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/ZaichenY09, author = {Zaichen Qian and Evangeline F. Y. Young}, editor = {Gi{-}Joon Nam and Prashant Saxena}, title = {Multi-voltage floorplan design with optimal voltage assignment}, booktitle = {Proceedings of the 2009 International Symposium on Physical Design, {ISPD} 2009, San Diego, California, USA, March 29 - April 1, 2009}, pages = {13--18}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1514932.1514937}, doi = {10.1145/1514932.1514937}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/ZaichenY09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/LawY08, author = {Jill H. Y. Law and Evangeline F. Y. Young}, title = {Multi-bend bus driven floorplanning}, journal = {Integr.}, volume = {41}, number = {2}, pages = {306--316}, year = {2008}, url = {https://doi.org/10.1016/j.vlsi.2007.09.002}, doi = {10.1016/J.VLSI.2007.09.002}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/LawY08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/ShamYZ08, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young and Hai Zhou}, title = {Optimizing wirelength and routability by searching alternative packings in floorplanning}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {13}, number = {1}, pages = {21:1--21:13}, year = {2008}, url = {https://doi.org/10.1145/1297666.1297687}, doi = {10.1145/1297666.1297687}, timestamp = {Wed, 16 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/todaes/ShamYZ08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/MaY08, author = {Tilen Ma and Evangeline F. Y. Young}, editor = {Chong{-}Min Kyung and Kiyoung Choi and Soonhoi Ha}, title = {TCG-based multi-bend bus driven floorplanning}, booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference, {ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008}, pages = {192--197}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/ASPDAC.2008.4483938}, doi = {10.1109/ASPDAC.2008.4483938}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/MaY08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/MaY08, author = {Qiang Ma and Evangeline F. Y. Young}, editor = {Sani R. Nassif and Jaijeet S. Roychowdhury}, title = {Network flow-based power optimization under timing constraints in MSV-driven floorplanning}, booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008, San Jose, CA, USA, November 10-13, 2008}, pages = {1--8}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCAD.2008.4681544}, doi = {10.1109/ICCAD.2008.4681544}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/MaY08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LiY08, author = {Liang Li and Evangeline F. Y. Young}, editor = {Sani R. Nassif and Jaijeet S. Roychowdhury}, title = {Obstacle-avoiding rectilinear Steiner tree construction}, booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008, San Jose, CA, USA, November 10-13, 2008}, pages = {523--528}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCAD.2008.4681625}, doi = {10.1109/ICCAD.2008.4681625}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/LiY08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/WangYZGGC08, author = {Renshen Wang and Evangeline F. Y. Young and Yi Zhu and Fan Chung Graham and Ronald L. Graham and Chung{-}Kuan Cheng}, editor = {David Z. Pan and Gi{-}Joon Nam}, title = {3-D floorplanning using labeled tree and dual sequences}, booktitle = {Proceedings of the 2008 International Symposium on Physical Design, {ISPD} 2008, Portland, Oregon, USA, April 13-16, 2008}, pages = {54--59}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1353629.1353641}, doi = {10.1145/1353629.1353641}, timestamp = {Thu, 25 Jul 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/WangYZGGC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:reference/algo/Young08b, author = {Evangeline F. Y. Young}, editor = {Ming{-}Yang Kao}, title = {Slicing Floorplan Orientation}, booktitle = {Encyclopedia of Algorithms - 2008 Edition}, publisher = {Springer}, year = {2008}, url = {https://doi.org/10.1007/978-0-387-30162-4\_379}, doi = {10.1007/978-0-387-30162-4\_379}, timestamp = {Thu, 27 Jun 2019 16:25:31 +0200}, biburl = {https://dblp.org/rec/reference/algo/Young08b.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:reference/crc/KohYC08, author = {Cheng{-}Kok Koh and Evangeline F. Y. Young and Yao{-}Wen Chang}, editor = {Charles J. Alpert and Dinesh P. Mehta and Sachin S. Sapatnekar}, title = {Global Interconnect Planning}, booktitle = {Handbook of Algorithms for Physical Design Automation}, publisher = {Auerbach Publications}, year = {2008}, url = {https://doi.org/10.1201/9781420013481.ch33}, doi = {10.1201/9781420013481.CH33}, timestamp = {Mon, 26 Oct 2020 09:04:39 +0100}, biburl = {https://dblp.org/rec/reference/crc/KohYC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@incollection{DBLP:reference/crc/Young08, author = {Evangeline F. Y. Young}, editor = {Charles J. Alpert and Dinesh P. Mehta and Sachin S. Sapatnekar}, title = {Floorplan Representations}, booktitle = {Handbook of Algorithms for Physical Design Automation}, publisher = {Auerbach Publications}, year = {2008}, url = {https://doi.org/10.1201/9781420013481.ch10}, doi = {10.1201/9781420013481.CH10}, timestamp = {Wed, 12 Jul 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/reference/crc/Young08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/iet-cdt/XuWIY07, author = {Qiang Xu and Baosheng Wang and Andr{\'{e}} Ivanov and Fung Yu Young}, title = {Test scheduling for built-in self-tested embedded SRAMs with data retention faults}, journal = {{IET} Comput. Digit. Tech.}, volume = {1}, number = {3}, pages = {256--264}, year = {2007}, url = {https://doi.org/10.1049/iet-cdt:20060128}, doi = {10.1049/IET-CDT:20060128}, timestamp = {Thu, 30 Mar 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/iet-cdt/XuWIY07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TongYCD07, author = {Dennis K. Y. Tong and Evangeline F. Y. Young and Chris C. N. Chu and Sampath Dechu}, title = {Wire Retiming Problem With Net Topology Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {26}, number = {9}, pages = {1648--1660}, year = {2007}, url = {https://doi.org/10.1109/TCAD.2007.895583}, doi = {10.1109/TCAD.2007.895583}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TongYCD07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/ShamY07, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young}, title = {Area reduction by deadspace utilization on interconnect optimized floorplan}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {12}, number = {1}, pages = {3:1--3:11}, year = {2007}, url = {https://doi.org/10.1145/1217088.1217091}, doi = {10.1145/1217088.1217091}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/todaes/ShamY07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/MaYP07, author = {Qiang Ma and Evangeline F. Y. Young and Kong{-}Pang Pun}, editor = {Georges G. E. Gielen}, title = {Analog placement with common centroid constraints}, booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007, San Jose, CA, USA, November 5-8, 2007}, pages = {579--585}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ICCAD.2007.4397327}, doi = {10.1109/ICCAD.2007.4397327}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/MaYP07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/MaY07, author = {Qiang Ma and Evangeline F. Y. Young}, editor = {Georges G. E. Gielen}, title = {Voltage island-driven floorplanning}, booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007, San Jose, CA, USA, November 5-8, 2007}, pages = {644--649}, publisher = {{IEEE} Computer Society}, year = {2007}, url = {https://doi.org/10.1109/ICCAD.2007.4397338}, doi = {10.1109/ICCAD.2007.4397338}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/MaY07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/ShamYC06, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young and Chris C. N. Chu}, editor = {Ellen Sentovich}, title = {Optimal cell flipping in placement and floorplanning}, booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006, San Francisco, CA, USA, July 24-28, 2006}, pages = {1109--1114}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1146909.1147189}, doi = {10.1145/1146909.1147189}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/ShamYC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ets/XuWY06, author = {Qiang Xu and Baosheng Wang and F. Y. Young}, title = {Retention-Aware Test Scheduling for BISTed Embedded SRAMs}, booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24, 2006}, pages = {83--88}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/ETS.2006.40}, doi = {10.1109/ETS.2006.40}, timestamp = {Thu, 30 Mar 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ets/XuWY06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/ChingY06, author = {Royce L. S. Ching and Evangeline F. Y. Young}, editor = {Gang Qu and Yehea I. Ismail and Narayanan Vijaykrishnan and Hai Zhou}, title = {Shuttle mask floorplanning with modified alpha-restricted grid}, booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006, Philadelphia, PA, USA, April 30 - May 1, 2006}, pages = {85--90}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1127908.1127930}, doi = {10.1145/1127908.1127930}, timestamp = {Wed, 16 Aug 2023 21:16:32 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/ChingY06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/LawYC06, author = {Jill H. Y. Law and Evangeline F. Y. Young and Royce L. S. Ching}, editor = {Gang Qu and Yehea I. Ismail and Narayanan Vijaykrishnan and Hai Zhou}, title = {Block alignment in 3D floorplan using layered {TCG}}, booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006, Philadelphia, PA, USA, April 30 - May 1, 2006}, pages = {376--380}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1127908.1127994}, doi = {10.1145/1127908.1127994}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/LawYC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/TamYC06, author = {Yiu{-}Cheong Tam and Evangeline F. Y. Young and Chris C. N. Chu}, editor = {Soha Hassoun}, title = {Analog placement with symmetry and other placement constraints}, booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006, San Jose, CA, USA, November 5-9, 2006}, pages = {349--354}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1233501.1233571}, doi = {10.1145/1233501.1233571}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/TamYC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChingYLC06, author = {Royce L. S. Ching and Evangeline F. Y. Young and Kevin C. K. Leung and Chris C. N. Chu}, editor = {Soha Hassoun}, title = {Post-placement voltage island generation}, booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006, San Jose, CA, USA, November 5-9, 2006}, pages = {641--646}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1233501.1233632}, doi = {10.1145/1233501.1233632}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChingYLC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/ShamY05, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young}, editor = {Tingao Tang}, title = {Congestion prediction in floorplanning}, booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation, {ASP-DAC} 2005, Shanghai, China, January 18-21, 2005}, pages = {1107--1110}, publisher = {{ACM} Press}, year = {2005}, url = {https://doi.org/10.1145/1120725.1120835}, doi = {10.1145/1120725.1120835}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/ShamY05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/LawY05, author = {Jill H. Y. Law and Evangeline F. Y. Young}, editor = {Patrick Groeneveld and Louis Scheffer}, title = {Multi-bend bus driven floorplanning}, booktitle = {Proceedings of the 2005 International Symposium on Physical Design, {ISPD} 2005, San Francisco, California, USA, April 3-6, 2005}, pages = {113--120}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1055137.1055162}, doi = {10.1145/1055137.1055162}, timestamp = {Tue, 06 Nov 2018 11:07:46 +0100}, biburl = {https://dblp.org/rec/conf/ispd/LawY05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/ShamY05, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young}, editor = {Igor L. Markov and Mike Hutton}, title = {Congestion prediction in early stages}, booktitle = {The Seventh International Workshop on System-Level Interconnect Prediction {(SLIP} 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings}, pages = {91--98}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1053355.1053376}, doi = {10.1145/1053355.1053376}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/ShamY05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChuY04, author = {Chris C. N. Chu and Evangeline F. Y. Young}, title = {Nonrectangular shaping and sizing of soft modules for floorplan-design improvement}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {23}, number = {1}, pages = {71--79}, year = {2004}, url = {https://doi.org/10.1109/TCAD.2003.819896}, doi = {10.1109/TCAD.2003.819896}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChuY04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/YoungCH04, author = {Evangeline F. Y. Young and Chris C. N. Chu and M. L. Ho}, title = {Placement constraints in floorplan design}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {12}, number = {7}, pages = {735--745}, year = {2004}, url = {https://doi.org/10.1109/TVLSI.2004.830915}, doi = {10.1109/TVLSI.2004.830915}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/YoungCH04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/TongY04, author = {Dennis K. Y. Tong and Evangeline F. Y. Young}, editor = {Charles J. Alpert and Patrick Groeneveld}, title = {Performance-driven register insertion in placement}, booktitle = {Proceedings of the 2004 International Symposium on Physical Design, {ISPD} 2004, Phoenix, Arizona, USA, April 18-21, 2004}, pages = {53--60}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/981066.981077}, doi = {10.1145/981066.981077}, timestamp = {Tue, 06 Nov 2018 11:07:46 +0100}, biburl = {https://dblp.org/rec/conf/ispd/TongY04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YoungCS03, author = {Evangeline F. Y. Young and Chris C. N. Chu and Zion Cien Shen}, title = {Twin binary sequences: a nonredundant representation for general nonslicing floorplan}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {22}, number = {4}, pages = {457--469}, year = {2003}, url = {https://doi.org/10.1109/TCAD.2003.809651}, doi = {10.1109/TCAD.2003.809651}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YoungCS03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ShamY03, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young}, title = {Routability-driven floorplanner with buffer block planning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {22}, number = {4}, pages = {470--480}, year = {2003}, url = {https://doi.org/10.1109/TCAD.2003.809649}, doi = {10.1109/TCAD.2003.809649}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ShamY03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YuenY03, author = {Wing Seung Yuen and Evangeline F. Y. Young}, title = {Slicing floorplan with clustering constraint}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {22}, number = {5}, pages = {652--658}, year = {2003}, url = {https://doi.org/10.1109/TCAD.2003.810738}, doi = {10.1109/TCAD.2003.810738}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YuenY03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MakY03, author = {Wai{-}Kei Mak and Evangeline F. Y. Young}, title = {Temporal logic replication for dynamically reconfigurable {FPGA} partitioning}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {22}, number = {7}, pages = {952--959}, year = {2003}, url = {https://doi.org/10.1109/TCAD.2003.814237}, doi = {10.1109/TCAD.2003.814237}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MakY03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/WongY03, author = {Keith W. C. Wong and Evangeline F. Y. Young}, editor = {Hiroto Yasuura}, title = {Fast buffer planning and congestion optimization in interconnect-driven floorplanning}, booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference, {ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003}, pages = {411--416}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/1119772.1119854}, doi = {10.1145/1119772.1119854}, timestamp = {Thu, 11 Mar 2021 17:04:51 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/WongY03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/ShamYZ03, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young and Hai Zhou}, editor = {Hiroto Yasuura}, title = {Interconnect-driven floorplanning by searching alternative packings}, booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference, {ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003}, pages = {417--422}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/1119772.1119855}, doi = {10.1145/1119772.1119855}, timestamp = {Wed, 16 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/ShamYZ03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LaiYC03, author = {Steve T. W. Lai and Evangeline F. Y. Young and Chris C. N. Chu}, title = {A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees}, booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2003), 3-7 March 2003, Munich, Germany}, pages = {10856--10861}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10086}, doi = {10.1109/DATE.2003.10086}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/LaiYC03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/WongYM03, author = {Eric S. H. Wong and Evangeline F. Y. Young and Wai{-}Kei Mak}, editor = {Mircea R. Stan and David Garrett and Kazuo Nakajima}, title = {Clustering based acyclic multi-way partitioning}, booktitle = {Proceedings of the 13th {ACM} Great Lakes Symposium on {VLSI} 2003, Washington, DC, USA, April 28-29, 2003}, pages = {203--206}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/764808.764860}, doi = {10.1145/764808.764860}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/WongYM03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChuYTD03, author = {Chris C. N. Chu and Evangeline F. Y. Young and Dennis K. Y. Tong and Sampath Dechu}, title = {Retiming with Interconnect and Gate Delay}, booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003, San Jose, CA, USA, November 9-13, 2003}, pages = {221--226}, publisher = {{IEEE} Computer Society / {ACM}}, year = {2003}, url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257648}, doi = {10.1109/ICCAD.2003.1257648}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChuYTD03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/WongSY02, author = {Wai{-}Chiu Wong and Chiu{-}Wing Sham and Evangeline F. Y. Young}, title = {Congestion Estimation with Buffer Planning in Floorplan Design}, booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2002), 4-8 March 2002, Paris, France}, pages = {696--701}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/DATE.2002.998375}, doi = {10.1109/DATE.2002.998375}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/WongSY02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ChuY02, author = {Chris C. N. Chu and Evangeline F. Y. Young}, title = {Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design}, booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2002), 4-8 March 2002, Paris, France}, pages = {1101}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/DATE.2002.998457}, doi = {10.1109/DATE.2002.998457}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ChuY02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/ShamY02, author = {Chiu{-}Wing Sham and Evangeline F. Y. Young}, editor = {Sachin S. Sapatnekar and Massoud Pedram}, title = {Routability driven floorplanner with buffer block planning}, booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD} 2002, Del Mar, CA, USA, April 7-10, 2002}, pages = {50--55}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/505388.505402}, doi = {10.1145/505388.505402}, timestamp = {Tue, 06 Nov 2018 11:07:47 +0100}, biburl = {https://dblp.org/rec/conf/ispd/ShamY02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/MakY02, author = {Wai{-}Kei Mak and Evangeline F. Y. Young}, editor = {Sachin S. Sapatnekar and Massoud Pedram}, title = {Temporal logic replication for dynamically reconfigurable {FPGA} partitioning}, booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD} 2002, Del Mar, CA, USA, April 7-10, 2002}, pages = {190--195}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/505388.505434}, doi = {10.1145/505388.505434}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/MakY02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/YoungCS02, author = {Evangeline F. Y. Young and Chris C. N. Chu and Zion Cien Shen}, editor = {Sachin S. Sapatnekar and Massoud Pedram}, title = {Twin binary sequences: a non-redundant representation for general non-slicing floorplan}, booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD} 2002, Del Mar, CA, USA, April 7-10, 2002}, pages = {196--201}, publisher = {{ACM}}, year = {2002}, url = {https://doi.org/10.1145/505388.505435}, doi = {10.1145/505388.505435}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ispd/YoungCS02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/YoungCH02, author = {Evangeline F. Y. Young and Chris C. N. Chu and M. L. Ho}, title = {A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design}, booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference {(ASP-DAC} 2002), and the 15th International Conference on {VLSI} Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002}, pages = {661}, publisher = {{IEEE} Computer Society}, year = {2002}, url = {https://doi.org/10.1109/ASPDAC.2002.995011}, doi = {10.1109/ASPDAC.2002.995011}, timestamp = {Mon, 14 Nov 2022 15:28:09 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/YoungCH02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YoungCLW01, author = {Evangeline F. Y. Young and Chris C. N. Chu and W. S. Luk and Y. C. Wong}, title = {Handling soft modules in general nonslicing floorplan usingLagrangian relaxation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {20}, number = {5}, pages = {687--692}, year = {2001}, url = {https://doi.org/10.1109/43.920707}, doi = {10.1109/43.920707}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YoungCLW01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YoungWY01, author = {Evangeline F. Y. Young and Martin D. F. Wong and Hannah Honghua Yang}, title = {On extending slicing floorplan to handle L/T-shaped modules andabutment constraints}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {20}, number = {6}, pages = {800--807}, year = {2001}, url = {https://doi.org/10.1109/43.924833}, doi = {10.1109/43.924833}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YoungWY01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/YuenY01, author = {Wing Seung Yuen and Fung Yu Young}, editor = {Satoshi Goto}, title = {Slicing floorplan with clustering constraints}, booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan}, pages = {503--508}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/370155.370520}, doi = {10.1145/370155.370520}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/YuenY01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YoungWY00, author = {Evangeline F. Y. Young and Martin D. F. Wong and Hannah Honghua Yang}, title = {Slicing floorplans with range constraint}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {19}, number = {2}, pages = {272--278}, year = {2000}, url = {https://doi.org/10.1109/43.828556}, doi = {10.1109/43.828556}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YoungWY00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/YoungCLW00, author = {Fung Yu Young and Chris C. N. Chu and W. S. Luk and Y. C. Wong}, editor = {Manfred Wiesel and Dwight D. Hill}, title = {Floorplan area minimization using Lagrangian relaxation}, booktitle = {Proceedings of the 2000 International Symposium on Physical Design, {ISPD} 2000, San Diego, CA, USA, April 9-12, 2000}, pages = {174--179}, publisher = {{ACM}}, year = {2000}, url = {https://doi.org/10.1145/332357.332396}, doi = {10.1145/332357.332396}, timestamp = {Thu, 26 Aug 2021 17:11:38 +0200}, biburl = {https://dblp.org/rec/conf/ispd/YoungCLW00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jacm/YoungCW99, author = {Fung Yu Young and Chris C. N. Chu and D. F. Wong}, title = {Generation of Universal Series-Parallel Boolean Functions}, journal = {J. {ACM}}, volume = {46}, number = {3}, pages = {416--435}, year = {1999}, url = {https://doi.org/10.1145/316542.316551}, doi = {10.1145/316542.316551}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jacm/YoungCW99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YoungWY99, author = {Evangeline F. Y. Young and Martin D. F. Wong and Hannah Honghua Yang}, title = {Slicing floorplans with boundary constraints}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {18}, number = {9}, pages = {1385--1389}, year = {1999}, url = {https://doi.org/10.1109/43.784129}, doi = {10.1109/43.784129}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YoungWY99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/aspdac/YoungW99, author = {Fung Yu Young and D. F. Wong}, title = {Slicing Floorplans with Boundary Constraint}, booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999}, pages = {17--20}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ASPDAC.1999.759699}, doi = {10.1109/ASPDAC.1999.759699}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/aspdac/YoungW99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChenZYWYS99, author = {Hung{-}Ming Chen and Hai Zhou and Fung Yu Young and D. F. Wong and Hannah Honghua Yang and Naveed A. Sherwani}, editor = {Jacob K. White and Ellen Sentovich}, title = {Integrated floorplanning and interconnect planning}, booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999}, pages = {354--357}, publisher = {{IEEE} Computer Society}, year = {1999}, url = {https://doi.org/10.1109/ICCAD.1999.810674}, doi = {10.1109/ICCAD.1999.810674}, timestamp = {Wed, 16 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iccad/ChenZYWYS99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/YoungW99, author = {Fung Yu Young and D. F. Wong}, editor = {D. F. Wong}, title = {Slicing floorplans with range constraint}, booktitle = {Proceedings of the 1999 International Symposium on Physical Design, {ISPD} 1999, Monterey, CA, USA, April 12-14, 1999}, pages = {97--102}, publisher = {{ACM}}, year = {1999}, url = {https://doi.org/10.1145/299996.300033}, doi = {10.1145/299996.300033}, timestamp = {Sun, 02 Oct 2022 16:10:02 +0200}, biburl = {https://dblp.org/rec/conf/ispd/YoungW99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/YoungW98, author = {Fung Yu Young and D. F. Wong}, editor = {Hiroto Yasuura}, title = {Slicing floorplans with pre-placed modules}, booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998}, pages = {252--258}, publisher = {{ACM} / {IEEE} Computer Society}, year = {1998}, url = {https://doi.org/10.1145/288548.288622}, doi = {10.1145/288548.288622}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/YoungW98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/YoungW97, author = {F. Y. Young and D. F. Wong}, title = {How good are slicing floorplans?}, journal = {Integr.}, volume = {23}, number = {1}, pages = {61--73}, year = {1997}, url = {https://doi.org/10.1016/S0167-9260(97)00014-X}, doi = {10.1016/S0167-9260(97)00014-X}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/integration/YoungW97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/YoungW97, author = {Fung Yu Young and D. F. Wong}, title = {On the Construction of Universal Series-Parallel Functions for Logic Module Design}, booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI} in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA, October 12-15, 1997}, pages = {482--488}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/ICCD.1997.628912}, doi = {10.1109/ICCD.1997.628912}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/YoungW97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ispd/YoungW97, author = {Fung Yu Young and D. F. Wong}, editor = {Andrew B. Kahng and Majid Sarrafzadeh}, title = {How good are slicing floorplans?}, booktitle = {Proceedings of the 1997 International Symposium on Physical Design, {ISPD} 1997, Napa Valley, California, USA, April 14-16, 1997}, pages = {144--149}, publisher = {{ACM}}, year = {1997}, url = {https://doi.org/10.1145/267665.267705}, doi = {10.1145/267665.267705}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/ispd/YoungW97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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