BibTeX records: David E. Lackey

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@inproceedings{DBLP:conf/itc/KellerCFCMSILG10,
  author    = {Brion L. Keller and
               Krishna Chakravadhanula and
               Brian Foutz and
               Vivek Chickermane and
               R. Malneedi and
               Thomas J. Snethen and
               Vikram Iyengar and
               David E. Lackey and
               Gary Grise},
  title     = {Low cost at-speed testing using On-Product Clock Generation compatible
               with test compression},
  booktitle = {{ITC}},
  pages     = {724--733},
  publisher = {{IEEE} Computer Society},
  year      = {2010}
}
@inproceedings{DBLP:conf/iccad/IyengarXVZLHV07,
  author    = {Vikram Iyengar and
               Jinjun Xiong and
               Subbayyan Venkatesan and
               Vladimir Zolotov and
               David E. Lackey and
               Peter A. Habitz and
               Chandu Visweswariah},
  title     = {Variation-aware performance verification using at-speed structural
               test and statistical timing},
  booktitle = {{ICCAD}},
  pages     = {405--412},
  publisher = {{IEEE} Computer Society},
  year      = {2007}
}
@inproceedings{DBLP:conf/vts/IyengarPFWLGTDO07,
  author    = {Vikram Iyengar and
               Kenneth Pichamuthu and
               Andrew Ferko and
               Frank Woytowich and
               David E. Lackey and
               Gary Grise and
               Mark Taylor and
               Mike Degregorio and
               Steven F. Oakland},
  title     = {An Integrated Framework for At-Speed and ATE-Driven Delay Test of
               Contract-Manufactured ASICs},
  booktitle = {{VTS}},
  pages     = {173--178},
  publisher = {{IEEE} Computer Society},
  year      = {2007}
}
@inproceedings{DBLP:conf/itc/Lackey06,
  author    = {David E. Lackey},
  title     = {Efficient Latch and Clock Structures for System-on-Chip Test Flexibility},
  booktitle = {{ITC}},
  pages     = {1--7},
  publisher = {{IEEE} Computer Society},
  year      = {2006}
}
@inproceedings{DBLP:conf/aspdac/KoehlLD03,
  author    = {J{\"{u}}rgen Koehl and
               David E. Lackey and
               George W. Doerre},
  title     = {IBM's 50 Million gate ASICs},
  booktitle = {{ASP-DAC}},
  pages     = {628--634},
  publisher = {{ACM}},
  year      = {2003}
}
@inproceedings{DBLP:conf/dac/LackeyZK03,
  author    = {David E. Lackey and
               Paul S. Zuchowski and
               J{\"{u}}rgen Koehl},
  title     = {Designing mega-ASICs in nanogate technologies},
  booktitle = {{DAC}},
  pages     = {770--775},
  publisher = {{ACM}},
  year      = {2003}
}
@article{DBLP:journals/ibmrd/DoerreL02,
  author    = {George W. Doerre and
               David E. Lackey},
  title     = {The {IBM} ASIC/SoC methodology - {A} recipe for first-time success},
  journal   = {{IBM} Journal of Research and Development},
  volume    = {46},
  number    = {6},
  pages     = {649--660},
  year      = {2002}
}
@inproceedings{DBLP:conf/iccad/LackeyZBSGC02,
  author    = {David E. Lackey and
               Paul S. Zuchowski and
               Thomas R. Bednar and
               Douglas W. Stout and
               Scott W. Gould and
               John M. Cohn},
  title     = {Managing power and performance for System-on-Chip designs using Voltage
               Islands},
  booktitle = {{ICCAD}},
  pages     = {195--202},
  publisher = {{ACM} / {IEEE} Computer Society},
  year      = {2002}
}
@article{DBLP:journals/ibmrd/EngelGHLPPRRS96,
  author    = {James J. Engel and
               Thomas S. Guzowski and
               Anderson Hunt and
               David E. Lackey and
               Lansing D. Pickup and
               Robert A. Proctor and
               Karla Reynolds and
               Ann Marie Rincon and
               David R. Stauffer},
  title     = {Design methodology for {IBM} {ASIC} products},
  journal   = {{IBM} Journal of Research and Development},
  volume    = {40},
  number    = {4},
  pages     = {387--406},
  year      = {1996}
}
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