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Semantic ScholarPablo Ibáñez
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2010 – today
- 2019
[j12]Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé
, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera:
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distrib. Comput. 125: 31-44 (2019)- [j11]Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals:
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distrib. Comput. 125: 106-120 (2019) - [c16]Jose M. Herruzo, Sonia Gonzalez-Navarro, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, Oscar G. Plata:
Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. DCC 2019: 577 - [c15]Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals:
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA 2019: 5:1-5:8 - 2018
- [j10]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería:
Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. 61(6): 856-880 (2018) - 2016
- [j9]Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Pablo Ibáñez:
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. IEEE Trans. Computers 65(3): 755-769 (2016) - 2015
- [c14]Carl Christian Kjelgaard Mikkelsen, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Pablo García-Risueño:
Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints. PPAM (1) 2015: 160-171 - 2013
- [j8]Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José María Llabería:
Exploiting reuse locality on inclusive shared last-level caches. TACO 9(4): 38:1-38:19 (2013) - [c13]Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería:
The reuse cache: downsizing the shared last-level cache. MICRO 2013: 310-321 - 2012
- [j7]Benjamin Sahelices, Agustín De Dios Hernández, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería:
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. J. Comput. Sci. Technol. 27(1): 75-91 (2012) - [j6]Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería:
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. TACO 8(4): 19:1-19:20 (2012) - [i1]Pablo García-Risueño, Pablo E. Ibáñez:
A review of High Performance Computing foundations for scientists. CoRR abs/1205.5177 (2012) - 2011
- [j5]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instruction-Level Parallelism 13 (2011) - [j4]Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería:
Filtering directory lookups in CMPs. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 695-707 (2011) - [c12]Ana Bosque, Víctor Viñals, Pablo Ibáñez, José María Llabería:
Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) 2011: 269-281 - 2010
- [c11]Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería:
Filtering Directory Lookups in CMPs. DSD 2010: 207-216
2000 – 2009
- 2009
- [j3]Enrique F. Torres, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería:
Store Buffer Design for Multibanked Data Caches. IEEE Trans. Computers 58(10): 1307-1320 (2009) - [c10]Benjamin Sahelices, Pablo Ibáñez, Víctor Viñals, José María Llabería:
A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par 2009: 149-161 - 2008
- [c9]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Low-Cost Adaptive Data Prefetching. Euro-Par 2008: 327-336 - 2007
- [j2]Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Computer Architecture News 35(4): 37-44 (2007) - 2006
- [j1]Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals:
Software Demand, Hardware Supply. IEEE Micro 26(4): 72-82 (2006) - [c8]Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería:
Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484 - 2005
- [c7]Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería:
Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480 - 2004
- [c6]Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería:
Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524 - 2003
- [c5]Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería:
Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596 - 2001
- [c4]María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals:
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP 2001: 345-354 - 2000
- [c3]Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería:
Modeling load address behaviour through recurrences. ISPASS 2000: 101-108
1990 – 1999
- 1998
- [c2]Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán:
Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing 1998: 369-376 - 1996
- [c1]Pablo Ibáñez, Víctor Viñals:
Performance Assessment of Contents Management in Multilevel On-Chip Caches. EUROMICRO 1996: 431-440
Coauthor Index
aka: José M. Llabería
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