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2010 – today
- 2011
[c19]Jang-Ping Sheu, Chi-Yuan Lo, Wei-Kai Hu:
A Distributed Routing Protocol and Handover Schemes in Hybrid Vehicular Ad Hoc Networks. ICPADS 2011: 428-435
2000 – 2009
- 2009
- [c18]Yu-Chee Tseng, Chin-Hao Wu, Fang-Jing Wu, Chi-Fu Huang, Chung-Ta King, Chun-Yu Lin, Jang-Ping Sheu, Chun-Yu Chen, Chi-Yuan Lo, Chien-Wen Yang, Chi-Wen Deng:
A Wireless Human Motion Capturing System for Home Rehabilitation. Mobile Data Management 2009: 359-360 - 2001
- [c17]William H. Kao, Chi-Yuan Lo, Raminderpal Singh, Mark Basel:
Parasitic extraction: current state of the art and future trends. ISCAS (5) 2001: 487-490
1990 – 1999
- 1995
- [j7]So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
A cell-based hierarchical pitchmatching compaction using minimal LP. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 523-526 (1995) - [c16]Anoop Singhal, Chi-Yuan Lo:
Object oriented data modeling for VLSI/CAD. VLSI Design 1995: 25-29 - 1994
- [j6]Chi-Yuan Lo, Jirí Matousek, William L. Steiger:
Algorithms for Ham-Sandwich Cuts. Discrete & Computational Geometry 11: 433-452 (1994) - [j5]Shun-Lin Su, Charles H. Barry, Chi-Yuan Lo:
A space-efficient short-finding algorithm [VLSI layouts]. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1065-1068 (1994) - 1993
- [j4]Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu:
HS: a hierarchical search package for CAD data. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 1-5 (1993) - [c15]So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. DAC 1993: 395-400 - [c14]Anoop Singhal, Robert M. Arlein, Chi-Yuan Lo:
DDB: An Object Oriented Design Data Manager for VLSI CAD. SIGMOD Conference 1993: 467-470 - 1992
- [j3]Charles R. Bonapace, Chi-Yuan Lo:
An O(n log m) algorithm for VLSI design rule checking. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 753-758 (1992) - [c13]Chi-Yuan Lo, Jirí Matousek, William L. Steiger:
Ham-Sandwich Cuts in R^d. STOC 1992: 539-545 - 1991
- [c12]Debaprosad Dutt, Chi-Yuan Lo:
On Minimal Closure Constraint Generation for Symbolic Cell Assembly. DAC 1991: 736-739 - 1990
- [c11]Chi-Yuan Lo, Ravi Varadarajan:
An O(n1.5logn) 1-d Compaction Algorithm. DAC 1990: 382-387 - [c10]Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu:
HS: A Hierarchical Search Package for CAD Data. ICCAD 1990: 478-481
1980 – 1989
- 1989
- [j2]Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo:
Time-efficient VLSI artwork analysis algorithms in GOALIE2. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 640-648 (1989) - [c9]Chong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo:
GENAC: An Automatic Cell Synthesis Tool. DAC 1989: 239-244 - [c8]Hyunchul Shin, Chi-Yuan Lo:
An Efficient Two-Dimensional Layout Compaction Algorithm. DAC 1989: 290-295 - [c7]Chi-Yuan Lo:
Automatic Tub Region Generation for Symbolic Layout Compaction. DAC 1989: 302-306 - [c6]Charles R. Bonapace, Chi-Yuan Lo:
An O(nlogm) Algorithm for VLSI Design Rule Checking. DAC 1989: 503-507 - [c5]Anoop Singhal, Nishit P. Parikh, Debaprosad Dutt, Chi-Yuan Lo:
A data model and architecture for VLSI/CAD databases. ICCAD 1989: 276-279 - 1988
- [c4]Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo:
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. DAC 1988: 471-475 - 1987
- [j1]Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose:
Algorithms for an Advanced Fault Simulation System in MOTIS. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 232-240 (1987) - 1984
- [c3]Chin-Fu Chen, Chi-Yuan Lo, Hao N. Nham, Prasad Subramaniam:
The second generation motis mixed-mode simulator. DAC 1984: 10-17 - 1983
- [c2]Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose:
A data structure for MOS circuits. DAC 1983: 619-624 - 1982
- [c1]Ajoy K. Bose, Patrick Kozak, Chi-Yuan Lo, Hao N. Nham, Ernesto Pacas-Skewes, Kwok W. Wu:
A fault simulator for MOS LSI circuits. DAC 1982: 400-409
Coauthor Index
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