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2020 – today
- 2024
[j27]Hongji Fang
, Zhenguo Ma, Feng Yu, Bei Zhao, Bo Zhang:
Optimised Serial Commutator FFT Architecture in Terms of Multiplexers. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 445-449 (2024)- [j26]Zhenguo Ma, Yang Xu, Hongli Xu, Jianchun Liu, Yinxing Xue:
Like Attracts Like: Personalized Federated Learning in Decentralized Edge Computing. IEEE Trans. Mob. Comput. 23(2): 1080-1096 (2024) - [j25]Yang Xu, Zhenguo Ma, Hongli Xu, Suo Chen, Jianchun Liu, Yinxing Xue:
FedLC: Accelerating Asynchronous Federated Learning in Edge Computing. IEEE Trans. Mob. Comput. 23(5): 5327-5343 (2024) - 2023
- [j24]Zhenguo Ma, Yang Xu, Hongli Xu, Zeyu Meng, Liusheng Huang, Yinxing Xue:
Adaptive Batch Size for Federated Learning in Resource-Constrained Edge Computing. IEEE Trans. Mob. Comput. 22(1): 37-53 (2023) - [j23]Yang Xu, Yunming Liao, Hongli Xu, Zhenguo Ma, Lun Wang, Jianchun Liu:
Adaptive Control of Local Updating and Model Compression for Efficient Federated Learning. IEEE Trans. Mob. Comput. 22(10): 5675-5689 (2023) - [c3]Suo Chen, Zhenguo Ma, Zhiyuan Wang:
Accelerating Hierarchical Federated Learning with Adaptive Aggregation Frequency in Edge Computing. CNIOT 2023: 990-995 - 2022
- [j22]Bo Zhang, Zhenguo Ma, Wei Luo:
Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1627-1631 (2022) - [j21]Hongji Fang, Bo Zhang, Feng Yu, Bei Zhao, Zhenguo Ma:
A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4533-4537 (2022) - [j20]Qianhao Chen, Wenqi Wu, Haori Zheng, Bei Zhao, Zhenguo Ma, Weijie Chen:
Stream-Based Lossless Compression of Sensor Signals Using an Integer Adaptive Predictor. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 5194-5198 (2022) - 2021
- [j19]Jianchun Liu, Hongli Xu, Yang Xu, Zhenguo Ma, Zhiyuan Wang, Chen Qian, He Huang:
Communication-efficient asynchronous federated learning in resource-constrained edge computing. Comput. Networks 199: 108429 (2021) - [j18]Bo Zhang, Zhenguo Ma, Feng Yu:
A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1423-1427 (2021) - [c2]Xin Qi, Hongli Xu, Zhenguo Ma, Suo Chen:
Joint Network Selection and Task Offloading in Mobile Edge Computing. CCGRID 2021: 475-482 - 2020
- [j17]Ke Zang, Zhenguo Ma:
Automatic Modulation Classification Based on Hierarchical Recurrent Neural Networks With Grouped Auxiliary Memory. IEEE Access 8: 213052-213061 (2020) - [j16]Yatao Zhang, Zhenguo Ma, Wentao Dong:
Nonlinear Quality Indices Based on a Novel Lempel-Ziv Complexity for Assessing Quality of Multi-Lead ECGs Collected in Real Time. J. Inf. Process. Syst. 16(2): 508-521 (2020) - [j15]Chenpu Li, Qianjian Xing, Zhenguo Ma:
HKSiamFC: Visual-Tracking Framework Using Prior Information Provided by Staple and Kalman Filter. Sensors 20(7): 2137 (2020) - [j14]Meiting Xue, Qianjian Xing, Chen Feng, Feng Yu, Zhen-Guo Ma:
FPGA-Accelerated Hash Join Operation for Relational Databases. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1919-1923 (2020) - [j13]Wen-Qi Wu, Meiting Xue, Tian-Qi Zhu, Zhen-Guo Ma, Feng Yu:
High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA. IEEE Trans. Circuits Syst. 67-II(11): 2502-2506 (2020) - [j12]Chenpu Li, Qianjian Xing, Zhenguo Ma, Ke Zang:
MFCFSiam: A Correlation-Filter-Guided Siamese Network with Multifeature for Visual Tracking. Wirel. Commun. Mob. Comput. 2020: 6681391:1-6681391:19 (2020)
2010 – 2019
- 2019
- [j11]Huan Zhang, Bei Zhao, Wei-Jun Li, Zhen-Guo Ma, Feng Yu:
Resource-Efficient Parallel Tree-Based Join Architecture on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 111-115 (2019) - [j10]Yunxiang Wang, Zhen-guo Ma, Feng Yu:
Pipelined Algorithm and Modular Architecture for Matrix Transposition. IEEE Trans. Circuits Syst. II Express Briefs 66-II(4): 652-656 (2019) - [c1]Zhenguo Ma, Bingrui Chen, Yuan Xu, Yangxiao Li, Yatao Zhang:
Comparing Performance of Iterative and Non-Iterative Classifiers for 2-Lead ECGs on Multi-Feature Schemes. CISP-BMEI 2019: 1-6 - 2018
- [j9]Min Yuan, Qianjian Xing, Zhen-guo Ma, Feng Yu, Yingke Xu:
A Fused Continuous Floating-Point MAC on FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(9): 1594-1598 (2018) - 2017
- [j8]Qianjian Xing, Zhen-guo Ma, Feng Yu:
A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(6): 1333-1337 (2017) - [j7]Qianjian Xing, Zhen-guo Ma, Yingke Xu:
A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1347-1351 (2017) - [j6]Xiubin Mao, Zhen-guo Ma, Feng Yu, Qianjian Xing:
A Continuous-Flow Memory-Based Architecture for Real-Valued FFT. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1352-1356 (2017) - 2016
- [j5]Bei Zhao, Chen Cheng, Zhen-guo Ma, Feng Yu:
Time Delay Estimation via Co-Prime Aliased Sparse FFT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2566-2570 (2016) - [j4]Weijun Li, Feng Yu, Zhen-guo Ma:
Efficient Circuit for Parallel Bit Reversal. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 381-385 (2016) - [j3]Xiaobo Yin, Feng Yu, Zhen-guo Ma:
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 803-807 (2016) - 2015
- [j2]Zhen-guo Ma, Xiaobo Yin, Feng Yu:
A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 876-880 (2015) - 2011
- [j1]Zhen-guo Ma, Feng Yu, Rui-feng Ge, Ze-ke Wang:
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. J. Zhejiang Univ. Sci. C 12(4): 323-329 (2011)
Coauthor Index
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