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Seung-Ho Ok

Seung Ho Ok

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affiliation: Samsung ElectronicsHwaseong-si, South Korea
affiliation: Kyungpook National University, School of Electrical Engineering & Computer Science, Daegu, South Korea

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2010 – 2019

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2018
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Seung-Ho Ok, Jae Hoon Shim, Byungin Moon:
Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors. J. Supercomput. 74(12): 6665-6690 (2018)
2017
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  - journals/sensors/OkLSLM17
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Seung-Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon:
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors. Sensors 17(2): 426 (2017)
2013
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  - conf/islped/OkBLM13
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Seung-Ho Ok, Kyeong-Ryeol Bae, Sung Kyu Lim, Byungin Moon:
Design and analysis of 3D IC-based low power stereo matching processors. ISLPED 2013: 15-20
2011
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Kyeong-Ryeol Bae, Seung-Ho Ok, Hyeon-Sik Son, Sang Yoon Oh, Yong-Hwan Lee, Byungin Moon:
An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing. FGIT-FGCN (1) 2011: 136-146
[c6]
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Hyeon-Sik Son, Kyeong-Ryeol Bae, Seung-Ho Ok, Yong-Hwan Lee, Byungin Moon:
A Rectification Hardware Architecture for an Adaptive Multiple-Baseline Stereo Vision System. FGIT-FGCN (1) 2011: 147-155
2010
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Dong-Hwi Woo, Kyeong-Ryeol Bae, Hyeon-Sik Son, Seung-Ho Ok, Yong-Hwan Lee, Byungin Moon:
A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000. FGIT-FGCN (2) 2010: 343-346

2000 – 2009

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2009
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Seung Ho Ok, Woo-Jin Seo, Jin-Ho Ahn, Sungho Kang, Byung In Moon:
An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search. FGIT-FGCN 2009: 539-546
[c3]
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  - conf/ncm/SeoOAKM09
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Woo-Jin Seo, Seung Ho Ok, Jin-Ho Ahn, Sungho Kang, Byung In Moon:
An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine. NCM 2009: 1499-1502
2008
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Sang Gyun Kim, Woo Sik Kim, Seung Ho Ok, Byung In Moon:
High-Speed Priority Queue Architecture for Multiple Out Links. DELTA 2008: 410-414
2007
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  - conf/fgcn/OkM07
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Seung Ho Ok, Byung In Moon:
A Digit Reversal Circuit for the Variable-Length Radix-4 FFT. FGCN (2) 2007: 496-500

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