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ORCIDEric Qin 0001
Person information
- affiliation: Georgia Institute of Technology, School of Electrical and Computer Engineering, Atlanta, USA
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2020 – today
- 2023
[c8]Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya
, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. HPCA 2023: 259-272- [i6]Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. CoRR abs/2302.08687 (2023) - 2022
- [b1]Eric Qin:
Building Efficient Tensor Accelerators for Sparse and Irregular Workloads. Georgia Institute of Technology, Atlanta, GA, USA, 2022 - [c7]Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna:
Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. DAC 2022: 583-588 - [c6]Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna:
Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators. IPDPS 2022: 571-582 - [i5]Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna:
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity. CoRR abs/2201.08916 (2022) - 2021
- [j2]Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim:
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 605-616 (2021) - [c5]Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. DAC 2021: 253-258 - [c4]Eric Qin, Geonhwa Jeong, William Won, Sheng-Chun Kao, Hyoukjun Kwon, Sudarshan Srinivasan, Dipankar Das, Gordon Euhyun Moon, Sivasankaran Rajamanickam, Tushar Krishna:
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats. IPDPS 2021: 1014-1024 - [i4]Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna:
A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators. CoRR abs/2103.07977 (2021) - [i3]Eric Qin, Geonhwa Jeong, William Won, Sheng-Chun Kao, Hyoukjun Kwon, Sudarshan Srinivasan, Dipankar Das, Gordon Euhyun Moon, Sivasankaran Rajamanickam, Tushar Krishna:
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats. CoRR abs/2103.10452 (2021) - [i2]Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. CoRR abs/2110.01752 (2021) - 2020
- [j1]Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim:
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2424-2437 (2020) - [c3]Eric Qin, Ananda Samajdar, Hyoukjun Kwon, Vineet Nadella, Sudarshan Srinivasan, Dipankar Das, Bharat Kaul, Tushar Krishna:
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training. HPCA 2020: 58-70
2010 – 2019
- 2019
- [c2]Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim:
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. DAC 2019: 178 - [i1]Abhisek Kundu, Sudarshan Srinivasan, Eric C. Qin, Dhiraj D. Kalamkar, Naveen K. Mellempudi, Dipankar Das, Kunal Banerjee, Bharat Kaul, Pradeep Dubey:
K-TanH: Hardware Efficient Activations For Deep Learning. CoRR abs/1909.07729 (2019) - 2015
- [c1]Md Muztoba, Eric Qin, Nicholas Tran, Ümit Y. Ogras:
Context-aware control of smart objects via human-machine communication. BioCAS 2015: 1-4
Coauthor Index
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