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Semantic ScholarSanjay V. Rajopadhye
Sanjay Rajopadhye
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- affiliation: Colorado State University, USA
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2010 – today
- 2018
[j27]Yun Zou, Sanjay Rajopadhye
:
A Code Generator for Energy-Efficient Wavefront Parallelization of Uniform Dependence Computations. IEEE Trans. Parallel Distrib. Syst. 29(9): 1923-1936 (2018)- [i5]Waruna Ranasinghe, Nirmal Prajapati, Tomofumi Yuki, Sanjay Rajopadhye:
PCOT: Cache Oblivious Tiling of Polyhedral Programs. CoRR abs/1802.00166 (2018) - [i4]Nirmal Prajapati, Sanjay Rajopadhye, Hristo Djidjev:
Analytical Cost Metrics : Days of Future Past. CoRR abs/1802.01957 (2018) - 2017
- [c70]Gaël Deest, Tomofumi Yuki, Sanjay Rajopadhye, Steven Derrien:
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. FPL 2017: 1-8 - [c69]Nirmal Prajapati, Waruna Ranasinghe, Sanjay V. Rajopadhye, Rumen Andonov, Hristo Djidjev, Tobias Grosser:
Simple, Accurate, Analytical Time Modeling and Optimal Tile Size Selection for GPGPU Stencils. PPOPP 2017: 163-177 - [i3]Nirmal Prajapati, Sanjay Rajopadhye, Hristo Djidjev, Nandakishore Santhi, Tobias Grosser, Rumen Andonov:
Accelerator Codesign as Non-Linear Optimization. CoRR abs/1712.04892 (2017) - 2016
- [i2]Tian Jin, Nirmal Prajapati, Waruna Ranasinghe, Guillaume Iooss, Yun Zou, Sanjay Rajopadhye, David G. Wonnacott:
Hybrid Static/Dynamic Schedules for Tiled Polyhedral Programs. CoRR abs/1610.07236 (2016) - 2015
- [j26]Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton, Alexandre Cornu, Dominique Lavenier:
Combining execution pipelines to improve parallel implementation of HMMER on FPGA. Microprocessors and Microsystems - Embedded Hardware Design 39(7): 457-470 (2015) - [c68]Yun Zou, Sanjay V. Rajopadhye:
Automatic Energy Efficient Parallelization of Uniform Dependence Computations. ICS 2015: 373-382 - [c67]Nirmal Prajapati, Waruna Ranasinghe, Vamshi Tandrapati, Rumen Andonov, Hristo Djidjev, Sanjay V. Rajopadhye:
Energy Modeling and Optimization for Tiled Nested-Loop Codes. IPDPS Workshops 2015: 888-895 - 2014
- [c66]Lucas W. Krakow, Louis Rabiet, Yun Zou, Guillaume Iooss, Edwin K. P. Chong, Sanjay Rajopadhye:
Optimizing Dynamic Resource Allocation. ICCS 2014: 1277-1288 - [c65]Guillaume Iooss, Christophe Alias, Sanjay V. Rajopadhye:
On Program Equivalence with Reductions. SAS 2014: 168-183 - 2013
- [c64]Tomofumi Yuki, Sanjay V. Rajopadhye:
Folklore Confirmed: Compiling for Speed = Compiling for Energy. LCPC 2013: 169-184 - [c63]Tomofumi Yuki, Paul Feautrier, Sanjay V. Rajopadhye, Vijay A. Saraswat:
Array dataflow analysis for polyhedral X10 programs. PPOPP 2013: 23-34 - [e1]Sanjay V. Rajopadhye, Michelle Mills Strout:
Languages and Compilers for Parallel Computing, 24th International Workshop, LCPC 2011, Fort Collins, CO, USA, September 8-10, 2011. Revised Selected Papers. Lecture Notes in Computer Science 7146, Springer 2013, ISBN 978-3-642-36035-0 [contents] - [i1]Tomofumi Yuki, Paul Feautrier, Sanjay V. Rajopadhye, Vijay A. Saraswat:
Checking Race Freedom of Clocked X10 Programs. CoRR abs/1311.4305 (2013) - 2012
- [j25]Jean-Marc Jézéquel, Benoît Combemale, Steven Derrien, Clement Guy, Sanjay V. Rajopadhye:
Bridging the chasm between MDE and the world of compilation. Software and Systems Modeling 11(4): 581-597 (2012) - [j24]Lakshminarayanan Renganarayanan, DaeGon Kim, Michelle Mills Strout, Sanjay V. Rajopadhye:
Parameterized loop tiling. ACM Trans. Program. Lang. Syst. 34(1): 3:1-3:41 (2012) - [j23]Hilary E. Brown, Siddharth Suryanarayanan, Sudarshan Natarajan, Sanjay Rajopadhye:
Improving Reliability of Islanded Distribution Systems With Distributed Renewable Energy Resources. IEEE Trans. Smart Grid 3(4): 2028-2038 (2012) - [c62]Yun Zou, Sanjay V. Rajopadhye:
Scan detection and parallelization in "inherently sequential" nested loop programs. CGO 2012: 74-83 - [c61]Tomofumi Yuki, Gautam Gupta, DaeGon Kim, Tanveer Pathan, Sanjay V. Rajopadhye:
AlphaZ: A System for Design Space Exploration in the Polyhedral Model. LCPC 2012: 17-31 - 2011
- [c60]Doug Hains, Zach Cashero, Mark Ottenberg, Wim Bohm, Sanjay V. Rajopadhye:
Improving CUDASW++, a Parallelization of Smith-Waterman for CUDA Enabled Devices. IPDPS Workshops 2011: 490-501 - [c59]Sanjay V. Rajopadhye, Samik Gupta, DaeGon Kim:
Alphabets: An Extended Polyhedral Equational Language. IPDPS Workshops 2011: 656-664 - [c58]V. Basupalli, Tomofumi Yuki, Sanjay V. Rajopadhye, Antoine Morvan, Steven Derrien, Patrice Quinton, David Wonnacott:
ompVerify: Polyhedral Analysis for the OpenMP Programmer. IWOMP 2011: 37-53 - [c57]Antoine Floch, Tomofumi Yuki, Clement Guy, Steven Derrien, Benoît Combemale, Sanjay V. Rajopadhye, Robert B. France:
Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far? MoDELS 2011: 608-622 - 2010
- [c56]Tomofumi Yuki, Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye, Charles Anderson, Alexandre E. Eichenberger, Kevin O'Brien:
Automatic creation of tile size selection models. CGO 2010: 190-199 - [c55]Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton:
Accelerating HMMER on FPGA using parallel prefixes and reductions. FPT 2010: 37-44
2000 – 2009
- 2009
- [j22]Clémentin Tayou Djamégni, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset, Maurice Tchuente:
A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems. J. Parallel Distrib. Comput. 69(1): 1-11 (2009) - [c54]DaeGon Kim, Sanjay V. Rajopadhye:
Efficient Tiled Loop Generation: D-Tiling. LCPC 2009: 293-307 - 2008
- [c53]Nissa Osheim, Michelle Mills Strout, Dave Rostron, Sanjay V. Rajopadhye:
Smashing: Folding Space to Tile through Time. LCPC 2008: 80-93 - [c52]Sanjay V. Rajopadhye, Gautam Gupta, Lakshminarayanan Renganarayanan:
A domain specific interconnect for reconfigurable computing. LCTES 2008: 79-88 - [c51]Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye:
Positivity, posynomials and tile size selection. SC 2008: 55 - 2007
- [j21]Joseph R. Cavallaro, Sanjay V. Rajopadhye, Lothar Thiele, Tobias Noll:
Special Issue on ASAP 2004 Conference. VLSI Signal Processing 49(1): 1-2 (2007) - [c50]K. Nibbelink, Sanjay V. Rajopadhye, Richard McConnell:
0/1 Knapsack on Hardware: A Complete Solution. ASAP 2007: 160-167 - [c49]Gautam Gupta, DaeGon Kim, Sanjay V. Rajopadhye:
Scheduling in the Z-Polyhedral Model. IPDPS 2007: 1-10 - [c48]Lakshminarayanan Renganarayanan, Manjukumar Harthikote-Matha, Rinku Dewri, Sanjay V. Rajopadhye:
Towards Optimal Multi-level Tiling for Stencil Computations. IPDPS 2007: 1-10 - [c47]Lakshminarayanan Renganarayanan, DaeGon Kim, Sanjay V. Rajopadhye, Michelle Mills Strout:
Parameterized tiled loops for free. PLDI 2007: 405-414 - [c46]Gautam Gupta, Sanjay V. Rajopadhye:
The Z-polyhedral model. PPOPP 2007: 237-248 - [c45]DaeGon Kim, Lakshminarayanan Renganarayanan, Dave Rostron, Sanjay V. Rajopadhye, Michelle Mills Strout:
Multi-level tiling: M for the price of one. SC 2007: 51 - [p2]Sanjay V. Rajopadhye, Lakshimarayanan Renganarayana, Gautam Gupta, Michelle Mills Strout:
Computations on Iteration Spaces. The Compiler Design Handbook, 2nd ed. 2007: 15 - 2006
- [c44]DaeGon Kim, Sanjay V. Rajopadhye:
An Improved Systolic Architecture for LU Decomposition. ASAP 2006: 231-238 - [c43]DaeGon Kim, Gautam Gupta, Sanjay V. Rajopadhye:
On Control Signals for Multi-Dimensional Time. LCPC 2006: 141-155 - [c42]Gautam Gupta, Sanjay V. Rajopadhye:
Simplifying reductions. POPL 2006: 30-41 - 2005
- [c41]Sanjay V. Rajopadhye, Kolin Paul:
A 1.5-D Architecture for Back-Propagation Training. ERSA 2005: 112-118 - [c40]Lakshminarayanan Renganarayanan, U. Ramakrishna, Sanjay V. Rajopadhye:
Combined ILP and Register Tiling: Analytical Model and Optimization Framework. LCPC 2005: 244-258 - 2004
- [c39]Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye:
A Geometric Programming Framework for Optimal Multi-Level Tiling. SC 2004: 18 - 2003
- [j20]Rumen Andonov, Stephan Balev, Sanjay V. Rajopadhye, Nicola Yanev:
Optimal Semi-Oblique Tiling. IEEE Trans. Parallel Distrib. Syst. 14(9): 944-960 (2003) - [c38]Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye:
Switched Memory Architectures-Moving Beyond Systolic Arrays. ASAP 2003: 28-39 - 2002
- [c37]Sanjay V. Rajopadhye, Steven Derrien:
Energy/Power Estimation of Regular Processor Arrays. ISSS 2002: 50-55 - [c36]Gautam Gupta, Sanjay V. Rajopadhye, Patrice Quinton:
Scheduling reductions on realistic machines. SPAA 2002: 117-126 - [p1]Sanjay V. Rajopadhye:
Dependence Analysis and Parallelizing Transformations. The Compiler Design Handbook 2002: 329-372 - 2001
- [c35]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combining Instruction and Loop Level Parallelism for FPGAs. FCCM 2001: 273-282 - [c34]Steven Derrien, Sanjay V. Rajopadhye:
Loop Tiling for Reconfigurable Accelerators. FPL 2001: 398-408 - [c33]Manju Manjunathaiah, Graham M. Megson, Sanjay V. Rajopadhye, Tanguy Risset:
Uniformization of Affine Dependance Programs for Parallel Embedded System Design. ICPP 2001: 205-213 - [c32]David Cachera, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset:
Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms. IPDPS 2001: 148 - [c31]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS 2001: 165-170 - [c30]Rumen Andonov, Stephan Balev, Sanjay V. Rajopadhye, Nicola Yanev:
Optimal semi-oblique tiling. SPAA 2001: 153-162 - 2000
- [j19]Rumen Andonov, Vincent Poirriez, Sanjay V. Rajopadhye:
Unbounded knapsack problem: Dynamic programming revisited. European Journal of Operational Research 123(2): 394-407 (2000) - [j18]Fabien Quilleré, Sanjay V. Rajopadhye, Doran Wilde:
Generation of Efficient Nested Loops from Polyhedra. International Journal of Parallel Programming 28(5): 469-498 (2000) - [j17]Clémentin Tayou Djamégni, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset:
Derivation of systolic algorithms for the algebraic path problem by recurrence transformations. Parallel Computing 26(11): 1429-1445 (2000) - [j16]Fabien Quilleré, Sanjay V. Rajopadhye:
Optimizing memory usage in the polyhedral model. ACM Trans. Program. Lang. Syst. 22(5): 773-815 (2000) - [c29]Scott Bowden, Doran Wilde, Sanjay V. Rajopadhye:
Quadratic Control Signals in Linear Systolic Arrays. ASAP 2000: 268-275 - [c28]Steven Derrien, Sanjay V. Rajopadhye:
FCCMS and the Memory Wall. FCCM 2000: 329-330 - [c27]Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC 2000: 155-159
1990 – 1999
- 1999
- [c26]Sanjay V. Rajopadhye, Claude Tadonki, Tanguy Risset:
The Algebraic Path Problem Revisited. Euro-Par 1999: 698-707 - 1998
- [c25]Rumen Andonov, Sanjay V. Rajopadhye, Nicola Yanev:
Optimal Orthogonal Tiling. Euro-Par 1998: 480-490 - [c24]Stephan Balev, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset:
Linear Programming Models for Scheduling Systems of Affine Recurrence Equations - A Comparative Study. SPAA 1998: 250-258 - 1997
- [j15]Rumen Andonov, Sanjay V. Rajopadhye:
Optimal Orthogonal Tiling of 2-D Iterations. J. Parallel Distrib. Comput. 45(2): 159-165 (1997) - [j14]Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset:
On Manipulating Z-Polyhedra Using a Canonical Representation. Parallel Processing Letters 7(2): 181-194 (1997) - [j13]Doran Wilde, Sanjay V. Rajopadhye:
Memory Reuse Analysis in the Polyhedral Model. Parallel Processing Letters 7(2): 203-215 (1997) - [j12]Patrick M. Lenders, Sanjay V. Rajopadhye:
Multirate VLSI Arrays and Their Synthesis. IEEE Trans. Computers 46(5): 515-529 (1997) - [j11]Rumen Andonov, Sanjay V. Rajopadhye:
Knapsack on VLSI: from Algorithm to Optimal Circuit. IEEE Trans. Parallel Distrib. Syst. 8(6): 545-561 (1997) - 1996
- [j10]Virginia Mary Lo, Sanjay V. Rajopadhye, Jan Arne Telle, Xiaoxiong Zhong:
Parallel Divide and Conquer on Meshes. IEEE Trans. Parallel Distrib. Syst. 7(10): 1049-1058 (1996) - [c23]Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset:
Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains. ASAP 1996: 391-401 - [c22]Doran Wilde, Sanjay V. Rajopadhye:
Memory Reuse Analysis in the Polyhedral Model. Euro-Par, Vol. I 1996: 389-397 - [c21]Rumen Andonov, Hafid Bourzoufi, Sanjay V. Rajopadhye:
Two-dimensional orthogonal tiling: from theory to practice. HiPC 1996: 225-231 - [c20]Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov:
A Regular VLSI Array for an Irregular Algorithm. IRREGULAR 1996: 195-200 - 1995
- [j9]Rumen Andonov, Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde:
A Shift Registered-Based Systolic Array for the Unbounded Knapsack Problem. Parallel Processing Letters 5: 251-262 (1995) - [c19]Doran Wilde, Sanjay V. Rajopadhye:
The naive execution of affine recurrence equations. ASAP 1995: 1-12 - [c18]Patrick M. Lenders, Sanjay V. Rajopadhye:
Synthesis of Multirate VLSI Arrays. ASAP 1995: 310-321 - [c17]Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde:
Deriving Imperative Code from Functional Programs. FPCA 1995: 36-44 - [c16]Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde:
On deriving data parallel code from a functional program. IPPS 1995: 766-772 - 1994
- [c15]Rumen Andonov, Sanjay V. Rajopadhye:
A sparse knapsack algo-tech-cuit and its synthesis. ASAP 1994: 302-313 - [c14]Rumen Andonov, Sanjay V. Rajopadhye:
Optimal Tile Sizing. CONPAR 1994: 701-712 - [c13]Rumen Andonov, Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde:
Pure Systolic Array for a Class of Dynamic Dependency Recurrences. Parcella 1994: 207-214 - 1993
- [j8]Sanjay Rajopadhye:
An improved systolic algorithm for the algebraic path problem. Integration 14(3): 279-296 (1993) - [c12]Rumen Andonov, Sanjay Rajopadhye:
An optimal algo-tech-cuit for the knapsack problem. ASAP 1993: 548-559 - [c11]Sanjay V. Rajopadhye, Manjunath Muddarangegowda:
Parallel Assignment, Reduction and Communication for Data Parallel Programming. PPSC 1993: 850-853 - [c10]Sanjay V. Rajopadhye:
Analysis of Affine Communication Specifications. SPDP 1993: 530-537 - 1992
- [j7]Xiaoxiong Zhong, Sanjay V. Rajopadhye:
Quasi-Linear allocation functions for efficient array design. VLSI Signal Processing 4(2-3): 97-110 (1992) - [j6]Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong:
Systematic generation of linear allocation functions in systolic array design. VLSI Signal Processing 4(4): 279-293 (1992) - [c9]Björn Lisper, Sanjay V. Rajopadhye:
Reasoning about Permutations in Regular Arrays. Designing Correct Circuits 1992: 139-157 - [c8]Xiaoxiong Zhong, Sanjay V. Rajopadhye, Virginia Mary Lo:
Parallel Implementation of Divide-and-Conquer Algorithms on Binary de Bruijn Networks. IPPS 1992: 103-107 - 1991
- [j5]Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Bill Nitzberg, Jan Arne Telle, Xiaoxiong Zhong:
OREGAMI: Tools for mapping parallel computations to parallel architectures. International Journal of Parallel Programming 20(3): 237-270 (1991) - [c7]Sanjay V. Rajopadhye:
An improved systolic algorithm for the algebraic path problem. Algorithms and Parallel VLSI Architectures 1991: 187-198 - [c6]Xiaoxiong Zhong, Sanjay V. Rajopadhye:
Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions. PARLE (1) 1991: 219-236 - 1990
- [j4]Sanjay V. Rajopadhye, Richard M. Fujimoto:
Automating the design of systolic arrays. Integration 9(3): 225-242 (1990) - [j3]Sanjay V. Rajopadhye, Richard Fujimoto:
Synthesizing systolic arrays from recurrence equations. Parallel Computing 14(2): 163-189 (1990) - [c5]Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Jan Arne Telle:
OREGAMI: Software Tools for Mapping Parallel Computations to Parallel Architectures. ICPP (2) 1990: 88-92 - [c4]Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Jan Arne Telle:
Mapping Divide-and-Conquer Algorithms to Parallel Architectures. ICPP (3) 1990: 128-135
1980 – 1989
- 1989
- [j2]Sanjay V. Rajopadhye:
Synthesizing Systolic Arrays with Control Signals from Recurrence Equations. Distributed Computing 3(2): 88-105 (1989) - 1987
- [c3]Sanjay V. Rajopadhye, Richard Fujimoto:
Systolic Array Synthesis by Static Analysis of Program Dependencies. PARLE (1) 1987: 295-310 - 1986
- [c2]Sanjay V. Rajopadhye, S. Purushothaman, Richard Fujimoto:
On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies. FSTTCS 1986: 488-503 - [c1]Sanjay V. Rajopadhye, Prakash Panangaden:
Verification of Systolic Arrays: A Stream Function Approach. ICPP 1986: 773-775 - 1985
- [j1]Sanjay V. Rajopadhye, P. A. Subrahmanyam:
Formal semantics for a symbolic IC design technique: Examples and applications. Integration 3(1): 13-32 (1985)
Coauthor Index
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