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2010 – today
- 2019
[j21]Sudip Shekhar
, Rajesh Inti, James E. Jaussi, Tzu-Chien Hsueh, Bryan Casper:
A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR. J. Solid-State Circuits 54(6): 1669-1681 (2019)- [j20]Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi, Sudip Shekhar:
A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter. IEEE Trans. on Circuits and Systems 66-I(1): 43-53 (2019) - [j19]Ahmed El Sayed, Amit K. Mishra, Abdelrahman H. Ahmed, Amir Hossein Masnadi Shirazi, Sang-Pil Woo, Yang-Seok Choi, Shahriar Mirabbasi, Sudip Shekhar:
A Hilbert Transform Equalizer Enabling 80 MHz RF Self-Interference Cancellation for Full-Duplex Receivers. IEEE Trans. on Circuits and Systems 66-I(3): 1153-1165 (2019) - [j18]Spoorthi Nayak, Abdelrahman H. Ahmed, Ahmad Sharkia, Ajith Sivadhasan Ramani, Shahriar Mirabbasi, Sudip Shekhar:
A 10-Gb/s -18.8 dBm Sensitivity 5.7 mW Fully-Integrated Optoelectronic Receiver With Avalanche Photodetector in 0.13- $\mu$ m CMOS. IEEE Trans. on Circuits and Systems 66-I(8): 3162-3173 (2019) - [j17]Erfan Ghaderi, Ajith Sivadhasan Ramani, Arya A. Rahimi, Deukhyoun Heo, Sudip Shekhar, Subhanshu Gupta:
An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers. IEEE Trans. on Circuits and Systems 66-I(9): 3296-3306 (2019) - [j16]Chen Yuan, Sudip Shekhar:
A Supply-Noise-Insensitive Digitally-Controlled Oscillator. IEEE Trans. on Circuits and Systems 66-I(9): 3414-3422 (2019) - [j15]Ajith Sivadhasan Ramani, Spoorthi Nayak, Sudip Shekhar:
A Differential Push-Pull Voltage Mode VCSEL Driver in 65-nm CMOS. IEEE Trans. on Circuits and Systems 66-I(11): 4147-4157 (2019) - [c21]Abdelrahman H. Ahmed, Daihyun Lim, Abdellatif Elmoznine, Yangjin Ma, Tam N. Huynh, Christopher Williams, Leonardo Vera, Yang Liu, Ruizhi Shi, Matthew Streshinsky, Ari Novack, Ran Ding, Rick Younce, Rafid A. Sukkar, Jose Roman, Michael Hochberg, Sudip Shekhar, Alexander V. Rylyakov:
A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter. ISSCC 2019: 484-486 - 2018
- [j14]Amir Nikpaik, Amir Hossein Masnadi Shirazi, Abdolreza Nabavi, Shahriar Mirabbasi, Sudip Shekhar:
A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS. J. Solid-State Circuits 53(2): 389-403 (2018) - [j13]Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar:
A Type-I Sub-Sampling PLL With a 100×100 µm2 Footprint and -255-dB FOM. J. Solid-State Circuits 53(12): 3553-3564 (2018) - [c20]Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar:
A 0.01mm2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with -254dB FOM. ISSCC 2018: 256-258 - 2017
- [j12]Gautham Prasad, Lutz Lampe, Sudip Shekhar:
Digitally Controlled Analog Cancellation for Full Duplex Broadband Power Line Communications. IEEE Trans. Communications 65(10): 4419-4432 (2017) - [c19]Sudip Shekhar, Tod Dickson:
Session 2 - Wireline techniques for advanced modulation schemes. CICC 2017: 1 - [c18]Gautham Prasad, Lutz Lampe, Sudip Shekhar:
Analog interference cancellation for full-duplex broadband power line communications. ISPLC 2017: 1-6 - [c17]Hasan Afkhami Ardakani, Amir Hossein Masnadi Shirazi, Sudip Shekhar, Shahriar Mirabbasi:
A low-power temperature sensing system for implantable biomedical applications. NEWCAS 2017: 377-380 - 2016
- [j11]Amir Hossein Masnadi Shirazi, Amir Nikpaik, Reza Molavi, Sam Lightbody, Hormoz Djahanshahi, Mazhareddin Taghivand, Shahriar Mirabbasi, Sudip Shekhar:
On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise. J. Solid-State Circuits 51(5): 1210-1222 (2016) - [j10]Gautham Prasad, Lutz Lampe, Sudip Shekhar:
In-Band Full Duplex Broadband Power Line Communications. IEEE Trans. Communications 64(9): 3915-3931 (2016) - [c16]Mohammed W. AlTaha, Spoorthi Nayak, Hasitha Jayatilleka, Sudip Shekhar, Shahriar Mirabbasi:
Silicon-photonic devices: Electronic control and stabilization. CCECE 2016: 1-4 - [c15]Gautham Prasad, Lutz Lampe, Sudip Shekhar:
Enhancing transmission efficiency of broadband PLC systems with In-Band Full Duplexing. ISPLC 2016: 46-51 - 2015
- [c14]Amir Nikpaik, Abdolreza Nabavi, Amir Hossein Masnadi Shirazi, Sudip Shekhar, Shahriar Mirabbasi:
A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM. CICC 2015: 1-4 - [c13]Ahmad Sharkia, Sankaran Aniruddhan, Sudip Shekhar, Shahriar Mirabbasi:
A high-performance, yet simple to design, digital-friendly type-I PLL. CICC 2015: 1-4 - [c12]Rajesh Inti, Sudip Shekhar, Ganesh Balamurugan, James E. Jaussi, Clark Roberts, Tzu-Chien Hsueh, Bryan Casper:
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS. VLSIC 2015: 346- - [c11]Sudip Shekhar, Rajesh Inti, James E. Jaussi, Tzu-Chien Hsueh, Bryan Casper:
A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR. VLSIC 2015: 350- - 2014
- [j9]Tawfiq Musah, James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Gokce Keskin, Sudip Shekhar, Joseph T. Kennedy, Shreyas Sen, Rajesh Inti, Mozhgan Mansuri, Michael Leddige, Bryce Horine, Clark Roberts, Randy Mooney, Bryan Casper:
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. J. Solid-State Circuits 49(12): 3079-3090 (2014) - 2013
- [j8]Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. J. Solid-State Circuits 48(12): 3229-3242 (2013) - [c10]Sudip Shekhar, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper:
Design considerations for low-power receiver front-end in high-speed data links. CICC 2013: 1-8 - [c9]Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper:
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. ISSCC 2013: 402-403 - 2011
- [j7]Sankaran Aniruddhan, Sudip Shekhar, David J. Allstot:
A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing. IEEE Trans. on Circuits and Systems 58-I(5): 860-867 (2011) - [j6]Sudip Shekhar, Daibashish Gangopadhyay, Eum Chan Woo, David J. Allstot:
A 2.4-GHz Extended-Range Type-I SigmaDelta Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise. IEEE Trans. on Circuits and Systems 58-II(8): 472-476 (2011) - 2010
- [j5]Frank O'Mahony, James E. Jaussi, Joseph T. Kennedy, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. J. Solid-State Circuits 45(12): 2828-2837 (2010) - [c8]Heng-Chia Hsu, Kaushik Dasgupta, Nathan M. Neihart, Sudip Shekhar, Jeffrey S. Walling, David J. Allstot:
U-shaped slow-wave transmission lines in 0.18μm CMOS. ISCAS 2010: 1296-1299 - [c7]Daibashish Gangopadhyay, Sudip Shekhar, Jeffrey S. Walling, David J. Allstot:
A 1.6 mW 5.4 GHz transformer-feedback gm-boosted current-reuse LNA in 0.18/μm CMOS. ISCAS 2010: 1635-1638 - [c6]Frank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, Clark Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. ISSCC 2010: 156-157
2000 – 2009
- 2009
- [j4]Sudip Shekhar, Ganesh Balamurugan, David J. Allstot, Mozhgan Mansuri, James E. Jaussi, Randy Mooney, Joseph T. Kennedy, Bryan Casper, Frank O'Mahony:
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver. IEEE Trans. on Circuits and Systems 56-I(8): 1818-1829 (2009) - 2008
- [j3]Sudip Shekhar, Jeffrey S. Walling, Sankaran Aniruddhan, David J. Allstot:
CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits. J. Solid-State Circuits 43(5): 1177-1186 (2008) - [j2]Jeffrey S. Walling, Sudip Shekhar, David J. Allstot:
Wideband CMOS Amplifier Design: Time-Domain Considerations. IEEE Trans. on Circuits and Systems 55-I(7): 1781-1793 (2008) - [c5]Mozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Sudip Shekhar, Randy Mooney, Bryan Casper:
Strong injection locking of low-Q LC oscillators. CICC 2008: 699-702 - [c4]Frank O'Mahony, Sudip Shekhar, Mozhgan Mansuri, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Bryan Casper, David J. Allstot, Randy Mooney:
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. ISSCC 2008: 452-453 - 2006
- [c3]Sankaran Aniruddhan, Sudip Shekhar, David J. Allstot:
A delay generation technique for fast-locking frequency synthesizers. ISCAS 2006 - [c2]Sudip Shekhar, Sankaran Aniruddhan, David J. Allstot:
A fully-differential CMOS Clapp VCO for IEEE 802.11a applications. ISCAS 2006 - 2005
- [j1]Wei Zhuo, Xiaoyong Li, Sudip Shekhar, Sherif H. K. Embabi, José Pineda de Gyvez, David J. Allstot, Edgar Sánchez-Sinencio:
A capacitor cross-coupled common-gate low-noise amplifier. IEEE Trans. on Circuits and Systems 52-II(12): 875-879 (2005) - 2004
- [c1]Min Chu, Sudip Shekhar, David J. Allstot, Tarun Kanti Bhattacharyya:
Design considerations for anti-phase injected quadrature voltage controlled oscillators. ICECS 2004: 25-28
Coauthor Index
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