Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDM. H. Vasantha
Person information
- affiliation: National Institute of Technology Goa, India
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[j20]K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin:
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 12: 50126-50136 (2024)- 2023
- [j19]K. G. Shreeharsha
, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar:
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 11: 123577-123588 (2023) - [c44]R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni:
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. ISCAS 2023: 1-5 - [c43]Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran:
Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES 2023: 287-291 - [c42]Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi:
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID 2023: 1-6 - 2022
- [c41]Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha:
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS 2022: 3428-3432 - 2021
- [j18]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha:
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9: 108119-108130 (2021) - [j17]P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithin Kumar:
$\pm \, 0.5$ V, 254 $\upmu $W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit. Circuits Syst. Signal Process. 40(5): 2114-2134 (2021) - [j16]Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi:
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. Integr. 81: 268-279 (2021) - [j15]P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithin Kumar:
A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1748-1752 (2021) - [c40]Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni:
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. ISCAS 2021: 1-5 - [c39]K. G. Shreeharsha, Charudatta Korde, M. H. Vasantha, Y. B. Nithin Kumar:
Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm. iSES 2021: 127-130 - [c38]Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha:
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. ISVLSI 2021: 19-24 - [c37]Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini:
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSID 2021: 252-257 - 2020
- [j14]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8: 183367-183377 (2020) - [j13]Siddharth Rajkumar Kala, Sushma Chandaka, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra, Edoardo Bonizzoni:
6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process. IET Circuits Devices Syst. 14(3): 340-346 (2020) - [j12]Vivek Sharma, Nithin Kumar Y. B., Vasantha M. H.:
IET Circuits, Devices & Systems. IET Circuits Devices Syst. 14(6): 881-891 (2020) - [j11]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14(16): 4110-4121 (2020) - [j10]Bipul Boro, Karri Manikantta Reddy, Nithin Y. B. Kumar, M. H. Vasantha:
Approximate radix-8 Booth multiplier for low power and high speed applications. Microelectron. J. 101: 104816 (2020) - [j9]Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha:
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. SN Comput. Sci. 1(6): 310 (2020) - [j8]Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. IEEE Trans. Circuits Syst. 67-II(12): 2918-2922 (2020) - [j7]Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi:
Design of Approximate Booth Squarer for Error-Tolerant Computing. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1230-1241 (2020) - [c36]Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha:
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. iSES 2020: 167-170 - [c35]Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.:
A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES 2020: 216-220 - [c34]Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini:
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. iSES 2020: 277-280 - [c33]Suraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.:
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. ISVLSI 2020: 48-53 - [c32]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha:
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS 2020: 138-141 - [c31]Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., Vasantha M. H., Ramnath Kini:
A Wideband 12 Phase Ring Oscillator for 5G Applications. MWSCAS 2020: 885-888
2010 – 2019
- 2019
- [j6]S. Rekha, Vasantha Moodabettu Harishchandra, Tonse Laxminidhi:
Ultra-low voltage, power efficient continuous-time filters in 180 nm CMOS technology. IET Circuits Devices Syst. 13(7): 988-997 (2019) - [c30]Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Process Corner Calibration for Standard Cell Based Flash ADC. iSES 2019: 195-200 - [c29]Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra:
Two-Step Flash ADC Using Standard Cell Based Flash ADCs. iSES 2019: 292-295 - [c28]Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha:
An Asynchronous Analog to Digital Converter for Video Camera Applications. ISVLSI 2019: 175-180 - [c27]Prasad Vernekar, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. ISVLSI 2019: 627-631 - [c26]Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.:
Design and Analysis of Energy Efficient Reversible Logic based Full Adder. MWSCAS 2019: 339-342 - [c25]P. S. Veerendranath, Vivek Sharma, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications. TENCON 2019: 658-661 - 2018
- [j5]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
An energy-efficient fault-aware core mapping in mesh-based network on chip systems. J. Netw. Comput. Appl. 105: 79-87 (2018) - [j4]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
Hardware implementation of fault tolerance NoC core mapping. Telecommun. Syst. 68(4): 621-630 (2018) - [j3]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures. Wirel. Pers. Commun. 100(2): 213-225 (2018) - [c24]Purnima Kalekar, Prasad Vernekar, M. H. Vasantha, Y. B. Nithin Kumar, Edoardo Bonizzoni:
A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications. IEEE SENSORS 2018: 1-4 - [c23]Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni:
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS 2018: 1-5 - [c22]Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha:
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. iSES 2018: 6-10 - [c21]Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar:
Design of Area-Power-Delay Efficient Square Root Carry Select Adder. iSES 2018: 80-85 - [c20]Anirudha Pandey, Karri Manikantta Reddy, Praveen Yadav, Nithin Y. B. Kumar, M. H. Vasantha:
Design and Analysis of Approximate Multipliers for Error-Tolerant Applications. iSES 2018: 94-97 - [c19]Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. ISVLSI 2018: 164-169 - [c18]Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha:
Performance Enhancement of Split Length Compensated Operational Amplifiers. ISVLSI 2018: 608-613 - [c17]Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi:
Design of Approximate Dividers for Error Tolerant Applications. MWSCAS 2018: 496-499 - [c16]Praveen Yadav, Anirudha Pandey, Karri Manikantta Reddy, K. J. Ravi Prasad, M. H. Vasantha, Nithin Y. B. Kumar:
Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs. MWSCAS 2018: 500-503 - [c15]Dhavala Shashidhar, Vivek Sharma, G. R. Prashanth, Nithin Y. B. Kumar, M. H. Vasantha:
Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell. TENCON 2018: 1768-1773 - [c14]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON 2018: 1813-1817 - [c13]P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni:
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. VLSID 2018: 214-219 - 2017
- [j2]Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
System level fault-tolerance core mapping and FPGA-based verification of NoC. Microelectron. J. 70: 16-26 (2017) - [j1]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
High-performance and energy-efficient fault-tolerance core mapping in NoC. Sustain. Comput. Informatics Syst. 16: 1-10 (2017) - [c12]Anoop D, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
High Performance Sense Amplifier Based Flip Flop for Driver Applications. iNIS 2017: 129-132 - [c11]Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI 2017: 585-588 - [c10]Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin:
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. ISVLSI 2017: 589-593 - [c9]S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI 2017: 600-603 - 2016
- [c8]Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha:
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT 2016: 35:1-35:6 - [c7]Saurabh B. Kaurati, Nithin Y. B. Kumar, Shivnarayan Patidar, M. H. Vasantha:
Design and Implementation of Tunable Bandpass Filter for Biomedical Applications. iNIS 2016: 43-46 - [c6]S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin:
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. ISVLSI 2016: 105-109 - [c5]B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin:
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. ISVLSI 2016: 146-151 - [c4]S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI 2016: 343-348 - [c3]A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha:
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSID 2016: 202-206 - 2015
- [c2]Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha:
Low power, high speed error tolerant multiplier using approximate adders. VDAT 2015: 1-6 - 2012
- [c1]Vasantha M. H., Tonse Laxminidhi:
0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process. ISED 2012: 33-37
Coauthor Index
aka: Nithin Y. B. Kumar
aka: Nithin Kumar Y. B.
aka: Kumar Y. B. Nithin
aka: Y. B. Nithin Kumar
aka: Siddharth Rajkumar Kala
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:47 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
