Google
Google Scholar
MS Academic
CiteSeerX
CORE
Semantic ScholarSrikanth Venkataraman
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2010 – today
- 2019
[j11]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24(4): 42:1-42:19 (2019)- [c52]
Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE 2019: 1022-1027 - [c51]
Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman:
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. VTS 2019: 1-6 - 2018
- [c50]
Naixing Wang, Irith Pomeranz, Brady Benware, M. EnamulAmyeen, Srikanth Venkataraman:
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests. DFT 2018: 1-6 - [c49]
Irith Pomeranz, Srikanth Venkataraman:
Interconnect-aware tests to complement gate-exhaustive tests. ETS 2018: 1-6 - 2017
- [j10]
Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Test Modification for Reduced Volumes of Fail Data. ACM Trans. Design Autom. Electr. Syst. 22(4): 67:1-67:17 (2017) - [j9]
Shraddha Bodhe, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. IEEE Trans. VLSI Syst. 25(4): 1497-1505 (2017) - [c48]
Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen:
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. ITC 2017: 1-9 - 2016
- [j8]
Shraddha Bodhe, Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
Diagnostic Fail Data Minimization Using an N-Cover Algorithm. IEEE Trans. VLSI Syst. 24(3): 1198-1202 (2016) - [c47]
M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction. ATS 2016: 138-143 - [c46]
M. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma:
A novel diagnostic test generation methodology and its application in production failure isolation. ITC 2016: 1-10 - [c45]
Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman:
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. VTS 2016: 1-6 - 2014
- [c44]
Bo Yao, Irith Pomeranz, Srikanth Venkataraman, Enamul Amyeen:
Built-in generation of functional broadside tests considering primary input constraints. ACM Great Lakes Symposium on VLSI 2014: 237-238 - 2013
- [c43]
Said Hamdioui, Davide Appello, Arnaud Grasset, Xinli Gu, Bram Kruseman, Riccardo Mariani, Hermann Obermeir, Srikanth Venkataraman:
Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes? ETS 2013: 1 - 2012
- [c42]
Srikanth Venkataraman, Nagesh Tamarapalli:
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. VLSI Design 2012: 16-17 - 2011
- [c41]
Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan:
Logic BIST silicon debug and volume diagnosis methodology. ITC 2011: 1-10 - 2010
- [c40]
Dongok Kim, Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman:
Defect diagnosis based on DFM guidelines. VTS 2010: 206-211
2000 – 2009
- 2009
- [c39]
Enamul Amyeen, Srikanth Venkataraman, Mun Wai Mak:
Microprocessor system failures debug and fault isolation methodology. ITC 2009: 1-10 - [c38]
Richard McLaughlin, Srikanth Venkataraman, Carlston Lim:
Automated Debug of Speed Path Failures Using Functional Tests. VTS 2009: 91-96 - 2008
- [c37]
Dongok Kim, Irith Pomeranz, Enamul Amyeen, Srikanth Venkataraman:
Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects. ATS 2008: 217-220 - [c36]
Srikanth Venkataraman, Nagesh Tamarapalli:
DFM / DFT / SiliconDebug / Diagnosis. VLSI Design 2008: 5-6 - [c35]
King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman:
Diagnosis of Scan Clock Failures. VTS 2008: 67-72 - 2007
- [j7]
Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman:
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1700-1712 (2007) - [c34]
Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian:
Making Manufacturing Work For You. DAC 2007: 107-108 - [c33]
Srikanth Venkataraman:
DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield. ISQED 2007: 5 - [c32]
Srikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak:
Quality Driven Manufacturing and SOC Designs. ISQED 2007: 5 - [c31]
Dongok Kim, Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau:
Testing for systematic defects based on DFM guidelines. ITC 2007: 1-10 - [c30]
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang:
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. VTS 2007: 231-238 - 2006
- [j6]
Ruifeng Guo, Srikanth Venkataraman:
An algorithmic technique for diagnosis of faulty scan chains. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1861-1868 (2006) - [j5]
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. VLSI Syst. 14(7): 763-776 (2006) - [c29]
Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman:
Improving Precision Using Mixed-level Fault Diagnosis. ITC 2006: 1-10 - [c28]
David Abercrombie, Bernd Koenemann, Nagesh Tamarapalli, Srikanth Venkataraman:
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. VLSI Design 2006: 14 - [c27]
Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman:
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. VTS 2006: 66-71 - [c26]
Bharath Seshadri, Xiaoming Yu, Srikanth Venkataraman:
Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification. VTS 2006: 380-385 - [c25]
Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, Enamul Amyeen, Sudhakar M. Reddy:
Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS 2006: 392-399 - 2005
- [c24]
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE 2005: 996-1001 - [c23]
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Fault Diagnosis and Fault Model Aliasing. ISVLSI 2005: 206-211 - [c22]
Srikanth Venkataraman:
Achieving higher yield through diagnosis? ITC 2005: 2 - [c21]
Zoran Stanojevic, Ruifeng Guo, Subhasish Mitra, Srikanth Venkataraman:
Enabling yield analysis with X-compact. ITC 2005: 9 - 2004
- [c20]
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri:
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. DATE 2004: 68-75 - [c19]
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. ITC 2004: 489-497 - [c18]
Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee:
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. ITC 2004: 669-678 - [c17]
Srikanth Venkataraman:
Diagnosis meets Physical Failure Analysis: What is needed to succeed? ITC 2004: 1442 - [c16]
Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen:
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design 2004: 475-480 - [c15]
Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo:
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. VTS 2004: 23-30 - [c14]
Debashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran:
Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application. VTS 2004: 97-102 - 2003
- [c13]
Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. VTS 2003: 351-358 - 2001
- [j4]
Srikanth Venkataraman, Scott Brady Drummonds:
Poirot: Applications of a Logic Fault Diagnosis Tool. IEEE Design & Test of Computers 18(1): 19-30 (2001) - [j3]
Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty:
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001) - [c12]
Ruifeng Guo, Srikanth Venkataraman:
A technique for fault diagnosis of defects in scan chains. ITC 2001: 268-277 - [c11]
Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar:
On Diagnosing Path Delay Faults in an At-Speed Environment. VTS 2001: 28-33 - 2000
- [c10]
Srikanth Venkataraman, Scott Brady Drummonds:
POIROT: a logic fault diagnosis tool and its applications. ITC 2000: 253-262 - [c9]
Srikanth Venkataraman, Scott Brady Drummonds:
A Technique for Logic Fault Diagnosis of Interconnect Open Defects. VTS 2000: 313-318
1990 – 1999
- 1999
- [c8]
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs:
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. VTS 1999: 58-63 - 1998
- [c7]
Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel:
Diagnostic Simulation of Sequential Circuits Using Fault Sampling. VLSI Design 1998: 476-481 - 1997
- [c6]
Srikanth Venkataraman, W. Kent Fuchs:
A deductive technique for diagnosis of bridging faults. ICCAD 1997: 562-567 - [c5]
Srikanth Venkataraman, W. Kent Fuchs:
Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-Tracing. ITC 1997: 878-886 - [c4]
Srikanth Venkataraman, W. Kent Fuchs:
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits. VLSI Design 1997: 381-387 - 1996
- [j2]
Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman:
Diagnostic simulation of stuck-at faults in combinational circuits. J. Electronic Testing 8(1): 87-97 (1996) - [c3]
Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel:
Partial Scan Design Based on Circuit State Information. DAC 1996: 807-812 - [c2]
Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs:
Dynamic diagnosis of sequential circuits based on stuck-at faults. VTS 1996: 198-203 - 1995
- [j1]
Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois:
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. Computers 44(2): 223-233 (1995) - [c1]
Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel:
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138
Coauthor Index
Enamul Amyeen
aka: M. Enamul Amyeen
aka: M. Enamul Amyeen
last updated on 2019-08-08 21:22 CEST by the dblp team
data released under the ODC-BY 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
the dblp computer science bibliography is funded by:
